JPS6095796A - Sample and hold circuit - Google Patents

Abstract

PURPOSE:To keep the holding potential at an accurate level by providing a capacitor and a switch in order to suppress the variation of the electric charge which is charged by a holding capacitor in a process when a sampling period is switched to a holding period. CONSTITUTION:A switch 12 is closed at the side of a potential E2 in a sample period and at the side of a holding period respectively in response to a sampling pulse 12 which is produced by a sampling pulse generator 7. In the same way, a switch S3 is closed at the side of a potential E4 in a sampling period and at the side of a potential E5 in a holding period respectively. Therefore the variation degree DELTAQ of the electric charge which is charged by a holding capacitor C1 is displayed at a capacity C5 of the capacitor. Thus the variation degree DELTAV of the holding potential appearing at an output terminal 2 is set at ''0'' when the C5 and potentials E4 and E5 are selected so as to satisfy DELTAV=0, i.e., C4(E3-E2)= C5(E4-E5). In such a way, an accurate potential can be kept.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a sample and hold circuit.

In particular, the capacitance H of the hold capacitor is small.

The present invention also relates to a sample and hold circuit suitable for IC implementation.

[Background of the invention]

Generally, sample and hold circuit C is referred to as S&H circuit. ) has a configuration as shown in FIG. In FIG. 1, a signal 10 manually inputted from an input terminal 1 is connected to a switch S1t which is turned on and off in accordance with a sampling pulse 12 generated by a sampling pulse generation circuit 7.
, ) to the output terminal 2. During the period when the switch S1 is on (sampling period), the potential of the input terminal 1 is transmitted as is to the output terminal 2;

During the period when the switch S1 is off (hold period), the hold capacitor C1 is charged with an electric charge corresponding to the potential immediately before the switch S1 is turned off, and the output terminal 2 is kept at the potential immediately before the switch S1 is turned off. Now - as an example, the input signal 10 is the string wave 10 shown in FIG.
When the sampling pulse 12 is the pulse 12 shown in the figure, the signal transmitted to the output terminal 2 is a hold signal 14 (the hold signal 14 that holds the input sine wave 10 at the falling edge of the pulse 12). Figure 5 shows the waveform.)
become that way.

Here, FIGS. 2 and 5 will be used to explain a specific case of a SkH circuit particularly suitable for IC implementation.

The principle of its operation will be explained. FIG. 2 is a circuit diagram showing an example of a specific SkH circuit.

In FIG. 2, an input signal 10 (a sampled and held signal, the sine wave 10 shown in FIG. 5) is input to the input terminal 1.
Terminals 4 and 5 are connected to switching transistors Q5. Q
B and Q6. and a sampling pulse 12 that turns Q7 on and off, respectively.

The I)C voltage 13 corresponding to this is input. now.

When the sampling pulse 12 is at a high level (hereinafter referred to as the sampling period), transistors Q5 to Q8 are on, and transistors Q6 to Q8 are on. Q7 is turned off. In this state, the circuit shown in FIG.

Transistor Q4. This is a negative full feedback amplifier consisting of an emitter follower negative feedback circuit using QB.

A negative feedback type width filter generally has the configuration shown in Fig. 4,
What are its input/output characteristics?

Un = A (J-βva)-m-(11 where U
, 1 input signal 100 +I, I output signal 101 Gain β of AI differential amplifier; feedback rate of feedback circuit 103. If we transform the above equation (1).

So, now β=1. That is A>i.

va 4; v1□ (3) becomes.

However, in the sample period in FIG. 2, the input signal becomes the output signal as it is. still.

The value of the load resistor R1 in the circuit shown in FIG. It is determined based on the balance with the current value. Transistors Q3 and Q4 in this state
The base potential of the transistor is a potential E2 which is the sum of the potential E1 of the output terminal 2 and the base-emitter voltage of the transistor.

Next, referring to FIG. 2, a description will be given of a time when the sampling pulse 12 is at a low level (hereinafter referred to as a hold period). In this case, transistors Q6 and Q7 are turned on, and transistors Q5 and Q8 are turned off. Therefore, the base potential of the transistors Q6 and Q4 is caused by a voltage drop caused by the resistor R1 and the constant current sources 11 and I2.

Pace potential of transistor Q2 (potential of output terminal 2) E
The potential E6 is sufficiently lower than that of 11C.

As a result, the transistors Qs and Qa are turned off, preventing charges from flowing into the hold capacitor C1 from the trace source line. or.

Since the collector current of transistor Q5 is not flowing,
Transistor Q1. Q2 is also in a cutoff state, preventing the charge charged in the hold capacitor C1 from flowing out.

Therefore, during the hold period, the potential E1 of the output terminal 2 is equal to the sampling pulse 1 as explained in FIG.
2 will be held at the potential in front of the surface which becomes low level.

The above is the operating principle of the SkH circuit shown in FIG.

However, in the above SkH circuit.

In actual operation, there are problems as described below. The problems will be explained below.

In general, a transistor has a structure as shown in Fig. 6.

Junction capacitance t between pace and collector and between pace and emitter
C2 and C3 are present. and.

In the circuit 511 of FIG. 2 described above, in the process of switching from the sample period to the hold period.

Pace potential of transistors Q6 and Q4 E2 to E6
It was necessary to descend to For these reasons, the baseline of the transistor Q2 in the S&H circuit shown in FIG. 2 can be isometrically regarded as the equivalent circuit shown in FIG. 6. In FIG. 6, capacitor C4 has the capacitance when the pace-collector capacitance of transistor Q2 and the pace-emitter capacitance of transistor Q3 are connected in series, and the pace-emitter capacitance of transistor Q4 is connected in parallel. This is the capacity when

Here, C2+) is the capacitance between the pace and collector of the transistor C51) is the capacitance between the pace and emitter of the transistor. Potential E1 is the base potential of transistor Q2 immediately before the hold period, potential E2 is the base potential of transistors Q3 and Q4 during the sample period, and potential E
3 is the base potential of transistors Q3 and Q4 during the hold period.

Note that the terminal A of the switch S2 corresponds to the baseline of the transistors Q3 and Q4 in the 511 circuit of FIG.

Therefore, in the 511 circuit described above, in the process of switching from the sample period to the hold period due to the capacitor C4, the charge charged in the hold capacitor C1 changes, and as a result, the hold potential appearing at the output terminal 2 changes to V. Only that will change. This change in bold potential ΔV means that in the equivalent circuit of FIG. 6, one end of capacitor C4 (the one not connected to bold capacitor C1) is set to potential E2 during the sampling period by switch S2, which is switched according to sampling pulse 12. During the hold period, the potential becomes E3.

Here is the capacity of the 011 hold capacitor.

C4: Capacity expressed by the above formula (4).

E2: Transistor during sample period Base potential of the transistors Qs and Q4.

E3 + hold period transistor Ta Q3. Base potential of Q4.

ΔQ: to hold capacitor C1 of the electric charge being charged Amount of change.

It is expressed as Now, since E2>E5, the amount of change ΔV in the hold potential has a negative value.

Therefore, the bold potential actually appearing at the output terminal 2 has a waveform as shown in FIG. 15, compared to 14 in FIG. 5, making it difficult to hold the potential accurately.

Also, when sampling and holding high-voltage frequency signals or when installing the hold capacitor C1 inside the IC, the capacitance of the hold capacitor C1 has to be small, so the denominator of Equation 1 (5) is small. As is clear from the above, 1ΔV1 increases by a large amount.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a sample-and-hold circuit suitable for IC implementation, which allows accurate sample-and-hold even when the value of the hold capacitor is small.

[Summary of the invention]

The present invention relates to a sample and hold circuit.

In order to suppress fluctuations in the charge charged in the hold capacitor during the process of switching from the sample period to the hold period, a new capacitor and switch are provided to maintain the hold potential at an accurate value.

[Embodiments of the invention]

The principle of the sample-and-hold circuit of the present invention will be explained below with reference to FIG.

FIG. 7 is an equivalent circuit diagram when the present invention is applied to the above-mentioned FIG. Hold capacitor C1゜Capacitor C4 and switch 8
The second class has the same configuration as in Fig. 6, with 6 capacitors C5,
Switch S3 and voltage source E4. E5 is a newly installed circuit.

In FIG.
Accordingly, the sample period is closed to the potential R2 side, and the hold period is closed to the potential R3 side. On the other hand, the switch S5 is similarly closed to the potential R4 side during the sample period and to the potential R5 side during the hold period. As a result, the amount of variation Δq in the charge charged in the hold capacitor C1 is as follows.

ΔQ2C4(R5-R2)+C5(R5-R4) (
6) Here, (?51 is expressed by the capacitance of the capacitor. Therefore, the amount of change ΔV in the hold potential appearing at the output terminal 2 is.

ΔQ ΔMe=−−−□, −(7) CI+C4+C5. Now, if we select capacitor C5 and potential E4 and E5 so that ΔV=0, that is, C4(R3-R2)=C5(R4-R5)-(81), then from equations (6) and (7) above, ΔV = 0, and an accurate potential can be maintained.

The present invention eliminates fluctuations in the hold potential by the means described above.

Note that it is clear that the capacitor C5 is not an actual capacitor, but may be a junction capacitance of a transistor or the like like the capacitor C4 described above.

FIG. 8 shows an example of an S&H circuit to which the present invention is applied. In FIG. 8, resistor R2 and transistor Q9. The circuits other than the portions surrounded by broken lines are the same as those shown in FIG. 2 described above, and detailed explanation thereof will be omitted here. still,
Transistors Q14, Q10, Q16 and resistors R3, R4', R5 constitute a constant current source using bias potential 15 applied to terminal 6.

In FIG. 8, during the sample period, transistors Q5 and Qa are on, and transistors Q6 and Q7 are off. Therefore.

The base potentials of transistors Q1 and Q2 are approximately equal, and the base potentials of transistors Q6 and Q4 are equal to the base potential of transistor Q2, E 1 'K Vsg (
) is the potential E2, which is the sum of the transistor's base-to-emitter voltage. or,.

Since the transistor Q5 is in the on state, the collector potential of the transistor Q1 (the emitter potential of the transistor Q9) is equal to the collector current of the transistor Q1 and the resistor R.
The potential E4 is lower than the power supply voltage +VCC by the voltage drop caused by 2. S & in Fig. 8 in this state
The H portion is equivalent to the equivalent circuit shown in FIG. However, the capacitor C4 is a combined capacitance of the junction capacitance of the transistors Q2, Q5, and Q4 shown by the formula (4HC), and the capacitor C5 is the base-emitter junction capacitance of the transistor Q9.

On the other hand, during the hold period, transistors Q6 and Q7 are turned on, and transistors Q5 and Q7 are turned on. Since QB is in an off state, transistors Q1 to Q4 are in a cutoff state. Therefore, the collector potential of transistor Q1 is the power supply voltage Vcc (=E5), and the base potential of transistors Q3 and Q4 is lower than the power supply voltage +FCC by the voltage drop due to the collector current of transistors Q6 and Q7 and resistor R1. The potential is E5. Equivalent circuit in this state [In FIG. 7, the switch S2 is closed to the switch terminal side and the switch S6 is closed to the switch terminal F side.

In the process of switching from the sample period to the hold period, Qa changes to the amount of change in the charge of the hold capacitor C1 due to the change (E'5-R2)K in the base potential of the capacitor C4 and the transistors Q6 and Q4.

ΔQa = C4 (E5 - E2) - (91.

In addition, the capacitor C5 and the hold capacitor C1 due to the change in the emitter potential of the transistor Q9 (E5=E4)
The amount of change in charge ΔQ, 6 is.

ΔQb=C5(E5-E4)-(and)).

In the S&H circuit of this embodiment, the potential E4 is determined by selecting the resistor R2 so that the amount of change in the charge of the hold capacitor C1 becomes ΔQ,=-ΔQb. This resistance R2 and potential E4 are.

From formula (8).

Here, IQl: Transistor Q flowing during the sample period
Collector current of 1.

It is. This allows the single S&H circuit to perform accurate sample and hold.

The circuit surrounded by the broken line 100 outputs the signal held in the S&H portion as an emitter follower, and the transistors Q10゜Qll, Q12 are as follows:
This is a pace current compensation circuit that prevents the charge charged in the hold capacitor CIK from flowing out due to the pace current of the transistor Q15. The operating principle of the pace current compensation will be explained below using FIG. 9.

Collector current 1c generally flows through a transistor.

What is the relationship between base current hr and emitter current I?

Iε=αIc=−−Ig−−−−−−(13)
1 +α Ic = −In (14) 1 +α where α is the current transfer ratio of the common base transistor.

It is expressed as

In FIG. 9, the pace current IBo flowing into transistor c, +i2 is determined by the emitter current I6, and this pace current IBG is supplied by the pace current I8o of transistor Q10. Further, the collector current of the transistor Q10 is determined by the base current IB, and the relationship between these currents is based on Equation 1 (13) and Equation (14).

Here, αN1 is the current transmission ratio of the pace-grounded NpN transistor. αP is the current transmission ratio of the pace-grounded PNP transistor. Furthermore, the emitter current I6 of the transistor Q12 is the collector current I3 of the transistor Q13, and the collector current I4 of the transistor Q10 is the collector current I3 of the transistor Q11.
The emitter current I4 of the transistor Q13, the pace current IB1 of the transistor Q13, and the base current 1n2 of the transistor Q11 are given by Equation 1 (13) to Equation (16).

It is expressed as Ib1=-Bo(17) H 1B2-αP Iso□-(18). Therefore, transistor Q130 base current IB1t, transistor Q11 pace current 1s
The relationship with 0 is from equation (17) and equation (18).

becomes. In general, 1. Because it is 1 in αP.

From formula (19), it can be regarded as Isl: Ib2.

As a result, the base current of the transistor Q13 in FIG. 8 is supplied by the pace current of the transistor Q11, and it is possible to prevent the charge charged in the hold capacitor C1 from flowing out.

Next, another embodiment to which the present invention is applied will be described using FIG. 10.

In FIG. 10, transistors Q26 and Q27 that perform switching operations, transistor Q9 that is used as a capacitor using junction capacitance, and a constant current source made up of transistor 52 and resistor 13 are used for holding from the sample period. This is a circuit for suppressing fluctuations in the charge charged in the hold capacitor C1 during the process of switching to the period, and the subsection surrounded by the dotted line 100 is the base current that outputs the hold signal as in the above-mentioned Fig. 8. It is a compensated emitter follower. An input signal (sampled/held signal) 10 is input to the terminal 1, a sampling pulse 12 is input to the terminal 4, a reference 1)C voltage for the sampling pulse 12 is input to the terminal 5, and
Terminal 6VC is transistor Q16 that constitutes a constant current source.
, Q32.

A bias voltage that provides the base potential of Q33 is input. A detailed explanation of the operation will be given below.

First, during the sample period (period in which the signal 12 is at a high level), transistors Q24 and Q27 are turned on, and transistors Q25 and Q26 are turned off. Therefore, differential pair transistors Q21 and Q2
2. A constant current source consisting of resistor R11, transistor Q55 via transistor Q24, and resistor R14 constitutes a differential amplifier. Since the base and collector of the transistor Q22 are connected, the differential amplifier is a negative full feedback amplifier. Therefore, the signal 10 input from the input terminal 1 is transmitted as is to the base line (terminal 2) of the transistor Q22. Further, in this state, since no collector current flows through the transistor Q25, the base of the transistor Q25 is at a potential E2 approximately equal to the power supply voltage +Vcc, and the transistor Q25 can be regarded as a diode.

On the other hand, the collector potential of transistor Q27 is.

Since the transistor Q27 is in the on state, the potential E4 is lower than the power supply voltage +VCC by the voltage drop caused by the collector current of the transistor Q27 and the resistor R2.

In this state, the equal number circuit of the S&H portion shown in FIG. 10 becomes the equal number circuit shown in FIG. 7.

However, in this case, capacitor C4 in FIG. 7 is the base-emitter junction capacitance of transistor Q25, and capacitor C5 is the base-emitter junction capacitance of transistor Q9.

Next, during the hold period (the period in which the sampling pulse 12 is at a low level), transistors Q25 and Q26 are turned on, transistors Q24 and Q27 are turned off, and transistors Q21 . Q22), it becomes suspended. Since the transistor Q25 is on, the base potential of the transistor Q23 is a potential E3 lower than the power supply voltage Vcc by the voltage drop caused by the collector current of the transistor Q25 and the resistor R12.
becomes. However, the potential E3 at this time is the transistor Q
23 is cut off to prevent charges from flowing from the power supply line to the hold capacitor C1.

It is set to be lower than the emitter potential of transistor Q23.

On the other hand, since the transistor Q27 is in the off state, no collector current flows, and the collector potential (emitter potential of the transistor Q9) becomes the power supply voltage VccC=E5).

The equivalent circuit in this state is equivalent to the case where the switch S2 is closed to the switch terminal 1 and the switch S3 is closed to the switch terminal F in Fig. i7.

From the above, the amount of variation ΔQ in the charge charged in the hold capacitor C・1 during the process of switching from the sample period to the hold period of the S&H circuit shown in FIG.
c is from equation 1 (6).

ΔQc =C4CF2-E2)+C5(E5-E4
) (20). In the embodiment shown in FIG. 10, the current value of the current source consisting of the resistor R2, the transistor Q32, and the resistor R15 is selected according to the above formula (20).

As explained above, by reducing the variation ΔQ of the charge charged in the hold capacitor C1 to zero, it is possible to suppress the variation ΔV of the hold potential and hold an accurate potential.

In the two S&H circuits described above, as a means to suppress the charge change cap ΔQ in the hold capacitor C1 to zero, in the 5k11 circuit shown in FIG. 8, by selecting the value of the resistor R2, and by selecting the value of the resistor R2 in the In the S&H circuit, this has been done by selecting the resistor R2 and the base-emitter junction capacitance of the transistor Q9. Under the condition that the 6 transistor Q9 is always kept in the cut-off state,
The means for reducing the charge change amount ΔQ to zero can be arbitrarily selected as long as it satisfies the condition of Equation 1 (8).

Also, especially when integrated into an IC, the capacitor C5 should be the base-emitter junction capacitance of the transistor, and the capacitor C5 should be the base-emitter junction capacitance of the transistor.
By taking the ratio with 4, it is possible to easily suppress the amount of charge change ΔQ to zero even with variations in the absolute values of the capacitors C4 and C5.

〔Effect of the invention〕

As explained above, by using the present invention, it is possible to accurately sample and hold signals regardless of the capacity of the hold capacitor, and in particular, it is possible to sample and hold signals at high frequencies.
The effect is great when a small capacitance is used as a hold capacitor in a sample/hold circuit where a hold capacitor is provided inside an IC.

[Brief explanation of drawings]

Figure 1 is a principle diagram of the Sl, H circuit, Figure 2 is a circuit diagram specifically showing an example of the Sl8 circuit, Figure 6 is a circuit diagram for explaining the junction capacitance of a transistor, and Figure 4 is a negative Equivalent circuit diagram of a feedback amplifier. Figure 5 is a waveform diagram showing a specific example of the approximate signal waveform of each terminal for explaining the SkH circuit diagram, and Figure 6 is a waveform diagram showing a specific example of the approximate signal waveform of each terminal to explain the SkH circuit diagram.
Figure 7 is an equivalent circuit diagram of the 5lkH circuit shown in the figure, Figure 7 is an equivalent circuit diagram of the Sl8 circuit of the present invention, Figure 8 is a circuit diagram showing an example of the Sl8 circuit of the present invention, Figure 9 is a base current compensation type circuit diagram. FIG. 3 is a circuit diagram for explaining an output circuit of an emitter follower. FIG. 10 is a circuit diagram showing an example of the 5JkH circuit of the present invention. Explanation of symbols C1: Hold capacitor. SL... Sample switch. Q9...Compensation transistor. Representative Patent Attorney Akio Takahashi No. 1 Dormitory 2 Figure 30 Figure 4 Figure j Figure 7 l No------; 00

Claims (1)

[Claims] 1. Consisting of a first switch that opens and closes according to a control signal input to a control terminal, and a first capacitor connected between the output terminal of the first switch and a reference potential. In the sample-and-hold circuit, a second capacitor having one terminal connected to the output terminal and the other terminal of the second capacitor are connected, and the first voltage source and the second voltage source are connected in accordance with the control signal. A sample-and-hold circuit characterized in that it has a second switch connected to a voltage source KI@. 2. The first switch is connected to first and second transistors whose emitters are coupled to each other, and the flilJ t is connected to the coupled emitters of the two transistors.
The transistor according to M description 1 is composed of a constant current source whose current value is controlled by the ill signal, and a feedback circuit connected between the collector paces of the second transistor and having means for turning off in accordance with the control signal. 2. The sample-and-hold circuit according to claim 1, wherein the pace is used as a signal input terminal, and the pace of the second transistor is used as an output terminal. 6. The sample-and-hold circuit as set forth in claim 1JJ or claim 2, wherein a junction capacitance of a transistor is used for the second capacitor.