JPH05242271A - Charge/discharge circuit - Google Patents

Abstract

PURPOSE:To accurately hold an input signal level and to stably perform an operation. CONSTITUTION:An input signal is supplied to the base of a transistor Tr24 in an input differential pair 16, and a capacitor C2 is charged via a base current mirror circuit 20 for transistors Tr26, Tr27. The potential level of the capacitor C2 is negative-fed back to the base of a transistor Tr25 in the input differential pair 16 via a double Darlington circuit 22 for transistors Tr29, Tr30. Therefore, the base potential of the transistor Tr25 is increased up to the same level as that of the transistor Tr24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charging / discharging circuit, and more particularly to a charging / discharging circuit incorporated in, for example, an IC.

[0002]

2. Description of the Related Art In a conventional charge / discharge circuit 1 shown in FIG. 8, when a sampling pulse such as a burst pulse is applied to the base of a transistor Tr1, the transistor Tr1 turns on. Therefore, the transistor Tr2
And the differential pair 2 including Tr3 are activated. A difference voltage between the input video signal and the reference voltage Vref is generated at the collectors of the transistors Tr2 and Tr3. This difference voltage is inverted by the mirror circuit 3 formed of the transistors Tr4, Tr5 and Tr6, and the transistor Tr7
Is supplied to the emitter of. Therefore, the transistor T
The capacitor C1 is discharged by the base current of r7.

On the contrary, the output voltage generated at the collector of the transistor Tr3 is the transistors Tr8, Tr9 and T.
It is inverted by the mirror circuit 4 constituted by r10 and supplied to the emitter of the transistor Tr11. This emitter current is applied to the transistors Tr11, Tr12 and Tr13.
The capacitor C1 is charged through the base current mirror circuit 5 composed of Therefore, the electric charge corresponding to the difference between the input video signal and the reference signal Vref is stored in the capacitor C1. Then, the electric charge of the capacitor C1 is changed to the triple Darlington circuit 6 including the transistors Tr14, Tr15 and Tr16, and the transistors Tr17 and Tr16.
It is output from the output terminal 7 via 18 and Tr19.

[0004]

In the charging / discharging circuit 1 of FIG. 8, the capacitor C is provided at the leading edge and the trailing edge of the sampling pulse.
The differential pulse is superposed on 1 to charge the parasitic capacitances of the emitter of the transistor Tr14, the base of the transistor Tr15 and the collector of the transistor Tr16 of the triple Darlington circuit 6, respectively. The charge of this parasitic capacitance is superimposed on the charge of the capacitor C1. As a result, peak detection is performed, and an accurate value cannot be held. This gives a similar result when there is noise other than the differential pulse.

Further, it is uncertain which level the potential level on the positive terminal side of the capacitor C1 is with respect to the reference voltage Vref. That is, the potential level of the capacitor C1 varies. Because the transistor Tr2
This is because the output from the collector of Tr3 and Tr3 is the difference between the input video signal and the reference voltage Vref, that is, a relative value.
If the potential level of the capacitor C1 varies and the potential level of the capacitor C1 is at the voltage Vcc level when the power is turned on, the transistors Tr11 and Tr12 are provided.
Does not work. When the potential level of the capacitor C1 is the ground level, the transistors Tr5 and T5
r6 does not work. In either case, there is a problem that a locked state occurs and the operation becomes unstable.

Therefore, a main object of the present invention is to provide a charging / discharging circuit capable of holding an accurate input signal level. Another object of the present invention is to provide a charge / discharge circuit that operates stably.

[0007]

According to a first aspect of the present invention, an input differential pair including a first transistor and a second transistor, the base of the first transistor receiving an input signal, charging according to the input signal or A charging / discharging circuit comprising a capacitor to be discharged, and a high input impedance buffer that negatively feeds back the charging or discharging voltage of the capacitor to the base of the second transistor.

A second invention is the first transistor and the second transistor.
And a capacitor that is charged or discharged in response to an input signal, and a base of the first transistor includes a second transistor as a charge or discharge path of the capacitor. It is a charging / discharging circuit. A third invention comprises an input differential pair for receiving an input signal, a capacitor charged or discharged according to the input signal, an amplifier circuit connected to the capacitor, and a compensation circuit for compensating an input current of the amplifier circuit. It is a discharge circuit.

[0009]

The input signal is supplied to the base of the first transistor, the charge of the capacitor is fed back to the base of the second transistor, and the charge is supplied from the capacitor until the base potentials of the first and second transistors become equal. To be done. Therefore, the capacitor accurately reflects the input signal. Further, the potential level of the capacitor can be calculated by using the stable base potential of the second transistor (= base potential of the first transistor) as a reference.

[0010]

According to the present invention, the capacitor can hold an accurate input signal level and the potential level of the capacitor can be known in advance by calculation, so that the operation can be stabilized. The above-mentioned object of the present invention,
Other objects, features and advantages will become more apparent from the detailed description of the embodiments below with reference to the drawings.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a charging / discharging circuit 1 of this embodiment.
At 0, when a sampling pulse is applied from the terminal 12 to the base of the transistor Tr21, the transistors Tr21 and Tr22 are turned on, and at the same time, the transistor Tr21 and the transistor Tr23 forming the current mirror circuit 14 are turned on. Then, the transistor Tr
The input differential pair 16 composed of 24 and Tr25 is activated. When an input signal during the sampling pulse period is given from the input terminal 18 to the base of the transistor Tr24, the transistor Tr24 turns on, and its collector passes through the base current mirror circuit 20 composed of the transistors Tr26, Tr27 and Tr28, The input signal charges capacitor C2.

On the other hand, transistors Tr21 and Tr2
2 through the capacitor C during the sampling pulse
2 is discharged. The electric charge of the capacitor C2 is supplied to the base of the transistor Tr25 via the double Darlington circuit 22 composed of the transistors Tr29 and Tr30 and the transistor Tr31. That is, the charge of the capacitor C2 is fed back to the base of the transistor Tr25.

As a result, the base potential of the transistor Tr25 rises until it reaches the same level as the base potential of the transistor Tr24. From the stable base potential of the transistor Tr25, the transistors Tr31, Tr30, T
Calculating the voltage drop across r29 and Tr28,
The potential level of the capacitor C2 can be calculated. That is, the problem of the prior art that the potential level of the capacitor C2 becomes indefinite is solved.

Since the base of the transistor Tr25 is controlled until it has the same potential as the base of the transistor Tr24, the input signal level during the sampling period can be taken out as it is by taking the output from the base of the transistor Tr25. Further, the transistors Tr29 and Tr30 form a double Darlington circuit 22, and the double Darlington circuit 22 can perform the same function as the conventional triple Darlington circuit. That is, the collector current of the transistor Tr29 is supplied to the emitter of the transistor Tr26,
When the collector current of 29 is I _C29 , the transistor T
A current of I _C29 / β _n is applied to the base of r26.
The current is multiplied by β _n in the transistor Tr27, and further multiplied by 1 / β _n in the transistor Tr28. Therefore, at the base of the transistor Tr29, I _C29 / β _n
Current is supplied. That is, the transistor Tr29
Is compensated by the base current of the transistor Tr28, and it is not necessary to supply the electric charge from the capacitor C2 to the base of the transistor Tr29. That is, the leakage of the electric charge of the capacitor C2 to the transistor Tr29 is eliminated, and the problem caused by the conventional peak detection hardly occurs. Therefore, an accurate level can be maintained.

However, transistors Tr29 and Tr
The double Darlington circuit 22 of 30 operates as a high input impedance circuit similarly to the conventional triple Darlington circuit, and may be composed of only the transistor Tr29 in some cases. Furthermore, double Darlington circuit 22
Instead of this, an inverted Darlington circuit may be used.

In this charging / discharging circuit 10, R2
≈2R1 is set. The charging / discharging circuit 10 of another embodiment shown in FIG. 2 is the charging / discharging circuit 10 shown in FIG.
The discharge path of the capacitor C2 in, that is, the one corresponding to the transistors Tr22 and Tr21 is replaced with one transistor Tr25 of the input differential pair 16,
This is a rationalization. The electric charge of the capacitor C2 is discharged through the transistor Tr25. Capacitor C
The charging operation of No. 2 is the same as that of FIG. If the collector current of the transistor Tr32 is I _C32 , it passes through the transistors Tr26, Tr27 and Tr28,
A current of I _C32 / β _n is supplied to the base of the transistor Tr32. At this time, the transistors Tr32 and T
The r33 functions similarly to the triple Darlington circuit.

In the charge / discharge circuit 10 shown in FIG. 2, it should be noted that the level of the input signal is dropped by the transistors Tr32 and Tr33 and output to the output terminal 24. However, the potential level of the capacitor C2 is As in the case of 1, the input signal level is accurately reflected.
In addition, in the charge / discharge circuit 10 shown in FIG.
Unlike the charging / discharging circuit 10 shown in FIG. 1 in which the input signal is applied to r24 and the capacitor C2 is grounded, the transistor Tr24 is fixed by the DC power supply DC1 and the capacitor C2 is set in the floating state, and the input signal is input from the input terminal 18. I am trying to give. This input signal is transferred to the transistors Tr28 and Tr2 via the capacitor C2.
Transistor Tr through 9, Tr30 and Tr31
Given to 25 bases. Thus, the capacitor C2
Because it can function as a capacitor coupling type circuit,
It becomes easy in IC design. The operation of the charging / discharging circuit 10 shown in FIG. 3 is the same as that of the charging / discharging circuit 10 shown in FIG. 1, and a duplicate description will be omitted here. By the charge / discharge circuit 10 of FIG. 3, the input signal whose potential level is fixed to the potential level of the DC power supply DC1 is output from the output terminal 24 as it is during the sampling period.

A charging / discharging circuit 10 of another embodiment shown in FIG.
Is a capacitor C2 in the charge / discharge circuit 10 shown in FIG.
The discharge path is constituted by the transistor Tr25, and is substantially the same as the charge / discharge circuit shown in FIG. 2 except that the transistor Tr24 is fixed by the DC power supply DC1. The charge / discharge circuit 10 shown in FIG. 5 uses the charge / discharge circuit 10 shown in FIG. 3 as a DC regeneration circuit. Therefore, when the input signal is a video signal, the output terminal 24 outputs a video signal fixed to the front end of the synchronizing signal included in the input signal or the DC power supply DC1.

A charging / discharging circuit 10 of another embodiment shown in FIG.
Is configured almost the same as the charge / discharge circuit 10 shown in FIG.
It can be used in a peak detection circuit for extracting the peak value of an input video signal. The charging / discharging circuit 10 of another embodiment shown in FIG. 7 is a modification of the charging / discharging circuit 10 shown in FIG. 5, and can be used as a sync separation circuit. That is, when the potential level of the input video signal is higher than the synchronization signal level, the transistor Tr25 is fully conductive,
A voltage drop occurs in the resistor R3 due to the current of the transistor Tr23. Further, when the potential level of the input video signal is the synchronization signal level, the collector current of the transistor Tr23 becomes about 1/2 of that in the above case, and a voltage drop occurs in the resistor R3, resulting in synchronous separation.

The charging / discharging circuit 10 of FIGS. 3 to 7 is a C-coupled circuit, which facilitates IC design as compared with a direct coupling circuit such as the charging / discharging circuit 10 shown in FIGS. Also,
The charging / discharging circuit 10 shown in FIGS. 4 and 5 can be used in, for example, a VTR reproduction system circuit or the like in which a sampling pulse cannot be supplied. It will be understood that, in all of the above-described embodiments, if the transistor type is reversed, the charging in the above description becomes a discharging operation, and the discharging operation becomes a charging operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.

FIG. 3 is a circuit diagram showing another embodiment of the present invention.

FIG. 4 is a circuit diagram showing another embodiment of the present invention.

FIG. 5 is a circuit diagram showing another embodiment of the present invention.

FIG. 6 is a circuit diagram showing another embodiment of the present invention.

FIG. 7 is a circuit diagram showing another embodiment of the present invention.

FIG. 8 is a circuit diagram showing a conventional technique.

[Explanation of symbols]

 10 ... Charge / discharge circuit 14 ... Current mirror circuit 16 ... Input differential pair 20 ... Base current mirror circuit 22 ... Double Darlington circuit C2 ... Capacitor Tr1-Tr33 ... Transistor

Claims (3)

[Claims] 1. An input differential pair including a first transistor and a second transistor, the base of the first transistor receiving an input signal, a capacitor charged or discharged according to the input signal, and the capacitor. A charging / discharging circuit comprising a high input impedance buffer that negatively feeds back the charging or discharging voltage to the base of the second transistor. 2. An input differential pair including a first transistor and a second transistor, the base of the first transistor receiving an input signal, and a capacitor charged or discharged according to the input signal, A charging / discharging circuit, wherein the second transistor is used as a charging or discharging path of the capacitor. 3. An input differential pair for receiving an input signal, a capacitor charged or discharged according to the input signal, an amplifier circuit connected to the capacitor, and a compensation circuit for compensating an input current of the amplifier circuit. , Charge and discharge circuit.