JP2585285B2 - Sample hold circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit suitable for a monolithic IC.

[Prior Art] As shown in FIG. 5, a conventional sample-and-hold circuit connects two transistors Q ₁₃ and Q ₁₄ with an emitter, inputs an input to one of the transistors, and connects a diode with the other to form a constant current source ( IA / 2) is connected to a bipolar monolithic IC.
Was used for This is, for example, ISSC, papers, TPM
14.1 (1983) pp. 178-179 (ISSCC, Digest of Tech)
nical Papers, THPM 14.1, pp 178-179 (1983)). This method is characterized in that the input is the base of a transistor, the input impedance is higher than the method using a diode bridge, and the circuit is simpler.

[Problems to be Solved by the Invention] The above-mentioned prior art is a diode-connected transistor.
A constant current source as a load of Q ₁₄ is required, forced use pnp transistor for the constant current source. But,
When a monolithic IC was used, a high-speed pnp transistor could not be obtained, which was an obstacle to speeding up the sample-and-hold circuit.

An object of the present invention is to use a bipolar monolithic IC without using a device such as a pnp transistor which is an obstacle to high speed operation.
It is an object of the present invention to provide a high-speed sample-and-hold circuit suitable for the following.

[Means for Solving the Problems] The above object is to use a resistor instead of the above-described constant current source,
Further, this is achieved by adding a circuit that ensures that the current flowing through the diode-connected transistor with the input transistor is always equal to the input signal level.

[Operation] A current that causes a voltage drop according to the input voltage flows through the resistor connected as a load, but the base-emitter voltage V _BE of the transistor is almost constant even if the collector current changes. The voltage drop across the resistor follows the input and can sample the input signal. Since the load is a resistor, a high-speed sample-and-hold circuit can be realized without obstructing high-speed operation unlike the conventional pnp transistor.

[Embodiment] Hereinafter, a first embodiment of the present invention will be described with reference to FIG. In the figure, an input signal is given from an IN terminal.
First, at the clock terminals CLK and CLK, CLK is set to “H”.
When the level is at the level, the transistor switches Q4 and Q5 are turned on, the current flows through the transistors Q1 and Q2, and the transistors switches to the sample state. In this case, Q1, Q2, Q3 of the base-emitter voltage as V _BE1, V _BE2, V _BE3 respectively, Q2, Q3 the current flowing through the I, the current of the constant current source IE, or a an input voltage V _IN Then, the following equation is established.

_{V IN -V BE1 = V CC -R1} · I-V BE2 -V BE1 (1) On the other hand, voltage V _CH of the hold capacitor C _H is the _{V CH = V IH -V BE1 +} V BE2 (2). Here, since the base-emitter voltage is almost constant even if the collector current changes, if V _{BE1 and} V _BE2 , the equation (2) gives V _CH V _IN (3). Is almost equal to

Next, when CLK becomes “L” level, Q5 turns off and Q4
Is turned on. At this time, the current _IE flows through R1 and R1
Is V _CC −R1 · _IE . Since the voltage at the time of sampling is V _CC −R1 · I and _IE > I, the voltage is lower than at the time of sampling, and if a constant is selected so that V _CH > V _CC −R1 · _IE , Q ₃ to Q ₃ becomes reverse biased, even no current flows in the Q _2, the voltage of the hold capacitor will be maintained.

As described above, by switching between the sample and hold states according to the CLK level, a sample and hold circuit can be realized. In FIG. 1, reference numeral 10 denotes a buffer circuit. In this embodiment, the resistor R1 is used as the load, and no speed reducing element such as pnp is used, so that a simple and high-speed sample and hold circuit can be realized.

In the above first embodiment, since the terminal voltage of the hold capacitor C _H is not necessarily made exactly equal to the input voltage,
This is a problem when high precision is required. this is,
A current I that satisfies the expression (1) flows through the transistor Q2, and a current I _E -I flows through Q1, and I is V
_{This is} caused by the fact that the base-emitter voltages V _{BE of} Q1 and Q2 become unequal because they are changed by _IN .
Therefore, when higher accuracy is required, V of Q1 and Q2
_BE must be equal.

FIG. 2 shows a second embodiment for solving the above problem. This figure is obtained by adding a second constant current source ΔI _E that changes according to an input signal to the constant current source I _EO in the first embodiment. The magnitude of ΔI _E can be calculated as follows.
First, in general, equation (7) holds. Assuming that the collector currents of Q1, Q2, and Q3 are always equal, and assuming that the dimensions of the transistors are equal, V _BE1 = V _BE2 = V _BE3 = V _BE .
It can be written as follows.

_{V CC -I · R1-V BE} = V IN (4) On the other hand, if the total current of the constant current source and I _E, it is I _E = 2I
If, Q1, since Q2 current flowing is equal _{I E = 2I E = 2 (} V CC -V BE -V IN) / R1 may always be satisfied (5). Therefore, when V _IN = V _INO , I _E = I
And is _EO, When V _IN is [Delta] V _IN changes _{I E = I EO + ΔI E} = 2 (V CC -V BE -V INO) / R1-2 · ΔV IN / R1 (6) next, [Delta] I _E = −ΔV _IN / (R1 / 2) (7) By adding a current source ΔI _E to I _EO such that
It is always possible to make _IE = 2I, and the collector currents of Q1 and Q2 are equal. Thus, V _BE of Q1 and Q2 is always equal for V _IN, can equal the terminal voltage V _CH of the input voltage V _IN and the hold capacitor.

FIG. 3 shows a specific circuit example of the second embodiment. A current source is constituted by the transistor Q7 and the resistors RE and RF. The current _IE of this current source is Can be expressed as Here, VR is the base voltage of the transistor Q7, V _BE is the base-emitter voltage, and VS is the voltage of the level shift constant voltage source VS. V _INO is a reference value of the input voltage, and ΔV _IN is a change in the input voltage. By comparing the equations (8) and (6), ΔI _E = −ΔV _IN / RF (10) Get. As for I _EO , V _S may be determined according to each constant so that I _EO is obtained from one item of the equation (6).

Next, another specific circuit side is shown in FIG. This is to detect the variation of V _IN from the terminal voltage of the resistor R1, and the effect of making the currents flowing through Q1 and Q2 always equal according to the input signal is the same as in the example of FIG. Again in this case Only the value of VS is different from the case of FIG.

The case where the base of the transistor Q2 is connected to the collector has been described above with reference to FIGS. 1 to 4.
This base may be connected to the output O / P of the sample and hold circuit. In this case, since feedback is applied so that the output O / P becomes equal to the input IN, a sample-hold circuit with a small offset between the input and the output can be realized.

If a resistor or only a buffer circuit is connected instead of the hold capacitor CH, it can be used as an analog switch as in the conventional case.

[Effects of the Invention] As described above, according to the present invention, a high-speed sample-and-hold circuit can be realized with a simple circuit without using an element that causes a reduction in speed, such as a pnp transistor, and only by adding a simpler circuit. The structure can be improved, and the effect of improving the economy and performance is great.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, and FIG.
3 and 4 are diagrams showing a specific circuit configuration of FIG. 2, and FIG. 5 is a diagram showing a conventional example. Q1… Input transistor, Q2… Diode connection transistor, R1… Load resistance, Q4, Q5… Switch transistor, CH… Hold capacitor, 10… Buffer circuit.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Toshihiko Shimizu 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Kenji Asobu 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd. Central Research Laboratory (56) References JP-A-60-95796 (JP, A)

Claims (2)

(57) [Claims] A first transistor having an input signal input to a base; a second transistor having an emitter and an emitter connected to each other; and an emitter connected to a collector of the second transistor. Connected to a third transistor, a collector and a base of the third transistor, and an operating potential point.
A load connected to the collector of the second transistor; a base driven by a control signal; and a collector connected to the collector and the base of the third transistor of the load circuit. A fourth terminal connected to a connection point with the first resistor
The base is driven by a negative-phase control signal having a phase opposite to that of the control signal, the fourth transistor and the emitter are interconnected, and the collector is interconnected by the first and second transistors. A fifth transistor connected to the emitter; a power supply connected to the interconnected emitters of the fourth and fifth transistors; The fourth transistor is turned off and the fifth transistor is turned on by the control signal and the negative-phase control signal, whereby the fifth transistor is turned on. A sample state in which a voltage corresponding to the input signal input to the base of one transistor is supplied to the capacitor. A voltage drop of the first resistor of the load circuit by causing the fourth transistor to be in a conductive state and the fifth transistor to be in a non-conductive state in accordance with a mode and the control signal and the antiphase control signal. And a hold state mode for holding the voltage supplied to the capacitor in the sample state mode by reverse biasing the third transistor.
A hold circuit, further comprising: a correction circuit including a sixth transistor, and a series circuit of a level shift circuit and a second resistor connected to an emitter of the sixth transistor, wherein the current source includes: A seventh base in which a predetermined bias voltage is applied to a base, an emitter is connected to a reference potential point via an emitter resistor, and a collector is connected to the interconnected emitters of the fourth and fifth transistors. A resistance value of the second resistor of the correction circuit is set to approximately 1/2 of the first resistance of the load circuit; and a base of the sixth transistor of the correction circuit is The input signal input to the base of the first transistor is applied, and the emitter of the sixth transistor is connected to the current through the series circuit of the correction circuit. A sample and hold circuit connected to the emitter of the seventh transistor of the source. 2. A first transistor having a base to which an input signal is inputted, a second transistor having an emitter and an emitter connected to each other, and an emitter connected to a collector of the second transistor. Connected to a third transistor, a collector and a base of the third transistor, and an operating potential point.
A load connected to the collector of the second transistor; a base driven by a control signal; and a collector connected to the collector and the base of the third transistor of the load circuit. A fourth terminal connected to a connection point with the first resistor
The base is driven by a negative-phase control signal having a phase opposite to that of the control signal, the fourth transistor and the emitter are interconnected, and the collector is interconnected by the first and second transistors. A fifth transistor connected to the emitter; a power supply connected to the interconnected emitters of the fourth and fifth transistors; The fourth transistor is turned off and the fifth transistor is turned on by the control signal and the negative-phase control signal, whereby the fifth transistor is turned on. A sample state in which a voltage corresponding to the input signal input to the base of one transistor is supplied to the capacitor. A voltage drop of the first resistor of the load circuit by causing the fourth transistor to be in a conductive state and the fifth transistor to be in a non-conductive state in accordance with a mode and the control signal and the antiphase control signal. And a hold state mode for holding the voltage supplied to the capacitor in the sample state mode by reverse-biasing the third transistor.
A hold circuit, further comprising: a correction circuit including a sixth transistor, and a series circuit of a level shift circuit and a second resistor connected to an emitter of the sixth transistor, wherein the current source includes: A seventh base in which a predetermined bias voltage is applied to a base, an emitter is connected to a reference potential point via an emitter resistor, and a collector is connected to the interconnected emitters of the fourth and fifth transistors. A resistance value of the second resistor of the correction circuit is set to approximately 1/2 of the first resistance of the load circuit; and a base of the sixth transistor of the correction circuit is The emitter of the sixth transistor is connected to the collector of a fourth transistor, and the emitter of the sixth transistor is connected to the seventh transistor of the current source via the series circuit of the correction circuit. A sample connected to the emitter of the
Hold circuit.