JPH0346816A - Pulse generator - Google Patents

Abstract

PURPOSE:To realize a double setting precision and to reduce the cost by providing a half clock control circuit which properly shifts the rise of a ripple carry signal by a half clock with a half clock control signal to generate a trigger clock signal. CONSTITUTION:When a half clock control signal HALF is in the high level, a half clock control circuit 6 shifts to right the rise of a ripple carry signal RCY by a half clock. Therefore, the high level section and the low level section can be controlled by the precision of the half clock of a clock signal CLK, namely, the double precision. For example, the high level or low level section is widened by an extent corresponding to the half clock of the clock signal CLK in comparison with that set by section setting data when the half clock control signal HLF is in the high level. Thus, the setting precision of the high level or low level section is raised twice without raising the frequency of the clock signal CLN, and the cost is reduced because this device is formed with inexpensive circuit elements.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse generator for obtaining a pulse width modulated output pulse signal for controlling a discharge lamp lighting circuit.

[Prior Art] Conventionally, this type of pulse generator for obtaining a pulse width modulated output pulse signal for controlling a discharge lamp lighting circuit has been used.
A predetermined on/off duty (predetermined "H" interval, "L" interval) is determined by an internal counter that is formed using a microprocessor and is software-based by a program.
I was trying to obtain an output pulse signal.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional example, the setting accuracy of on and off duties is regulated by the machine cycle of the microprocessor, and - the machine cycle within the membrane is several μ.
Since it is about 5c7c, there is a problem that it is not possible to set the on/off duty with an accuracy of several microseconds or less, which causes a problem when used as a pulse generator for switching control of a discharge lamp lighting circuit that lights a discharge lamp at high frequency. there were.

Therefore, in order to solve the above-mentioned problem, it is possible to obtain an output pulse signal that is pulse width modulated using hardware using a presettable counter circuit (logic circuit) that counts the clock signal. However, even if a counter circuit is used, the setting accuracy of the "H" section and "L" section is determined by the frequency of the tarok signal, so in order to achieve high setting accuracy,
It is necessary to use a clock signal with a high frequency, and when the frequency of the clock signal is increased, expensive circuit elements must be used, resulting in an increase in cost.

The present invention has been made in view of the above points, and its purpose is to be able to increase the accuracy of setting the on and off duty, and to double the setting without increasing the frequency of the clock signal. An object of the present invention is to provide a pulse generator that can achieve high accuracy and reduce costs.

[Means for Solving the Problems] The pulse generator of the present invention includes a data latch circuit that latches "H" section setting data and "L" section setting data of an output pulse signal, and a data latch circuit that counts a clock signal of a constant period. Consists of a presettable counter circuit in which the above two interval setting data are set alternately, and a toggle flip-flop circuit which uses the ripple carry signal from the above counter circuit as a trigger clock signal, and changes both interval setting data independently. The pulse generator is configured to obtain a pulse width modulated output pulse signal from the toggle flip-flop circuit by providing a pulse width control means to control the rising edge of the ripple carry signal by half a clock using a half clock control signal. A half clock control circuit is provided to form a trigger clock signal by appropriately shifting the trigger clock signal.

[Function] The present invention is configured as described above, and the "H" section setting data and the "L" section setting data of the output pulse signal are latched in a data latch circuit, and - a fixed period clock signal is counted. Then, a ripple carry signal from a presettable counter circuit in which the above two interval setting data are set alternately is used as a trigger clock signal of the toggle flip-flop circuit, and a pulse width modulated output pulse signal is obtained from the toggle flip-flop circuit. So,
Unlike the conventional example in which the "H" interval and "L" interval were set using the microprocessor's internal counter, the setting accuracy of on and off duty is not restricted by the microprocessor's machine cycle, and the machine cycle Regardless, the "H" interval and the "L" interval can be arbitrarily set, making it possible to increase the accuracy of setting the on and off duties. In addition, a half clock control circuit is provided which appropriately shifts the rising edge of the ripple carry signal by half a clock using the half clock control signal to form a trigger clock signal.
This makes it possible to double the setting accuracy and reduce costs without increasing the frequency of the clock signal.

[Embodiment] Fig. 1 shows an embodiment of the present invention, which includes a data latch circuit 1 that latches "H" interval setting data and °°L" interval setting data of an output pulse signal, and a tarlock signal of a constant period. A presettable counter circuit 2 that counts CLK and sets the above-mentioned two interval setting data alternately, and a ripple carry signal RC'Y from the counter circuit 2.
Toggle 71717071 circuit 3 with as trigger clock
A pulse width modulated output pulse signal OUT is obtained from the toggle flip-flop circuit 3 by providing pulse width control means for independently changing both interval setting data. In the embodiment, the pulse width control means is formed by a microprocessor, and the "H" output from the microprocessor is
The "section setting data" and "L" section setting data are input to input terminals IN, -IN, 2 of the data latch circuit 1, and are latched by a timing signal output from the timing control circuit 4.

Here, the data latch circuit 1 is formed of a primary buffer 1a and a secondary buffer 1b, and both buffers 1a, 1b are formed of flip-flops and T-buffers as shown in FIGS. 2 and 3. ing. In the primary buffer la, when the section data set signal HL is input,
Input terminal IN.

~IN, D T l−D T + input via □
2 is set as “H” section setting data D A + “”” D A l by latch signals LATCHA and LATCH.
, "L" section projection data DB, ~DB, □ are closed and latched. In addition, in the secondary buffer 1b, the latch data DA12, DB, ~・DB of the primary buffer 1a is output by the latch signal LTCH.
+2, and section setting data DA + to DA + selected by enable signals ENA and ENs.
2 or DB, -DB+2 is output as preset data of the counter circuit 2. Also,
The half clock control signal HLF is also latched once and the signal H
It is designed to be output as ALF.

Further, the counter circuit 2 and the toggle flip-flop circuit 3 are integrated as a counter/output circuit 5,
As shown in FIG. 4, a 12-bit counter circuit 2 is formed using three 4-bit presettable counters, and a ripple carry signal RCY of the counter circuit 2 is toggled and flipped via a half-clock control circuit 6. Flo・
・It is input to the 21 circuit 3 as a trigger clock signal. The flip-flop output of this toggle flip-flop circuit 3 is converted into an output pulse signal O via two inverters.
An enable signal E is output as UT and simultaneously reads predetermined preset/to data from the data latch circuit 1.
NA and EN are output. Here,
The half clock control circuit 6 outputs a ripple carry signal RC when the half clock control signal HALF is "H".
The rising edge of Y (the inversion timing of the toggle flip-flop circuit) is shifted to the right by half a clock, making it possible to control the "H" period and the "L" period with half a clock precision (double precision) of the clock signal CLK.

Further, the timing control circuit 4 outputs a latch signal LATCH.
, LATCHA, LATCHa, LTCH as shown in FIG. 5, and a clear signal C.
LEAR, load signal LOAD, latch signal LTCH,
The counter control circuit 4b as shown in FIG. , to control the operation timing of each circuit.

By the way, in the embodiment, the two-phase lock generation circuit 7 generates the two-phase lock signals OUT + and OUT 2 based on the output pulse signal OUT, and the output signal that controls the switching of the discharge lamp lighting device 10 is used. , output the output pulse signal OUT, or output the two-phase lock signal OUT.
The switching signal S determines whether to output T ,, OUT 2.
A single-end type (output pulse signal OU
Single-stone inverter type (with switching transistor controlled by T) or half-bridge type (two-phase lock signal OUT).

A switching 'M control signal for the discharge lamp lighting device 10 (two-wheel inverter type) in which a pair of switching transistors connected in series is controlled by 0UT2 is obtained. Here, the two-phase lock generation circuit 7 is based on a presettable counter circuit 7a that counts the clock signal CLK and sets a non-overlapping section, and a ripple carry signal RCY 2° output from the presettable counter circuit 7a. and a gate control circuit 7b that controls the gate circuit 7C, and has a non-overlapping section set based on non-overlapping section setting data HB+ to HB set using an 8-bit setting switch. The lock signal 0UT1.0UT2 is output.

The operation of the embodiment will be explained below using the time charts shown in FIGS. 8 and 9. FIG. 8 is a waveform diagram showing the basic operation of this embodiment. First, when the start signal 5TART output from the microprocessor rises, the "H" section setting data DA, - When D A + 2 is determined, the section data setting signal HL rises from the microprocessor, one pulse of the latch signal LATCHA is output, and the II H11 section setting data DA, ~DA, □ are stored in the primary buffer 1a of the data latch circuit 1. The 6th latched
“When the section setting data DB, ~DB, etc. are determined, the latch signal LATC is activated at the falling edge of the section data setting signal HL.
One pulse of H and t is output and "L"' section setting data D
B, ~D B + 2 are latched into the primary buffer 1a of the data latch circuit 1.

Next, the clear signal CLEAR becomes Ln, the latch signal LTCH is outputted as one pulse, and both interval setting data DA
, ~DA, □, and DBI~D B +2 are latched into the secondary buffer 1b. At this time, the enable signal ENA
is “H”, so the data is “H” from the secondary buffer 1b.
``When the section setting data DAI~DA+2 is read out and the load signal LOAD for setting the P9 set data in the counter circuit 2 is output, the counter circuit 2 (this "H" interval setting data DAI~DA+2 is outputted). l2 is set. In this state, the counter circuit 2 starts counting the clock signal CLK, and the output Q of the counter circuit 2
When all of 1 to Q2 become "I(", a ripple carry signal RCY is output.This ripple carry signal RC
The enable signal EN becomes "H" due to Y, and at the same time, the output pulse signal OUT also becomes "H''. Then,
When the section setting data DB, ~D B + 2 is preset in the counter circuit 2, counting of the clock signal CLK is started, and the ripple carry signal RCY is obtained,
When the output pulse signal becomes "L", the enable signal ENA becomes "H'", and the above-described operation is repeated.

Therefore, both section setting data DA, ~D A l 2
, DB, ~DB+2 based on the output pulse signal O
The "H" section and °L" section of UT can be set arbitrarily (within a range of 12 bits), and the on/off duty can be set. When changing the on/off duty, " H” section setting data DAI~D
After setting A + 2, section data setting signal HL
Set to “H” and set “Shi” section setting data DB, ~DB
After setting rz, set the section data setting signal HL to "L".
”.

For example, as shown in FIG. 8, the frequency of the clock signal CLK is 16 MHz (period 62.5 nsec)
When setting the “section” to 161 pulses and the “L” section to 164 pulses, the “H” section setting data DA, ~DA,
Set the 8th and 6th bits of □ to "Pa1".
8th bit of L″ section setting data DB, ~DB, 2,
It is sufficient to set the 6th bit, 2nd bit, and 1st bit to 1". In this case, the period of the output pulse signal OUT is 325 pulses of the tally clock signal CLK, which is 20.2 μsec. The frequency becomes 49°2kHz.Also, if the width of the "H" section or "L'° section is widened by one pulse (62.5nsec), the period becomes 326 pulses of the clock signal CLK, and the frequency becomes 49°.
．． It becomes 1kHz. Therefore, in the embodiment, the "H" section or "L" section of the output pulse signal OUT is set to 62
．． Can be set in 5n S e C increments, and can be set in 0.1
The frequency can now be controlled in kHz increments, and this setting accuracy is impossible to achieve with conventional pulse generators that use a software internal counter using a microprocessor. In this case, fine-grained lighting control can be performed.

It goes without saying that setting accuracy can be further increased by increasing the frequency of the clock signal CLK counted by the counter circuit 2.

Next, FIG. 9 is an operation explanatory diagram of half clock control, where the half clock control signal HLF output from the microcomputer (that is, the signal HALF output from the data latch circuit 1) is "L". In this case, the ripple carry signal RCY directly becomes the trigger clock for the toggle flip-flop circuit 3, and as shown in FIG.
), the output pulse signal OUT is inverted in synchronization with the rise of the ripple carry signal RCY. - On the other hand, when the half clock control signal HLF becomes "H", the rising edge of the ripple carry signal RCY shifts to the right by half a clock, as shown in FIG. 9(a).
This shifted pull-carry signal RCY serves as a trigger clock for the toggle flip-flop circuit 3 to invert the output pulse signal OUT. therefore,
When the half clock control signal HLF is “H”, the “H” interval or the “L” interval is set to the interval setting data DA, ~DA.
, 2°DB, ~DB, , compared to the case of FIG. The setting accuracy of the ward section and "L" section can be doubled, and cheap circuit elements can be used.
Half clock control can be automatically performed by synchronizing the half clock control signal HLF, which is low in cost, with the section data setting signal HL.

That is, the section setting data DAI to D A li D
By inputting the half clock control signal HLF when inputting B + to D B + z, the output pulse signal O
By changing the frequency f of the UT at regular intervals, the discharge lamp can be dimmed in stages and soft-started. Figure 10(a) shows an example of the change in frequency f when lighting a discharge lamp is soft-started without half-clock control, and Figure 10(b) shows the frequency when soft-started with half-clock control. An example of a change in f is shown. When half-clock control is performed, the width of change in frequency f can be halved compared to when half-clock control is not performed, and smooth soft start can be achieved by fine-grained stepwise dimming. It turns out that it can be done.

Next, in the two-phase lock generation circuit 7, a clock signal CL is output from a presettable counter circuit 7a to which non-overlap section setting data HB, ~HBa is preset.
K is counted to set a non-overlapping section, and as shown in FIG. 11, the gate circuit 7C is controlled based on the ripple carry signal RCY 2° output from the presettable counter circuit 7a. A two-phase lock signal OUT in which a gate control signal is formed and a non-overlapping section is added to the output pulse signal OUT by a gate circuit 7c controlled by the gate control signal.
,,ou'rz are formed.

The output pulse signal OUT and the two-phase lock signal OUT, 0UT2 generated as described above are outputted via the output switching circuit 8, and the output switching signal S E/HB is set to "H". ”, the output pulse signal OUT is output, and when the output switching signal SE/HB is “L”, the two-phase lock signals OUT, , OUT are output. Therefore, the output switching signal S E/H
By appropriately setting B, a pulse generator that can be used with a single-ended or half-bridge discharge lamp lighting device 10 can be obtained.

[Effects of the Invention] The present invention is configured as described above, and latches the ``H'' interval setting data and the ``L'' interval setting data of the output pulse signal in the data latch circuit, and counts the fixed period tarock. A ripple carry signal from a presettable counter circuit in which the above two interval setting data are alternately set is used as a trigger clock for a toggle flip-flop circuit, and a pulse width modulated output pulse signal is obtained from the toggle flip-flop circuit. Therefore, unlike the conventional example where the internal counter of the microprocessor was used to set the °°H" interval and the "L" interval, the setting accuracy of on and off duty is not restricted by the microprocessor's machine cycle. , the "H" section and "L" section can be arbitrarily set regardless of the machine cycle, and the on/off duty setting accuracy can be increased.Also, ripples can be eliminated with the half clock control signal. A half-clock control circuit is provided that appropriately shifts the rising edge of the carry signal by half a clock to form a trigger clock signal, making it possible to double the setting accuracy without increasing the frequency of the clock signal, reducing costs. It has the effect of being able to

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of an embodiment of the present invention, FIGS. 2 to 7 are circuit diagrams of the main parts of the same, and FIGS. 8 to 11 are operation explanatory diagrams of the same. 1 is a data latch circuit, 2 is a counter circuit, 3 is a toggle flip-flow 71 circuit, 4 is a timing control circuit, and 8 is a half clock control circuit.

Claims (1)

[Claims] (1) “H” section setting data of output pulse signal and “
a data latch circuit that latches L” section setting data;
It consists of a presettable counter circuit that counts a clock signal of a constant period and sets the above two interval setting data alternately, and a toggle flip-flop circuit that uses the ripple carry signal from the counter circuit as a trigger clock signal. A pulse generator which obtains a pulse width modulated output pulse signal from the above-mentioned toggle flip-flop circuit by providing a pulse width control means for independently changing the interval setting data, the pulse generator having a half clock control signal. A pulse generator comprising a half clock control circuit that appropriately shifts the rising edge of a ripple carry signal by half a clock to form a trigger clock signal.