JPH0346336A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a base width, to restrain a base-pushing effect at a high electric-current level and to reduce a junction capacitance between an outer base region and a collector layer by a method wherein an impurity layer whose impurity concentration is higher than that of the collector layer exists only just under an intrinsic base region. CONSTITUTION:An oxide film 5 is grown by a thermal oxidation method. During this process, P-type outer base regions 9 situated above an N<+> layer 6 are diffused into a substrate 1 and creeps to be deeper than the N<+> layer 6; the N<+> layer 6 which has existed below the P-type outer base region 9 vanish; as a result, the N<+> layer 6 is left only below a part which is to be used as a P-type intrinsic base region between the P-type outer base regions 9. In this case, the N<+> layer 6 whose impurity concentration is higher than that of an N-type epitaxial layer 4 to be used as a collector layer is formed only just under the P-type intrinsic base region 10, in addition, an impurity concentration at a junction part to the collector layer at the P-type outer base region 9 is reduced. Thereby, a base width is reduced, a base-pushing effect is restrained and also a junction capacitance between the outer base regions and the collector layer is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a manufacturing method particularly suitable for manufacturing semiconductor devices such as high-speed response bipolar transistors and integrated circuits thereof.

<Prior Art> When forming this type of bipolar transistor, a layer having an impurity concentration higher than that of the substrate is provided only directly under the emitter region and the intrinsic base region below the emitter region, thereby reducing the heath width. It is well known that the reduction is aimed at suppressing the base extrusion effect at high current injection levels and increasing the transition frequency. The conventional general manufacturing method of this is shown in the seventh section, which shows the manufacturing process.
This will be explained with reference to FIGS. 9 to 9.

First, as shown in FIG. 7, an oxide film 5 is formed on the surface of an N-type epitaxial layer 4, which will serve as a collector region, formed on a P-type silicon substrate (not shown). By selectively removing and implanting impurities such as boron using the remaining oxide film 5 etc. as a mask, two types of bases are formed: the intrinsic base region 10 with different impurity concentrations and the external base jTJ region 9 around this. Form a region.

Subsequently, phosphorus was applied at an accelerating voltage of 150 KeV and at a dose of 12
．． By implanting ions of about OXIQlzCIIl-z, the intrinsic base region 1 is formed as shown in FIG.
An N'' layer 6 having a higher impurity concentration than the N type epitaxial layer 4 is formed only directly below the layer 0.

Furthermore, after forming polysilicon doped with arsenic, this polysilicon is patterned to form an emitter electrode 1) as shown in FIG. 9, and arsenic is diffused from this emitter electrode 1) into the intrinsic base region 10. The emitter region 13 is then manufactured through a process of forming the emitter region 13.

As a result, the emitter region 13 and the intrinsic base region 10
An N° layer 6 having a higher impurity concentration than the substrate, that is, the N-type epitaxial layer 4, is formed only directly under the substrate, and a high-speed response bipolar transistor having the above-mentioned effects can be obtained without increasing the capacitance between the collector and the base. .

<Problems to be Solved by the Invention> By the way, it is known that as a means to further increase the response speed of a bipolar transistor, it is possible to reduce the junction capacitance between the external base region and the collector layer. This can be achieved by lowering the impurity concentration in the portion of the base region that is in contact with the collector layer. However, in the conventional manufacturing method described above, it is not possible to reduce the junction capacitance between the external base region and the collector region due to restrictions in the manufacturing process.

The present invention has been made in view of such conventional problems, and it is possible to form an impurity layer having a higher impurity concentration than the collector layer and the same type as the intrinsic base region only directly under the intrinsic base region, and also to form an impurity layer just below the intrinsic base region. A technical object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the impurity concentration of a portion of a base region that is connected to a collector region.

<Means for Solving the Problems> In the present invention, as a technical means for achieving the above-mentioned problems, a method for manufacturing a semiconductor device is performed through the following steps. That is, in a method for manufacturing a semiconductor device in which the emitter, collector, and base regions are formed vertically, and the base region includes two types of base regions, an intrinsic base region and an extrinsic base region, which have different impurity concentrations, a collector layer is formed on a substrate. An impurity layer having a high impurity concentration and the same type as that of the collector layer is formed in this collector layer, and in the surrounding portion of this impurity layer excluding the emitter formation region,
An impurity having a higher concentration than the impurity layer is introduced and diffused to have a deeper concentration distribution than the impurity layer to form the extrinsic base region, and the intrinsic base region and emitter are formed on the remaining impurity layer. It is characterized by passing through a step of sequentially forming regions.

Effect> An external base region is formed by introducing an impurity with a higher concentration than the impurity layer into the area around the impurity layer except for the emitter formation region and diffusing the impurity so as to have a deeper concentration distribution than the impurity layer. As a result, the impurity layer below the external base region disappears and the impurity layer remains only in the part where the intrinsic base region should be formed, and the impurity layer exists only directly under the intrinsic base region and emitter region formed above this. In addition, the impurity concentration of the portion of the external base region where the impurity layer was present, that is, the portion in contact with the collector layer, is reduced by the impurity layer having a lower impurity concentration than that of the external base region.

Therefore, by having an impurity layer with a higher impurity concentration than the collector layer just below the intrinsic base region, the base width is reduced and the base extrusion effect at high current levels is suppressed, while the extrinsic base region By lowering the impurity concentration in the portion in contact with the collector layer, the junction capacitance between the external base region and the collector layer is reduced, making it possible to manufacture a semiconductor device that responds at extremely high speed.

<Example> Hereinafter, a preferred example of the present invention will be described in detail with reference to FIGS. 1 to 6 showing the manufacturing process thereof.

First, as shown in FIG. 1, an N-type buried layer 2 and a P-type buried layer N3 are formed on the surface of a P-type silicon substrate 1.
Thereafter, an N-type epitaxial layer 4 that will become a collector layer is formed. An isolation oxide film 5 is formed on the surface of this N-type epitaxial N4 by means such as selective oxidation.

Next, a thermal oxide film with a thickness of about 300 people is formed on the region surrounded by the isolation oxide film 5 where a transistor element is to be formed, and then a base is formed using a resist (not shown) as a mask. An opening is made in the desired region, and phosphorus is applied to this opening at an acceleration voltage of 160 KeV and a dose of 4. OX 10”
Ion implantation is performed at a concentration of approximately cm-'' to form a N layer 6 as shown in FIG.

Subsequently, as shown in FIG. 3, after growing a silicon nitride film 7 containing only about 1,000 O4 over the entire surface, the silicon nitride film 7 is grown except for the emitter formation region and the portion where the collector electrode is taken out. The remaining portions are selectively removed using a photoetching method, and the oxide film 5 in the portion that will become the external base region around the emitter formation region is selectively removed using a photoetching method.
Then, using the two-layer films of the silicon nitride film 7 and the oxide film 5 as masks, boron is introduced into the silicon substrate 1 by ion implantation at an acceleration voltage of 10 KeV and a dose of about 1.0 x 10" -2. A mold external base region 9 is formed.

Thereafter, the resist 8 is removed, and then an oxide film 5 is grown to a thickness of about 2,000 O4 by thermal oxidation. At this time,
The P type external base region 9 located above the N+ layer 6 diffuses into the substrate 1 and penetrates deeper into the N'' layer 6 as shown in FIG. N″N6 that existed below disappears, and as a result, N′
The layer 6 remains only below the portion that should become the P-type physical base region between the P-type external base regions 9.
In the portion of the mold extrinsic base region 9 where the N' layer 6 is present, the impurity concentration of the N' layer 6 is lower than that of the extrinsic base region 9, so that the impurity concentration is lowered.

Next, the silicon nitride film 7 existing in the P-type material base formation region, emitter formation region, and collector electrode extraction region in FIG. 4 is removed, and the resist 8 is removed as shown in FIG. Boron was applied as a mask at an acceleration voltage of 20 KeV and a dose of 3. OX10
A P-type concrete base region 10 is formed by ion implantation at about I3 cm-''.

Then, the resist 8 was removed, and as shown in FIG. 6, the oxide film 5 in the emitter formation region and the collector electrode extraction region was removed, and the parts from which the oxide film 5 was removed were doped with arsenic. Polycrystalline silicon is formed and patterned using a photoetching method to form an emitter electrode 1) and a collector electrode 12. Thereafter, arsenic is diffused from the emitter electrode 1) and the collector electrode 12 into the P-type concrete base region 10 and the N-type epitaxial layer 4, respectively, to form an N-type emitter region 13 and a collector extraction region 14. Furthermore, if electrodes are formed by a well-known method (not shown), a bipolar transistor can be constructed.

The bipolar transistor manufactured in this way is
N″N having a higher impurity concentration than the N type epitaxial layer 4 which serves as a collector layer only directly under the P type base region 10.
6 is formed, and the impurity concentration of the P-type external base region 9 at the junction with the collector layer is lowered, so that in addition to reducing the base width and suppressing the base extrusion effect, the connection between the external base region and the collector layer is reduced. Interlayer junction capacitance is also reduced, and a bipolar transistor that responds at extremely high speed can be obtained.

<Effects of the Invention> As described above, by using the method for manufacturing a semiconductor device of the present invention, it is possible to form, for example, a N layer with an impurity concentration higher than that of the substrate only directly under the intrinsic base region, so that the base width can be reduced. In addition to increasing the transition frequency by reducing and suppressing the base extrusion effect at high current injection levels, it is possible to reduce the impurity concentration in the portion of the extrinsic base region in contact with the collector region, thereby reducing the impurity concentration between the extrinsic base region and the collector layer. It is possible to reduce the junction capacitance between the two and to obtain, for example, a bipolar transistor that responds at extremely high speed.

[Brief explanation of drawings]

1 to 6 are vertical cross-sectional views sequentially showing the manufacturing process of an embodiment of the present invention, and FIGS. 7 to 9 are vertical cross-sectional views sequentially showing the manufacturing process of a conventional manufacturing method. 1-.P-type silicon substrate (substrate) 4.-N-type epitaxial N (collection/-N'' layer (impurity layer) 9-.-P-type external base region 0.-P-type specific base region 3-Emitter Territory N)

Claims (1)

[Claims] (1) In a method for manufacturing a semiconductor device in which the emitter, collector, and base regions are formed vertically, and the base region includes two types of base regions, an intrinsic base region and an extrinsic base region, the collector and base regions are formed on a substrate. form a layer,
An impurity layer having a higher impurity concentration and the same type as that of the collector layer is formed in this collector layer, and an impurity having a higher concentration than the impurity layer is introduced into the surrounding portion of the impurity layer excluding the emitter formation region, and The method further comprises a step of forming the external base region by diffusing the impurity layer so as to have a deeper concentration distribution than the impurity layer, and sequentially forming the intrinsic base region and the emitter region on the remaining impurity layer. A method for manufacturing a semiconductor device.