JPH0345010A - Current source circuit - Google Patents

Abstract

PURPOSE:To reduce the settling time of an output voltage by varying an output current for a transient response period and outputting a current being the sum of a predetermined output current and an excess current in addition for a prescribed period, stopping the supply of the excess current and outputting only the prescribed current. CONSTITUTION:When a signal S at a terminal 2 changes from L to H, an output signal S1 of a sub current drive circuit 12 changes from L to H, switches 5, 8 are turned on and a sum (Ioo+Io1) of an output Ioo of a current source 1 an and output Io1 of a current source 7 is applied to a resistor 10 and a parasitic capacitor 11 via a terminal 3. Since the charge supplied to the parasitic capacitor 11 per unit time is much, the output voltage rises quickly. when the output voltage approaches an object IooR, only the output signal S1 of the sub current source drive circuit 12 changes to L again. Thus, the output voltage is settled to IooR. Thus, the voltage reply period is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a current source circuit, and particularly to a current source circuit that can shorten the transient response period of a current source.

[Conventional technology]

FIG. 7 shows a conventional current source circuit. l is a current source,
One terminal is connected to a constant potential, here a power supply potential, the other terminal of the current source 1 is connected to a terminal 3 via a switch 5, and the terminal 2 is connected to a control end of the switch 5. The current source 1 and the switch 5 constitute a current source circuit 4. A resistor 10 is connected to the terminal 3, and the other end of the resistor 10 is grounded. Note that 11 is a parasitic capacitance existing at the terminal 3.

Next, the operation will be explained.

Here, it is assumed that the switch 5 is turned on when an H level is applied to the terminal 2, and that the switch 5 is turned off when an L level is applied to the terminal 2. First, when the terminal 2 changes from the L level to the H level, the switch 5 is turned on, and the current output of the current source 1 is applied to the resistor 10 and the parasitic capacitance 11. At this time, even if the on-resistance of the switch 5 is zero and the output current Io immediately reaches the predetermined output level I0°, the output voltage immediately reaches the predetermined output level 1 novel. . It does not become R, i.e.
This is because in a transient state, the charge supplied by the output current is used to charge the parasitic capacitance.

Next, when terminal 2 goes from H level to L level, switch 5
turns off. At this time as well, the on-resistance of the switch 5 is zero, and even if the output current Io immediately becomes zero, the output voltage does not immediately become zero.

That is, this is because the discharge current of the parasitic capacitance 11 flows through the resistor 1o.

If the Laplace transform result of the current i,(t) applied to the resistor 10 is 1o(s), then the voltage vo(t) appearing at the terminal 3 is
The Laplace transform result Vo(s) of ) is as follows.

C: Parasitic capacitance value R: Resistance value of resistor 10 vo(o): Output voltage value in the initial state Here, if the step function is u(t) when switch 5 is turned on, then t 41 (t) −Ioo u (t)
・(2) vo (o) = O” (3) The Laplace transform result of equation (2) and equation (2) become (
1) By substituting into the equation and performing the inverse Laplace transform, the following equation is obtained.

Vo (t) = l00R(1-e −””)
= (4) Also, when switch 5 is turned off, io (t) = O... (5) Vo (o) = IooR - (6), and the Laplace transform result of equation (5) and equation (6) of(
1) By substituting into the equation and performing the inverse Laplace transform, the following equation is obtained.

Vo (t) -IooRe-”” ”(
7) The above operation is shown in FIG. Note that the deviation D(t) of the rising waveform and falling waveform from the final value is D(t)
-l Vo (t) -VO(00) l
・Given by (8), both rising and falling, D (t) ** I OORe −””
・=(9).

Here, the time for truly settling to the final value requires a time that is logically infinite from D(■)-0. Also, the final value is ±ΔV
If we set a window for D(t
)-ΔV, the settling time tsat becomes Δ■.

[Problem to be solved by the invention]

Since the conventional current source circuit is structured as described above,
There were drawbacks such as a long settling time for the output voltage to converge to the final value.

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a current source circuit that can shorten the settling time of the output voltage.

[Means for Solving the Problems] The current source circuit according to the present invention changes the output current value during the transient response period and outputs a current value obtained by adding surplus current to a predetermined output current value for a certain period of time. , after which the supply of surplus current is stopped and only a predetermined current value is output.

[Effect]

In this invention, since the bottom of the tank outputs a current obtained by adding surplus current to a predetermined output current value for a certain period during the transient response period, charging and discharging of the parasitic capacitance can be accelerated by this surplus current. .

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the bottom of a current source circuit according to an embodiment of the present invention capable of accelerating the rising waveform.

In FIG. 1, 2 and 7 are current sources, one terminal of which is connected to switches 5 and 8, respectively, and the other terminal of which is connected to a constant potential, here a power supply potential. 1
and 5 constitute a main current source 6, and 7 and 8 constitute a copper flow source 9 at the bottom of the tank. The output side terminals of the switches 5 and 8 are connected in common, and are connected to the output terminal 3 of the current source circuit 4. Further, the terminal 2 is a drive terminal of the current source circuit 4 and is input to the control terminal end of the switch 5 and the current control source drive circuit 12 .

The output of the current control source drive circuit 12 is connected to the control end of the switch 8.

In the above current source circuit, a resistor 10 is connected to the output terminal 3 as in the conventional example, and a parasitic capacitor 11 is connected to the terminal 3.
Suppose that it exists in .

Next, the operation will be explained.

The switch 5.8 receives the signals S, St applied to its control end.
Assume that it is turned on when is at H level.

First, when the signal S at the terminal 2 changes from L to H, the output signal S1 of the copper flow drive circuit 12 also changes from L to H. This turns on switch 5.8 and the current ? ttAl's output I0° and current [7's output■. The sum of the outputs of 1 (Ioo+I
o+) is applied to the resistor 10 and the parasitic capacitance 11 via the terminal 3. Therefore, Io. Compared to the conventional example in which only the voltage is applied, more charges are supplied to the parasitic capacitance 11 per unit time, so the output voltage rises faster. Next, when the output voltage approaches the target value 100R, the current control source drive circuit 12
Only the output signal S1 of is changed to L again. As a result, the output voltage is ■. . By changing the output of the current source circuit during the transient response period and then returning it to the original value, the transient response period can be shortened without changing the final output level.

Note that, as described above, the current control source drive circuit 12 receives the input signal S.
When becomes H, it is necessary to have a function of outputting H for a certain period of time and then outputting L again, and an example of its implementation will be described later.

Furthermore, although the first embodiment described above is an example in which the settling time at the time of rising is shortened, a second embodiment of the present invention is shown in FIG. In Figure 0 shown in Figure 1, 1 to 12 have the same configuration as the first embodiment. In addition to this, numerals 13 to 16 are provided to shorten the falling settling time. 13 is a current source;
A switch 14 is connected to its negative end, and the other end is connected to a constant potential, here a ground potential. 13 and 14 form a second copper flow source 15. The other end of the switch 14 is connected to the terminal 3 which is the output terminal of the current source circuit 4.

The second limiting current source drive circuit 16 has an input terminal connected to a terminal 2 which is a control terminal of the current source circuit 4, and an output terminal connected to a control terminal of the switch 14.

Next, the operation will be explained.

Since the rising operation is the same as the first embodiment,
The falling operation will be described. In the first embodiment, the switch 8 is turned on when the signal S changes from L to H, and is turned off again after a certain period of time. On the other hand, the switch 5 remains on as long as the signal S is H. Therefore, when considering the falling transient response, the initial state is that switch 5 is on, switch 8 is off, and the potential of terminal 3 is I. Taking into account 0 or more which is OR, the operation is as follows.

When the signal S changes from H to L, the output S2 of the second current control source drive circuit 16 changes from L to H.

As a result, switch 5 is turned off and switch 14 is turned on. Further, the switch 8 remains off. The output of the it flow source 13 is I. , and considering the direction of the current,
tot flows from terminal 3 toward the current source. Therefore, the charge discharged from the parasitic capacitance 11 per unit time increases compared to the conventional example in which the charge is discharged only through the resistor. That is, the output voltage falls faster than in the conventional example. When the zero-order output voltage approaches the target value of zero, only the output signal S2 of the second current control source drive circuit 16 changes to L again.

This causes the output voltage to settle to zero.

In this way, by changing the output of the current source circuit during the transient response period and then returning it to the original value, the transient response period can be shortened without changing the final output level.

Note that a specific configuration example of the second current control source drive circuit 16 will also be described later.

FIG. 3 shows a current source circuit according to a third embodiment of the present invention, 100 is a voltage controlled current source, one of the current paths is connected to a constant voltage, here a power supply voltage, and the other is a terminal. Connected to 3.

Reference numeral 101 denotes a control voltage generation circuit, whose output is connected to the control terminal of the voltage-controlled current source 100 and whose input is connected to the terminal 2.

Note that the voltage-controlled current source 100 and the control voltage generation circuit 101
constitutes a current source circuit 4. Here, a resistor 10 is connected to the output terminal 3 of the current source circuit 4, and the other end of the resistor 10 is grounded. Note that 11 is the parasitic capacitance of the terminal 3, as in the previous two embodiments.

Next, the operation will be explained.

When the signal S applied to terminal 2 changes from L to H,
The output VC of the control voltage generation circuit 101 is from VCL to VcH.
e, and after being at VC+4+ for a certain period of time, it becomes VCH. Further, when S changes from H to L, the output vc of the control voltage generation circuit 101 changes from vc)l to V Ct-, and becomes VCL after being at v0- for a certain period of time.

A specific example of the configuration of the circuit 101 that generates such a voltage change will be described later.

When Vc is vcL, the output of the voltage controlled current source 100 is zero, and when Vc is Vell, the output is a predetermined output ■. . Then, the operation will be as follows. When the signal S changes from L to H, v
c changes from vcL to VCN-. Accordingly,
The output of current source 100 is from zero to Io. Greater output (I
o. ＋■. , ) and is applied to the resistor 10 and the parasitic capacitance 11 via the terminal 3. Therefore, ■. . Since more charges are supplied to the parasitic capacitance per unit time than in the conventional example in which only a voltage is applied, the output voltage rises quickly.

Next, when the output voltage approaches the target value I0°R, Vc becomes V
Changes to CX. As a result, the output of current source 100 is I
. . When the signal S changes from H to L while settling to R, Vo changes from VCN to VCL-.

In response, the output of the current source 100 is a negative current ■. Outputs 3. That is, the current direction is flowing from the terminal 3 to the current source circuit 4. Therefore, the charge discharged from the parasitic capacitance 11 per unit time increases compared to the conventional example in which the charge is discharged only through the resistor. That is, the output voltage falls faster than in the conventional example, and when the zero-order output voltage approaches the target value of zero, vc becomes ■. - to vcL, current source 1
The output current of 00 is zero. As a result, the output voltage settles to zero. In this way, after changing the output of the current source circuit during the transient response period, by returning it to a predetermined value, the transient response period can be completed without changing the final output level. Can be shortened.

The operation of the above embodiment is shown in FIG.

The operation of the first embodiment corresponds to the rising response of the second embodiment, so its explanation will be omitted. Further, the output current and voltage of the second example and the third example were combined into one. In the output voltage plot diagram, 200a and 200b are output waveforms in the conventional example. Also! . −■. . +Io
Assuming that the + period continues for tp, the waveform during this period is 201a.

The waveform after that is indicated by 202a. Also ■. =
Assuming that the period of -1°2 continues for t, l, the waveform during this period is shown as 201b, and the waveform after that is shown as 202b. Moreover, the output current of 203a and 203b is ■.

. +IO+ and -IO! This is the waveform assuming that it remains held at .

In the rising waveform, if the step function is u (t), then 1o(t)=Ioou(t)+Io+u(t) I
o+u(t-tp)...-0v0(o) =0
=OD. By substituting the Laplace transform result of the 00 formula and the 00 formula into the formula (1) and performing the inverse Laplace transform, the following formula is obtained.

V (t) = IooR(1-e-””)+I
o+R(1-e-"") -Q7J(Q<t<tF
) v (t) = IooR(1-e-””)+I
o+R(1-e-””)1 o+R(1-e-”-”
"") (t < t p ) -03) In the falling waveform, i6 (t) -1ozu(t) + Iatu(t
LM) ””(+4)Vo (0) ” 10
0R-(151.(Substituting the Laplace transform result of equation 14 and equation 09 into equation (1) and performing the inverse Laplace transform, to (t) -I ooRe-"")-1oJ(
1-e-"") ・-a6) (0<t<tH) to (t) ""I,,Re-"")-I oz
R(1-e-””)+IozR(1-e-′t-”””
) (t<tN)...(!7), Q21.
03), 06), Q7j equations are respectively curves 201a20
2a, 201b, and 202b.

Here, I O+ or ■. ■. 8, t, or 1) I
By replacing t8 with t8, the deviation D of the rising waveform and falling waveform
When calculating X (t), from equation (8), both rising and falling DX (t) = RI I ooRe-"")-I
ox(1-e-””) l ・”08)(0<txtx
) DX (t) = RI Ioo-1ox(e”'c
"-1) l e-""=09)(t<tX), where the time 1o when the waveform reaches its final value for the first time
To find Dx(t+)=0 in formula 08), we get As a result, it can be seen that DX (t)=O(t<tX) (22) Also, from equation (21), ■.It can be seen that the larger 8 is, the closer t8 is to zero. That is,
Io at the rising edge at the moment the signal S changes. +I
An output current of -1°8 is applied during the falling edge, and at the moment the output voltage reaches the m value IooR or zero, the output current is Io applied during the rising edge. By setting the output current to zero at the falling edge, it is possible to truly stabilize in a finite time. Further, this settling time can be made as small as desired by increasing the current value 101 or hot.

Even if tX does not match to, the settling time can be shortened as long as t8 is within a certain range. In the case of the present invention, the deviation from the final value of the waveform when the waveform approaches the final value is given by equation 09. Here, if foe>Io. −1,, (et”/el −1) >
100・(24)2 is established. Equation (24) and (8)
, from formula 09, DX (t) <D(t)
...(25) holds true. That is, (2
It can be seen that within the range where equation 3) holds true, the final value of the waveform in the embodiment of the present invention is always smaller than in the conventional example, and that the embodiment of the present invention shortens the settling time.

Next, a specific configuration example of the current control source drive circuit and the control voltage generation circuit is shown in FIG. 5(a).

The current control source drive circuits 12 and 16 are combined into one circuit here and designated by 99. Further, the control voltage generation circuit is configured as shown in 101 using a sub-type current source 99. The signal S is input to an inverter 310 and a delay circuit 301, the inverter 310 inputs an inverted signal Sa, and the delay circuit 301 inputs tx to S.
A delayed signal sb delayed by the amount of time is generated. Sa, Sb are N0
It is input to R311 and AND312. NOR31
1's output S1 is Sa,! : H only when both Sb are L
Therefore, as shown in the waveform diagram of FIG. 5(b), the signal remains H for a time tx from the rise of S. AN
Since the output S2 of D312 becomes H only when both Sa and sb are H, as shown in FIG. 5(b), a signal that is 0 or more and remains H for a time tx from the fall of S is a limiting current source. This is the configuration and operation of the drive circuit.

The control voltage generation circuit includes the above-mentioned current control source drive circuit. 30
2, 303, 304, 305 are each VCLvCL-i
It is a voltage source having an output of CM or +VC+4, and is connected to a control voltage output terminal 315 via switches 306, 307, 308, and 309, respectively.

Switches 308 and 307 are opened and closed by direct signals 31.32. Here, the switch has a signal at the control end that is H.
It is assumed that it is turned on when . Therefore, Sl and S2
During the period when is H, as shown in FIG. 5(b), vc becomes VCN+ and vcL-, respectively.

Since the signals Sa and sl are input to the N0R 313, its output S3 becomes H only when these two signals Sa and Sl are both L, and has the waveform shown in FIG. 5(b). Therefore, the switch 309 is on during this period, and
, becomes VCH. N again.

Since the signals S and 82 are input to R314, its output 'S4 becomes H only when these two signals S and 32 are both L, and has the waveform shown in FIG. Therefore, during this period, the switch 306 is on, and vc is
becomes. In this way, a waveform as shown in FIG. 5(b) is obtained from the terminal 315 as the control IT pressure.

Incidentally, as a specific example of the structure of the delay circuit 301, one in which an even number of inverters are connected as shown in FIG. 6 is widely known. A desired delay can be obtained by appropriately designing the driving capacity of the inverter.

Further, this delay circuit may have a configuration other than this.

Furthermore, in the above embodiment, the specific configurations of the delay circuit, the copper flow S drive circuit, and the current source circuit are shown, but the current source ultimately outputs two values, and a third output during the transient response period. It is sufficient if the value is maintained for a certain period of time, and the same effect as above is achieved.

The voltage controlled current source in the third embodiment needs only to output three or four different output currents for three or four different control voltages, and has a specific relationship between the control voltage and the output current, e.g. There is no need to have a linear relationship.

〔Effect of the invention〕

As described above, according to the present invention, the current source circuit changes the output current value during the transient response period, outputs a current value obtained by adding surplus current to the predetermined output current value for a certain period of time, and then Since the configuration is such that the supply of surplus current is stopped and only a predetermined current value is output, charging and discharging of the parasitic capacitance can be accelerated by this surplus current, which has the effect of shortening the voltage response period.

[Brief explanation of drawings]

FIGS. 1, 2, and 3 show the first part of this invention. 2nd, 3rd
4 is a diagram for explaining the operation of the embodiment, FIG. 5 is a diagram for explaining the sub-type current source drive circuit and the control voltage generation circuit, and FIG. 6 is a delay circuit. 7 is a diagram showing a configuration example of a conventional current source circuit,
FIG. 8 is a diagram for explaining the operation of a conventional current source circuit. 1 is a current source, 2 is a drive terminal (logic signal application terminal) of the current source circuit, 3 is an output terminal, 4 is a current source circuit, 6 is a main current source, 7.13 is a sub current source, 5, 8.14 is a switch, 9.
15 is an auxiliary current source, 10 is a resistor, 11 is a parasitic capacitance, 12.
16 is a sub-type current source driving means, 100 is a voltage controlled current source, 1
01 is a control voltage generation circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) Has a current output terminal and is driven by a binary logic signal,
In a current source circuit that outputs a predetermined output current in response to this, the current source circuit outputs a current value other than the predetermined output current value within a transient response period of the voltage of the output terminal. source circuit.