JPH0344289A - Subscriber line signal processing system - Google Patents

Subscriber line signal processing system

Info

Publication number
JPH0344289A
JPH0344289A JP18121089A JP18121089A JPH0344289A JP H0344289 A JPH0344289 A JP H0344289A JP 18121089 A JP18121089 A JP 18121089A JP 18121089 A JP18121089 A JP 18121089A JP H0344289 A JPH0344289 A JP H0344289A
Authority
JP
Japan
Prior art keywords
layer
line
processor
signal
subscriber line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18121089A
Other languages
Japanese (ja)
Inventor
Koichi Murata
村田 幸一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18121089A priority Critical patent/JPH0344289A/en
Publication of JPH0344289A publication Critical patent/JPH0344289A/en
Pending legal-status Critical Current

Links

Landscapes

  • Sub-Exchange Stations And Push- Button Telephones (AREA)

Abstract

PURPOSE:To improve the economy of the hardware by sending and receiving layer 2 management information between a signal equipment and a main controller while relaying a processor of a line concentrator and sending and receiving layer 3 information directly. CONSTITUTION:A line concentrator 5 and processors of a signal device 8, and the line concentrator 5, the signal device 8 and processors of a main controller 13 are interconnected respectively by independent inter-processor buses 11, 12. Then the transmission reception of data link layer (layer 2) management information between the signal device 8 and the main controller 13 is implemented via processors of the line concentrator 5 and the transmission reception of data link layer (layer 2) management information of network layer (layer 3) information is implemented directly. The signal device 8 is used in common, then an irreducible minimum number of signal devices 8 have only to be installed in response to the utility rate of a subscriber line 1 and the economy of the hardware at a large scale is improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は加入者線信号処理方式に関し、特にCCITT
勧告Iシ勧告ダシリーズたl5DNユーザ網インタフエ
ースにおける加入者線信号処理方式に関するものである
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a subscriber line signal processing system, and in particular to a CCITT
Recommendation I Recommendation series concerns the subscriber line signal processing system at the 15DN user network interface.

〔従来の技術〕[Conventional technology]

従来、この種の加入者線信号処理方式において、データ
リンクレイヤ(レイヤ2)処理を行う信号装置は加入者
線に1:1にくくりつけになっていた。
Conventionally, in this type of subscriber line signal processing system, signaling devices that perform data link layer (layer 2) processing have been attached to subscriber lines in a 1:1 ratio.

従来の加入者線信号処理装置の一例を第2図に示す。第
2図において、加入者線21を終端する回線終端回路2
2からは加入者線信号線23と回線同期信号24が信号
装置25に引き込まれている。信号装置25は加入者線
信号のレイヤ2処理を行う加入者線対応に設けられたレ
イヤ2信号処理回路26と複数のレイヤ2信号処理回路
26の制御と回線同期信号の監視を行うプロセッサ27
から構成され、プロセッサ27はレイヤ2管理とネット
ワーク(レイヤ3)処理を行う主制御装置29のプロセ
ッサ30とプロセッサ間バス28により結合されている
。信号装置25と主制御装置29との間のレイヤ2管理
情報及びレイヤ3情報の送受はプロセッサ間バス28を
経由して行われる。
An example of a conventional subscriber line signal processing device is shown in FIG. In FIG. 2, a line termination circuit 2 that terminates a subscriber line 21
2, a subscriber line signal line 23 and a line synchronization signal 24 are led into a signaling device 25. The signaling device 25 includes a layer 2 signal processing circuit 26 provided for the subscriber line that performs layer 2 processing of subscriber line signals, and a processor 27 that controls the plurality of layer 2 signal processing circuits 26 and monitors line synchronization signals.
The processor 27 is connected by an inter-processor bus 28 to a processor 30 of a main controller 29 that performs layer 2 management and network (layer 3) processing. Transmission and reception of layer 2 management information and layer 3 information between the signaling device 25 and the main control device 29 is performed via the inter-processor bus 28.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の加入者線信号処理装置では、加入者線規
模が増えるに比例して加入者線対応のレイヤ2信号処理
回路26を必要とする。また、信号装置25のプロセッ
サ27が制御できるレイヤ2信号処理回路25の数にも
限界があることから信号装置25も多く必要となり、主
制御装置29とのプロセッサ間バス28の結合部も増加
する。
In the above-mentioned conventional subscriber line signal processing device, the layer 2 signal processing circuit 26 corresponding to the subscriber line is required in proportion to the increase in the scale of the subscriber line. Furthermore, since there is a limit to the number of layer 2 signal processing circuits 25 that can be controlled by the processor 27 of the signal device 25, more signal devices 25 are required, and the number of connections between the inter-processor bus 28 and the main control device 29 increases. .

しかしながら、加入者線は常時起動されている訳ではな
く、局条件にもよるが、ある一定の使用率で使用されて
いるため、加入者線収容数が増えるほど、同時には使用
されないレイヤ2信号処理回路26が増えることになり
、特に大規模構成時にハードウェアの経済性が悪くなる
という欠点がある。
However, subscriber lines are not activated all the time and are used at a certain usage rate, depending on the station conditions, so as the number of subscriber lines increases, layer 2 signals that are not used simultaneously This increases the number of processing circuits 26, which has the disadvantage of worsening the economy of hardware, especially in large-scale configurations.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の加入者線信号処理方式は、加入者線信号を引き
込み集線及び分配を行う集線スイッチとこの集線スイッ
チの制御と前記加入者線の同期監視を行うプロセッサか
らなる集線装置と、この集線装置の分配側端子を引き込
みデータリンクレイヤ(レイヤ2)処理を行うプロセッ
サを有する信号装置と、レイヤ2管理及びネットワーク
レイヤ(レイヤ3)処理を行うプロセッサを有する主制
御装置とから構成し、前記集線装置と前記信号装置のプ
ロセッサ間及び前記集線装置、信号装置。
The subscriber line signal processing system of the present invention includes a line concentrator including a line concentrator that draws in, concentrates and distributes subscriber line signals, a processor that controls the line concentrator switch and synchronously monitors the subscriber line, and the line concentrator. The line concentrator is composed of a signal device having a processor that draws in the distribution side terminal of the line and performs data link layer (layer 2) processing, and a main control device that has a processor that performs layer 2 management and network layer (layer 3) processing. and the processor of the signal device, the line concentrator, and the signal device.

主制御装置のプロセッサ間をそれぞれ独立したプロセッ
サ間バスで結合した加入者線信号処理装置において、前
記信号装置と前記主制御装置間のレイヤ2管理情報の送
受は前記集線装置のプロセッサを中継して行い、レイヤ
3情報の送受は直接行うことを特徴とする。
In a subscriber line signal processing device in which the processors of the main control device are connected by independent inter-processor buses, transmission and reception of layer 2 management information between the signal device and the main control device is carried out by relaying the processor of the line concentrator. The feature is that layer 3 information is transmitted and received directly.

〔実施例〕〔Example〕

次に、本発明について第1図を参照して説明する。 Next, the present invention will be explained with reference to FIG.

第1図は本発明の一実施例を示す加入者線信号処理装置
のブロック図である。
FIG. 1 is a block diagram of a subscriber line signal processing device showing one embodiment of the present invention.

第1図において、加入者線lを終端する回線終端回路(
以下LT)2からは加入者線信号線3と回線同期信号線
4が集線装置5に引き込まれている。集線装置5は加入
者線信号線4を集線及び分配する集線スイッチ(以下5
W)8と、SW6の制御と回線同期信号の監視を行うプ
ロセッサC以下PRA)7から構成されている。SW6
の分配側端子は信号装置8に接続されている。信号装置
8は1つの加入者線信号のレイヤ2処理を行うレイヤ2
信号処理回路(以下5P)9と複数の信号処理回路9の
制御を行うプロセッサ(以下FRB)10から構成され
る。集線装置5のPRA 7と信号装置80PRBIO
との間はプロセッサ間バスA(以下BA)11で結合さ
れ、集線装置5のPRA7と主制御装置13のプロセッ
サ(以下CPU)14との間及び信号装置8のPRBI
Oと主制御装置13のCPU14との間はプロセッサ間
バスB(以下BB)12で結合されている。
In Figure 1, a line termination circuit (
A subscriber line signal line 3 and a line synchronization signal line 4 are led from the LT (hereinafter referred to as LT) 2 to a line concentrator 5. The line concentrator 5 is a line concentrator switch (hereinafter referred to as 5) that concentrates and distributes the subscriber line signal lines 4.
W) 8, and a processor C and below PRA) 7 which control the SW 6 and monitor line synchronization signals. SW6
The distribution side terminal of is connected to the signal device 8. The signaling device 8 is a layer 2 signal that performs layer 2 processing of one subscriber line signal.
It is composed of a signal processing circuit (hereinafter referred to as 5P) 9 and a processor (hereinafter referred to as FRB) 10 that controls the plurality of signal processing circuits 9. Concentrator 5 PRA 7 and signaling device 80PRBIO
are connected by an inter-processor bus A (hereinafter referred to as BA) 11, and between the PRA 7 of the line concentrator 5 and the processor (hereinafter referred to as CPU) 14 of the main control unit 13 and the PRBI of the signal device 8.
The interprocessor bus B (hereinafter referred to as BB) 12 connects O and the CPU 14 of the main controller 13.

集線装置5のPRA7は回線同期信号を監視し、同期確
立した加入者線のみのSW6を制御することにより、信
号装置8の空きのSF3の1つに接続する。同時に、B
B12を経由して主制御装置13にその加入者線の同期
確立を通知する。次に、集線装置5を介して回線同期の
確立した加入者線信号線3を引き込んでいるSF3がレ
イヤ2の確立を検出すると、PRBIOがそれを検出し
、BAllを経由して集線装置5のPRA7に転送する
。この時、PRBIOはレイヤ2のリンク確立情報にS
F90回路番号を付与して転送する。その後、集線装置
5のPRA7はレイヤ2のリンク確立情報をBB12を
経由して主制御装置13のCPU14に転送する。この
時、PRA7はSF90回路番号を加入者線lの回線番
号に変換して転送する。このようにして、信号装置8と
主制御装置13との間でレイヤ2管理情報の送受を行う
The PRA 7 of the line concentrator 5 monitors the line synchronization signal and connects to one of the vacant SFs 3 of the signaling device 8 by controlling the SW 6 of only the subscriber line that has established synchronization. At the same time, B
The establishment of synchronization of the subscriber line is notified to the main controller 13 via B12. Next, when the SF 3, which pulls in the subscriber line signal line 3 whose line synchronization has been established via the line concentrator 5, detects the establishment of layer 2, PRBIO detects this and connects the line concentrator 5 via the BAll. Transfer to PRA7. At this time, PRBIO uses S as layer 2 link establishment information.
Give the F90 circuit number and transfer. Thereafter, the PRA 7 of the line concentrator 5 transfers the layer 2 link establishment information to the CPU 14 of the main control device 13 via the BB 12. At this time, PRA 7 converts the SF90 circuit number into the line number of subscriber line 1 and transfers it. In this way, layer 2 management information is transmitted and received between the signaling device 8 and the main control device 13.

レイヤ3情報は大量のデータ転送を伴うため、上記の方
法では効率が悪くなる。このため、BB12を介して信
号装置8と主制御装置9との間で直接データ転送を行う
。その後、レイヤ3情報のデータ転送終了通知なレイヤ
2管理情報の通知と同様の方法にて行う。また、信号装
置8がレイヤ3情報を転送できる主制御装置13のメモ
リアドレスは、あらかじめレイヤ2管理情報の送受と同
様の方法にて主制御装置13から信号装置8に通知して
おく。集線装置・5のPRA7は回線同期信号監視によ
り同期外れを検出すると、プロセッサ間バスを経由して
主制御装置13にその加入者線の同期外れを通知すると
ともに、その加入者線1は未使用状態になったと判定し
てSW6を制御し、加入者線信号線3とSF3とのパス
を開放してSF3を空き状態にする。
Since Layer 3 information involves a large amount of data transfer, the above method is inefficient. For this reason, direct data transfer is performed between the signaling device 8 and the main control device 9 via the BB12. Thereafter, the data transfer end notification of the layer 3 information is performed in the same manner as the notification of the layer 2 management information. Furthermore, the memory address of the main control device 13 to which the signaling device 8 can transfer the layer 3 information is notified in advance from the main control device 13 to the signaling device 8 using the same method as for sending and receiving the layer 2 management information. When the PRA 7 of the line concentrator 5 detects the loss of synchronization by monitoring the line synchronization signal, it notifies the main controller 13 of the loss of synchronization of the subscriber line via the inter-processor bus, and also indicates that the subscriber line 1 is not in use. When it is determined that the condition has been reached, the SW6 is controlled, the path between the subscriber line signal line 3 and the SF3 is opened, and the SF3 is made vacant.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明による加入者線信号処理装置
では、信号装置を共通的に使用することにより、加入者
線の使用率に応じて必要最小限の信号装置を設置すれば
良く、特に大規模時のハードウェアの経済性に優れてい
るという効果がある。
As explained above, in the subscriber line signal processing device according to the present invention, by using the signaling devices in common, it is only necessary to install the minimum necessary signal devices depending on the usage rate of the subscriber line, and especially large This has the effect of being excellent in hardware economy when scaled.

また、集線装置のプロセッサにより回線番号とレイヤ2
信号処理回路番号との交換を行うため、主制御装置のソ
フトウェアは信号装置の番号及びその信号装置内のレイ
ヤ2信号処理回路の番号を意識することなく、加入者線
の回線番号で一元的に管理できるので管理が容易になる
という効果がある。
In addition, the line number and layer 2
In order to exchange with the signal processing circuit number, the software of the main control unit can centrally exchange the line number of the subscriber line without being aware of the number of the signaling device or the number of the layer 2 signal processing circuit within the signaling device. This has the effect of making management easier because it can be managed.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す加入者線信号処理装置
のブロック図、第2図は従来の加入者線信号処理装置の
一例を示すブロック図である。 1・・・・・・加入者線、2・・・・・・回線終端回路
(LT)、3・・・・・・加入者線信号線、4・・・・
・・回線同期信号線、5・・・・・・集線装置、6・・
・・・・集線スイッチ(SW)、7・・・・・・プロセ
ッサ(PRA)、8・・・・・・信号装置、9・・・・
・・レイヤ2信号処理回路(S P)、10・・・・・
・プロセッサ(FRB)、11・・・・・・プロセッサ
間ノクスA (BA)、12・・・・・・プロセッサ間
ノくスB (BB)、13・・・・・・主制御装置、1
4・・・・・・プロセッサ(CP U)。
FIG. 1 is a block diagram of a subscriber line signal processing device showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional subscriber line signal processing device. 1...Subscriber line, 2...Line termination circuit (LT), 3...Subscriber line signal line, 4...
...Line synchronization signal line, 5... Line concentrator, 6...
... Line concentration switch (SW), 7 ... Processor (PRA), 8 ... Signal device, 9 ...
...Layer 2 signal processing circuit (SP), 10...
- Processor (FRB), 11... Inter-processor node A (BA), 12... Inter-processor node B (BB), 13... Main controller, 1
4... Processor (CPU).

Claims (1)

【特許請求の範囲】[Claims] 加入者線信号を引き込み集線及び分配を行う集線スイッ
チとこの集線スイッチの制御と前記加入者線の同期監視
を行うプロセッサからなる集線装置と、この集線装置の
分配側端子を引き込みデータリンクレイヤ(レイヤ2)
処理を行うプロセッサを有する信号装置と、レイヤ2管
理及びネットワークレイヤ(レイヤ3)処理を行うプロ
セッサを有する主制御装置とから構成し、前記集線装置
と前記信号装置のプロセッサ間及び前記集線装置、信号
装置、主制御装置のプロセッサ間をそれぞれ独立したプ
ロセッサ間バスで結合した加入者線信号処理装置におい
て、前記信号装置と前記主制御装置間のレイヤ2管理情
報の送受は前記集線装置のプロセッサを中継して行い、
レイヤ3情報の送受は直接行うことを特徴とする加入者
線信号処理方式。
A line concentrator consists of a line concentrator that draws subscriber line signals, concentrates and distributes them, a processor that controls the line concentrate switch and synchronizes and monitors the subscriber lines, and a data link layer (layer 2)
It consists of a signaling device having a processor that performs processing, and a main control device having a processor that performs layer 2 management and network layer (layer 3) processing, and between the line concentrator and the processor of the signal device, and between the line concentrator and the signal In a subscriber line signal processing device in which processors of a device and a main control device are connected by independent inter-processor buses, transmission and reception of layer 2 management information between the signal device and the main control device is relayed through the processor of the line concentrator. and do it,
A subscriber line signal processing system characterized by direct transmission and reception of layer 3 information.
JP18121089A 1989-07-12 1989-07-12 Subscriber line signal processing system Pending JPH0344289A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18121089A JPH0344289A (en) 1989-07-12 1989-07-12 Subscriber line signal processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18121089A JPH0344289A (en) 1989-07-12 1989-07-12 Subscriber line signal processing system

Publications (1)

Publication Number Publication Date
JPH0344289A true JPH0344289A (en) 1991-02-26

Family

ID=16096757

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18121089A Pending JPH0344289A (en) 1989-07-12 1989-07-12 Subscriber line signal processing system

Country Status (1)

Country Link
JP (1) JPH0344289A (en)

Similar Documents

Publication Publication Date Title
JP3158223B2 (en) Connection method for connecting switching network with originating processor and source processor
EP0817092A3 (en) Extended symmetrical multiprocessor architecture
JPS6163139A (en) Communication protocol controller
CA1194190A (en) Common channel interoffice signaling system
JPH0344289A (en) Subscriber line signal processing system
JPS5831637A (en) Multiplex processor
JPH03108837A (en) Time division bus control circuit
JP2715137B2 (en) Communication network control method
JPS58116897A (en) Time-division multiplex transmission system
JPH04148262A (en) Multi-address transfer device
KR0129612B1 (en) Apparatus for the con of hardware component of concentrated b-nt system
JPS5952947A (en) Bi-directional communicating system
SU840867A1 (en) Device for interfacing computers
JPS6077255A (en) Control system of plural buses
JPH0278354A (en) Maintenance information collecting system
JPS62243039A (en) Processor state monitoring system for decentralized control type switchboard
JPH04291430A (en) Program tracing system
JPH0117625B2 (en)
EP0306886A3 (en) Apparatus for in band connection establishment in multiple multi-drop networks
JPS60174546A (en) Control method of data transmission equipment
JPH0895927A (en) Large scale mutual connection switch
JPS63155993A (en) Subscriber line signal line concentration system
JPH04289946A (en) Collection/distribution repeater system
JPS63141429A (en) Packet multiplexer
JPH05210611A (en) Inter-processor communication control method in multipoint connecting system