JPH05210611A - Inter-processor communication control method in multipoint connecting system - Google Patents

Abstract

PURPOSE:To shorten a delay time until communication data is transmitted actually after it is generated, and also, to reduce a processing load of a control side processor and a subordinate side processor, with regard to an inter- processor communication method in the multipoint connecting system in which plural pieces of subordinate side processors are connected to the control side processor. CONSTITUTION:In the inter-processor communication control method in the multipoint connecting system in which plural pieces of subordinate side processors #1-#N are connected to a control side processor #0, control lines CL#1-CL#N are provided between the control side processor #0 and plural subordinate side processors #1-#N, respectively, and when a data transmitting request is generated in the own processors, the subordinate side processors #1-xsiN transmit the data transmitting request to the control side processor #0 through the own control line, and the control side processor #0 monitors each control line CL#1-CL#N and when a data transmitting request of the subordinate side processor #K is detected, a communication is executed by connecting a circuit to its subordinate side processor #K.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interprocessor communication method in a multipoint connection system in which a plurality of slave side processors are connected to a control side processor. In such an inter-processor communication method, when transmission data is generated in each subordinate processor, it is necessary to be able to transmit the transmission data to the control processor without delay.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional multipoint connection type CPU (central processing unit) configuration. In the figure, 6 is the controlling CPU, 7 _# 1 _{~7 #N} are N number of subordinate CPU, among CPU6,7 _# 1 ~7 _#N are interconnected by a single communication line 8 .. Conventionally, the communication between the control side CPU and each subordinate side CPU in this multipoint connection system has been performed as shown in FIG.
This is realized by the control-side CPU 6 sequentially polling the N subordinate-side _CPUs 7 _{# 1 to} 7 _#N as shown in the transmission sequence.

[0003]

Therefore, in order for the Kth subordinate CPU 7 _#K to transfer data to the control CPU 6, the control CPU 6 is the first subordinate CPU 7 _{# 1.}
It waits until its own turn (Kth) comes after polling sequentially from, and then performs data transfer after being polled. Thus, the Kth subordinate CPU
7 If _{you #K} to the transmission data is generated, so that the K-th dependent side CPU7 _#K waits for data transmission until their turn comes, delay in data transmission occurs. For example, when the number of subordinate CPUs is N, and the polling time required for one subordinate CPU is t, the delay time T is T = (ΣK × t) / N [where Σ is K Represents the integral from 1 to N].

Further, the control side CPU 6 periodically receives N number of subordinate side CPUs 7 _{# 1} ...
7 _#N polls all, so the processing load is _heavy . Further, the subordinate _CPUs 7 _{# 1 to} 7 _#N also _{impose a} processing load because the polling from the control CPU 6 determines whether or not the polling is for its own station and returns a response.

The present invention has been made in view of the above circumstances, and an object of the present invention is to shorten the delay time from the generation of communication data to the actual transmission of the communication data, and to reduce the delay time from the control side processor. This is to reduce the processing load of the side processor.

[0006]

FIG. 1 is an explanatory view of the principle of the present invention. The interprocessor communication control method in the multipoint connection system according to the present invention is the interprocessor communication control method in the multipoint connection system in which a plurality of slave side processors # 1 to #N are connected to the control side processor # 0. The control line C is provided between the control side processor # 0 and the plurality of subordinate side processors # 1 to #N.
L _{# 1 to} CL _#N are provided, and subordinate processors # 1 to #N
Sends a data transmission request to the control side processor # 0 via its own control line when a data transmission request is generated by itself,
The control side processor # 0 monitors each of the control lines CL _{# 1 to} CL _#N, and when it detects a data transmission request from the subordinate side processor #K, it connects to the subordinate side processor #K for communication. It is a thing.

The inter-processor communication control method in the multipoint connection system according to the present invention is the inter-processor communication control method described above, in which the control side processor # 0 and the plurality of subordinate side processors # 1 to #N are connected. data communication line TL _# 1 ~TL _#N are respectively provided, the control-side processor # 0 line switching to the switching circuit SW is provided in each data communication line TL _# 1 ~TL _#N, the controlling processor # 0
When a data transmission request is detected from the control line CL _#K , the switching circuit SW switches the line to the data communication line TL _#K of the slave processor #K that issued the data transmission request.

[0008]

When the subordinate processors # 1 to #N generate their own data transmission requests, the subordinate processors # 1 to #N transmit the data transmission request to the control side processor # 0 via their own control lines. The control side processor # 0 monitors each of the control lines CL _{# 1 to} CL _#N, and when it detects a data transmission request from the subordinate side processor #K, it connects to the subordinate side processor #K to perform communication. For example, the control side processor # 0 connects the control line C to this line connection.
When a data transmission request is detected from L _{# K} , the switching circuit S
This can be realized by selecting the data communication line TL _#K of the subordinate processor #K that issued the data transmission request by W and switching the line.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a CPU system of a multipoint connection system for carrying out an interprocessor communication method as an embodiment of the present invention. This CPU system can be applied to, for example, a line control device (control station side) of a pager system and a device (subordinate station side) that accommodates a telephone line. In the figure, 1 is a control station, 2 _{# 1} to 2 _#N are N dependent stations, and individual data communication is _performed between the control station 1 and each dependent station 2 _{# 1} to 2 _#N for data transfer. Lines 3 _{# 1 to} 3 _#N are provided, and individual control lines 4 _{# 1} to 4 _#N are provided for control signal transfer.
Asynchronous serial data transmission by RS232C is _performed on the data communication lines 3 _{# 1 to} 3 _#N .

Each of the subordinate stations 2 _{# 1} to 2 _#N is a subordinate CPU 2
1, a serial communication controller 22, a decoder 23, a register 24, a buffer 25, a memory 26 and the like. The serial communication controller 22 is a circuit that controls data transmission with the control station 1 via the corresponding data communication line 3. The decoder 23 has a subordinate CPU 21.
To the address bus, and when the address of the register 24 is designated by the subordinate CPU 21 via this address bus, it is decoded and turned on to the register 24.
Configured to write a bit. The output side of the register 24 is connected to the control line 4 corresponding to the own station via the buffer 25.

The control station 1 includes a control side CPU 11, a serial communication controller 12 for controlling data transmission between the subordinate stations 2 _{# 1} to 2 _#N, and a data communication line 3 according to an address signal from the control side CPU 11. Switch circuit 13 for selecting one of _{# 1 to} 3 _#N , control line 4 waveform shaping circuit group 14 provided for _{# 1} to 4 _#N , control line 4 _{# 1} to 4 _#N compatible Group of three-state buffers 15 provided at the control side CP
A decoder 16 for selecting one of the three-state buffers in the three-state buffer group 15 in accordance with an address signal from U11, a memory 17, and the like are included.
The signals from the respective control lines 4 _{# 1} to 4 _#N are waveform-shaped by the waveform shaping circuit 14 and input to the three-state buffer 15, and are input from the three-state buffer 15 to the control side CPU 11 via the data bus. Is configured as follows.

The operation of this embodiment system will be described below with reference to FIGS. Here, FIG. 3 is a diagram showing a processing sequence at the time of transmission on the control station side, FIG. 4 is a processing sequence at the time of transmission on the dependent station side, FIG. 5 is a processing procedure on the control station side, and FIG. is there.

First, the case where the Kth dependent station 2 _#K transmits data will be described below with reference to the processing sequence of FIG.

When transmission data is generated, the dependent station 2 _#K asserts its own control line 4 _#K to turn it on. That is, when the subordinate side CPU 21 of the subordinate station 2 _#K detects that there is transmission data in its own station, the subordinate side CPU 21 sets the register 24 to the decoder 2
Address via 3 and set ON bit to it to turn control line 4 _#K ON.

In the control station 1, the control-side CPU 11 periodically sends the three-state buffer group 1 via the decoder 16.
One of the buffers 5 is sequentially addressed, whereby the control signals from the control lines 4 _{# 1} to 4 _#N are sequentially selected and input to the control side CPU 11 via the data bus. .. As a result, the control side CPU 11 causes each control line 4
_{# 1-4 #N} status can be monitored regularly. As a result of this monitoring, when it is detected that the control line 4 _#K is ON, the control side CPU 11 causes the serial communication controller 12
Is a subordinate station corresponding to control line 4 _#K 2 data communication line 3 to _#K
The switch circuit 13 is switched so that the line is connected to _#K . Thereafter, the control station 1 is connected in response to a dependent station 2 _#K (AC
K signal). With the above, line connection and link establishment are completed, and data can be transmitted and received.

When the line is connected, the dependent station 2 _#K sends a fixed length of data to the control station 1 through the data communication line 3 _#K . When the control station 1 receives this data, it returns a response signal (ACK signal) to the dependent station 2 _#K . This operation is repeated until there is no transmission data on the dependent station 2 _#K side. When data transmission is completed, the dependent station 2 _#K finally sends a line disconnection signal (EOT).
Signal) to the control station 1. When the control station 1 receives this line disconnection signal, it switches the switch circuit 13 to disconnect the data communication line 3 _#K . After that, the control station 1 again shifts to a mode for monitoring the control lines 4 _{# 1} to 4 _#N , and is ready to communicate with other dependent stations.

Next, the case where the control station 1 transmits data to the Kth dependent station 2 _# K will be described with reference to the processing sequence of FIG.

When data to be transmitted to the dependent station 2 _#K is generated in the control station 1, the control side CPU 11 causes the switch circuit 13 to operate.
To switch the serial communication controller 12 to the dependent station 2
Connected to the data communication line 3 _#K to _#K, the data communication line 3
_A line connection signal (ENQ signal) is sent to the dependent station 2 _#K via _#K . Upon receiving this line connection signal, the dependent station 2 _#K returns a connection response (ACK signal) to the control station 1. As a result, line connection and link establishment are completed, and data can be sent and received.

The data transmission / reception after the line connection is the same as in the case where the data is sent from the dependent station 2 side to the control station 1 side. After the data transmission is completed, the control station 1 finally sends a line disconnection signal (EOT signal) to the dependent station 2 _#K , and the switch circuit 1
_Switch 3 to disconnect data communication line 3 _#K . After that, the control station 1 again shifts to a mode for monitoring the control lines 4 _{# 1} to 4 _#N , and is ready to communicate with other dependent stations.
Subordinate station 2 _#K is again in a standby state.

Here, a processing procedure in the subordinate station 2 for executing the above processing sequence will be described below with reference to FIG.

The dependent station 2 monitors whether or not the line connection notice from the control station 1 is received via the data communication line 3 of its own station (step S21), and this line connection notice is received. Then, a connection response is sent to the data communication line 3 of its own station. Then, the data reception process from the control station 1 side is performed (steps S31 and S32). Finally, when the line disconnection notification is received (step S30), the process returns to the line connection notification and transmission data presence / absence monitoring mode (step S21).

Now, it is assumed that transmission data addressed to the control station 1 is generated on the subordinate station side. Then, the subordinate CPU 21 of the subordinate station turns on its own control line 4 (step S
23). In response to this, when a connection response is received from the control station 1 via the data communication line 3 of the own station (step S2
4), data transmission processing is performed via the data communication line 3 of the own station (steps S25 to S27). When there is no more data to be transmitted, a line disconnection notification is sent to the control station 1 via the data communication line 3, and the mode returns to the line connection notification and transmission data presence / absence monitoring mode (steps S21 and S22).

Various modifications are possible in implementing the present invention. For example, in the above-described embodiment, the control station monitors the state of the control line from each subordinate station 2 by scanning with software, but the present invention is not limited to this, and for example, the state of each control line. May be detected by the hardware circuit, and when it is detected that the control line is turned on by this hardware circuit, the control CPU may be notified by an interrupt.

[0024]

As described above, according to the present invention, in the notification between the processors connected in multipoint, the delay time from the occurrence of communication data to the transfer of the communication data to the other party is large. Can be shortened to Further, the processing load for polling in the control side processor and the processing load for monitoring polling reception in the subordinate side processor are reduced.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a multipoint CPU system using an interprocessor communication method as an embodiment of the present invention.

FIG. 3 is a diagram showing a processing sequence when transmitting from the control station side in the embodiment.

FIG. 4 is a diagram showing a processing sequence in the case of transmission from the dependent station side in the embodiment.

FIG. 5 is a flowchart showing a processing procedure in the control station of the embodiment.

FIG. 6 is a flowchart showing a processing procedure in a subordinate station of the embodiment.

FIG. 7 is a block diagram showing a conventional multipoint connection type CPU system.

FIG. 8 is a diagram showing a data transmission sequence according to a conventional method.

[Explanation of symbols]

1 control station 2 _{# 1 to} 2 _#N dependent station 3 _{# 1 to} 3 _#N data communication line 4 _{# 1} to 4 _#N control line 11 control side CPU 12, 22 serial communication controller 13 switch circuit 14 waveform shaping circuit group 15 Three-state buffer group 16,23 Decoder 17,26 Memory 24 Register 25 Buffer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Toshihiro Yabe Toshihiro Yabe 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor, Mitsuhiro Matsuda 3-9-18 Shin-Yokohama, Kohoku Ward, Yokohama City, Kanagawa Prefecture Fujitsu Communication・ Inside Systems Co., Ltd.

Claims (2)

[Claims] 1. An inter-processor communication control method in a multipoint connection system in which a plurality of subordinate side processors (# 1 to #N) are connected to a control side processor (# 0). Control lines (CL _{# 1 to} CL _#N ) are respectively provided between the slave processor and the plurality of subordinate processors, and the subordinate processor requests data transmission via its own control line when a data transmission request is generated by itself. To the control side processor, the control side processor monitors each control line, and when it detects a data transmission request of the subordinate side processor, the control side processor is line-connected to the subordinate side processor for communication. Communication control method between processors in a system. 2. A data communication line (TL _{# 1 to} T) is respectively provided between the control side processor and the plurality of subordinate side processors.
L _#N ) is provided, the control side processor is provided with a switching circuit (SW) for switching the line to each of the data communication lines, and when the control side processor detects a data transmission request from the control line, 2. The inter-processor communication control method in the multipoint connection system according to claim 1, wherein the switching circuit switches the line to the data communication line of the subordinate processor that has issued the data transmission request.