JPH03108837A - Time division bus control circuit - Google Patents

Abstract

PURPOSE:To apply parallel control to plural peripheral equipments without mutual effect by constituting both an incoming control bus and an outgoing bus with time division buses divided into individual areas for each peripheral equipment. CONSTITUTION:When a central controller 1 sends a valid code '1' of a control signal and a control data to an area of a peripheral equipment 41 connecting to an incoming control bus 21, a bus adaptor 61 of the peripheral equipment 41 confirms the valid code '1' of a control signal of its own area, fetches a control data and a processing section 51 applies processing. While the processing section 51 processes a control data, when the central controller 1 sends a valid code '1' of a control signal and a control data to an area of a peripheral equipment 42 connecting to an incoming control bus 21, a bus adaptor 62 of the peripheral equipment 42 confirms the valid code '1' of a control signal of its own area, fetches a control data and a processing section 52 applies processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to communication switching networks, information processing devices, etc., and particularly to a time-sharing bus control circuit for controlling a plurality of peripheral devices.

[Conventional technology]

Conventionally, this type of time-sharing bus control circuit uses an address bus between a central control unit and multiple peripheral devices.

It is connected by a control bus consisting of a data bus and a control signal bus, and a device number that distinguishes the peripheral device is given to each of the plurality of peripheral devices in advance, and each peripheral device has a bus corresponding section that identifies its own device number. It is arranged.

The central controller sends a device number signal on the address bus, a data signal on the data bus, and a control signal on the control signal bus. In the peripheral device, the bus corresponding part reads the device number signal sent to it, and if it is its own device number and the control signal indicates valid, it takes in the data signal sent at the same time from the central control device. Perform processing.

After processing the data signal, the peripheral device
The bus is switched in the opposite direction toward the central controller, and a response signal is sent back to the data bus, and when the central controller reads the response signal, it terminates control of one peripheral device and begins the next control procedure.

[Problem to be solved by the invention]

The conventional time division bus control circuit described above has an address bus,
Consisting of a data bus and a control signal, multiple peripheral devices receive the device number signal via the address bus, and only when the device number is their own and the control signal is valid.
It is structured so that it captures and processes the data signal sent via the data bus, and after the processing of the data signal is completed and a response signal is sent back to the central control signal, it proceeds to control other peripheral devices. , peripheral devices other than the peripheral device specified by the device number signal cannot be controlled until the control of the specified peripheral device is completed, and especially when controlling a peripheral device that takes a long time to process, other peripheral devices There was a problem in that the system had to wait a long time for control, which was inefficient.

An object of the present invention is to provide a time division bus control circuit that solves the above problems.

[Means to solve the problem]

The time-sharing bus control circuit according to the present invention is a time-sharing bus control circuit in which a central control unit controls a plurality of peripheral devices via a control bus, in which the control bus controls individual areas for each peripheral device using the time-sharing bus. It has an uplink control bus in the transmission direction from the central control unit and a downlink control bus in the reception direction from the central control unit to the central control unit. Each individual area has a valid code for validating the area.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block configuration diagram showing an embodiment of the present invention, in which a central control device 1 connects two peripheral devices 41, 42, and 43 with two uplink control buses 21 and a downlink control bus 22. connected by a control bus.

The peripheral devices 41, 42, and 43 each have a bus corresponding section 61, 62, . . . , which takes in control data and returns a response signal.
63, and processing units 51, 52.5 that process control data.
3.

FIG. 2 is a format diagram showing an example of the data format of the upstream control bus 21 and the downstream control bus 22 in FIG. The downlink control bus 22 is divided into three areas for each of the three peripheral devices, and the uplink control bus 21 has a 1-bit control signal and an N-bit (
N: an integer) control data, and a 1-bit control and N-bit (N: an integer) response signal on the downlink control bus 22. Each bus corresponding section is configured to take in only its own area from a time-sharing position. be.

The control operation will be explained below with reference to FIGS. 1 and 2.

Now, when the central controller 1 sends the valid code "1" of the control signal and control data to the peripheral device 41 area of the uplink control bus 21, the bus corresponding section 61 of the peripheral device 41 transmits the control signal of its own area. The processing unit 51 confirms the valid code “1” and takes in the control data, and the processing unit 51 performs the processing.
When the processing of the data signal is completed, the bus corresponding section 61 returns the valid code "1" of the control signal and a response signal to the peripheral device 41 area of the downlink control bus 22.

While the processing unit 51 is processing control data, when the central control unit 1 sends the valid code "1" of the control signal and the control data to the peripheral device 42 area of the uplink control bus 21, the peripheral device 4
The bus corresponding unit 62 of No. 2 confirms that the control signal of its own area is a valid code "1", and takes in the control data.
The processing unit 52 performs the processing.

Furthermore, when the central control unit 1 sends the effective code "1" of the control signal and the control data to all the peripheral device areas of the uplink control bus 21, each of the bus corresponding parts 61, 62, . 63 confirms that the control signal of each area is a valid code "1" and takes in the control data,
Processing is performed in each processing section 51, 52, and 53.

[Effects of the Invention] As explained above, the present invention connects the central control unit and the peripheral devices by an upstream control bus in the sending direction from the central controller and a downlink control bus in the receiving direction from the central controller. connection,
By configuring both the upstream control bus and downstream control bus as time-sharing buses that are divided into individual areas for each peripheral device,
Since a plurality of peripheral devices are controlled in parallel without affecting each other, unnecessary waiting time can be eliminated by controlling other peripheral devices, and an address bus can also be eliminated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the time division bus control circuit of the present invention, and FIG. 2 is a data format diagram showing an example of the control bus of FIG. 1... Central control device, 21... Upstream control bus, 22
... Downlink control bus, 41, 42.43 ... Peripheral device 1.51.52.53 ... Processing unit, 61, 62.63
...Bus support department.

Claims (1)

[Claims] In a time-sharing bus control circuit in which a central control unit controls multiple peripheral devices via a control bus, the control bus is configured as a time-sharing bus for each peripheral device. and a downstream control bus in the reception direction to the central control unit, and the central control unit and the peripheral devices provide the control bus with valid codes for validating data in the individual areas of each peripheral device. A time-division bus control circuit comprising: