JPH0344069A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase resistance to radiation by laminating a thin field oxide film and a thin gate oxide film formed by wet oxidation at a low temperature. CONSTITUTION:A thin field oxide film 26 of 4000-5000Angstrom in thickness is formed between well regions 24, 28, A thin gate oxide film 30 of 100-200Angstrom in thickness is formed by wet oxidation at a temperature lower than or equal to 850 deg.C. A thin oxide film 31 of 100-200Angstrom in thickness is stacked and formed on the gate oxide film 30 and the field oxide film 26 by LP-CVD method. By forming the field oxide film and the gate oxide film, and stacking the LP-CVD oxide film, excellent resistance to the influence of hole trap caused by total dose of radiation is realized. The same effect can be obtained by damaging the surfaces by plasma processing, instead of stacking the LP CVD oxide film.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a CMOS semiconductor device.

(Prior Art) A conventional method for manufacturing a CMOS semiconductor device will be described with reference to FIG.

First, as shown in FIG. 3(a), a P well region 2 is formed in a part of an N type silicon substrate 1 by a known method. next,
A P channel stop region 3 and a field oxide film 4 are formed by ion implantation and the well-known LOCO3 method in a portion of the substrate 1 that will become a field region, excluding the P well region 2 and the region where the P channel MOS transistor is to be formed.

The field oxide film 4 is formed to have a thickness of about 7,000 layers.

Next, after removing the 5iJn film used in the LOCO3 method and the pad oxide film underneath, the P-channel MO of the substrate 1 is removed.
S) N in the transistor formation area as shown in FIG. 3(b).
A well region 5 is formed. This N well region 5 is formed by sacrificial oxidation of the substrate once, and then by known photolithography, ion implantation, and annealing in an N2 atmosphere at about 1000 to 1200°C.

Next, after removing the sacrificial oxide film, P well region 2 and N
A gate oxide film 6 having a thickness of approximately 200 to 300 layers is formed on the exposed surface of the well region 5, as shown in FIG. 3(b).

After that, a third
As shown in figure (c), for the N well region 5, 31p
Perform channel control ion implantation 7 using +.

Thereafter, a polysilicon film 8 as a gate electrode is formed on the entire surface to a thickness of about 3,000 layers by LP-CVD (low pressure chemical vapor deposition), and 31p+ is thermally diffused. Furthermore, the polysilicon film 8 is patterned together with the gate oxide film 6 to leave it only in the gate region portion above the P well region 2 and the N well region 5, as shown in FIG. 3(c).

Next, by photolithography, ion implantation, and annealing treatment, the inside of the P well region 2 and the N well region 5 is formed (FIG. 3).
As shown in d), source and drain regions 9 and 10 of both N and P channel MOS transistors are sequentially formed.

As a result, the P well region 2 side has an N channel MOS)
transistor, P channel MOS on N well region 5 side
The L transistor is completed.

Next, apply NSC film (1000 to 2000 thickness) and BP on the entire surface.
By sequentially forming SG films (6,000 to 8,000 thick) and performing reflow, an intermediate insulating film 11 is formed over the entire surface as shown in FIG. 3(d).

Thereafter, a contact hole 12 is formed in this intermediate insulating film 11 by known photolithography and etching techniques, as shown in FIG. Metal wiring 13 is similarly formed using photolithography and etching techniques.

(Problems to be Solved by the Invention) However, in the structure obtained by the conventional manufacturing method as described above, when irradiation with radiation such as γ rays is performed, the gate oxide film 6 and the field oxide film 4 are Ionized holes caused by the transmitted radiation are trapped and generate positive charges, which may shift the threshold value negatively or adversely affect the channel current at the interface with the substrate 1, leading to deterioration of the transconductance g111. However, it does not have sufficient resistance to the generation of interface states, making it unsuitable for use in equipment related to space or radiation.

The present invention has been made in view of the above points, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can have a strong structure against various characteristic deteriorations caused by radiation irradiation.

(Means for Solving the Problems) The present invention provides a method for manufacturing a semiconductor device, particularly a CMOS semiconductor device, in which a field oxide film is formed thinly, and wet oxidation is performed at 850° C. or lower on a P-well region and an N-well region. After forming a thin gate oxide film, a thin oxide film is formed overlying the gate oxide film and the field oxide film by low pressure chemical vapor deposition.

Alternatively, a field oxide film and a gate oxide film are formed in the same manner as above, and their surfaces are damaged by plasma treatment. Furthermore, in this method of causing damage, a thin oxide film or a thin thermal oxide film is formed over the damaged field oxide film and gate oxide film by low pressure chemical vapor deposition. Further, the semiconductor substrate has an epitaxial layer on the substrate portion, and this epitaxial layer is formed as thin as the depth of each well region formed in this epitaxial layer.

(Function) A thin field oxide film and a thin gate oxide film formed by wet oxidation at 850° C. or lower have a low hole trap density and high resistance to radiation. Moreover, if an oxide film made by low pressure chemical vapor deposition (LPGVD oxide film) with a high hole trap density is layered on top of these, the holes generated in the gate oxide film and field oxide film due to radiation irradiation will be removed from the substrate. It is not trapped at the interface with (
If trapped here, the device characteristics will deteriorate), and trapped at the interface with the LP-CVD oxide film on the upper surface. Therefore, by forming the field oxide film and gate oxide film as described above, and layering the LP-CVD oxide film,
It has strong resistance to the effect of hole traps caused by the total dose of radiation.

On the other hand, L is formed on the field oxide film and the gate oxide film.
Instead of stacking P-CVD oxide films, even if their surfaces are damaged by plasma treatment, L P-C
The same effect as when VD oxide films are stacked can be obtained. In other words, the field oxide film and gate oxide film (SiO□
If the surface of the film (film) is damaged by plasma treatment, some of the bonding means of Si in the SiO□ on the surface will be left open (
For example, 0=Si=0 -5i=0), and this free bond actively traps holes. Therefore, strong resistance to radiation can also be obtained in this case.

Note that if the surfaces of the field oxide film and gate oxide film are damaged by plasma treatment, a thermal oxide film or LP-CV film is placed over them to ensure the gate breakdown voltage.
D Overlap the oxide film. When stacking LPGVD oxide films,
With the addition of the hole trap effect caused by the L P-CVD oxide film, better results in terms of radiation resistance can be obtained.

Note that it is better for the oxide film as a whole to have a low hole trap density, so LP-C, which has a high hole trap density,
The VD oxide film is formed thin.

In addition, in this invention, since the epitaxial layer of the semiconductor substrate is thin and has a structure that is approximately equal to the depth of each well region formed therein, holes and electrons generated in the semiconductor substrate by heavy particles etc., even in the presence of radiation, are A good effect can also be expected on the latch-up phenomenon.

Also, if the field oxide film is thinner, there will be fewer steps.
Further, since the level difference is smoothed by the overlying L P-CVD oxide film or thermal oxide film, the covering condition of the upper layer film is improved.

(Example) Examples of the present invention will be described below with reference to the drawings. First, a first embodiment of the present invention will be described with reference to FIG.

In FIG. 1(a), 21 is a semiconductor substrate.

This semiconductor substrate 21 contains N-type impurities of 1016 to 101
Similarly, N-type impurities are added at a concentration of 10'' to 101015ato/cJ on the substrate portion 22 containing a concentration of 018ato/cr&.
The N-epitaxial layer 23 containing a concentration of about 4 to 6μ
It is formed by growing it to a thickness of m. This semiconductor substrate 21
A P well region 24 is formed in a part of the epitaxial layer 23 at the same depth as the thickness of the epitaxial layer 23 by a known method. Next, a P+ channel stop region 25 and a field oxide film 26 are formed by ion implantation and the well-known LOCOS method in the portion of the epitaxial layer 23 that will become the field region, excluding the P well region 24 and the P channel MOS transistor formation region. Intimidate. The field oxide film 26 is formed to a thickness of approximately 70,000 mm.

Next, after removing the Si:uL film used in the LOCO3 method, the field oxide film 26 is etched into four layers using known wet etching or etch-back.
Etch it so that it is as thin as 0.000 to 5000. At this time, Figure 1 (a) used in the LOCO3 method
The pad oxide film 27 shown in FIG. 2 is removed at the same time.

Next, as shown in FIG. 1(b), an N-well region 28 is formed in the P-channel MOS transistor forming region of the epitaxial layer 23. This N well region 28 is formed by sacrificial oxidation of the substrate, and then by known photolithography, ion implantation, and annealing in an N2 atmosphere at about 1000 to 1200°C. Further, this N-well region 28 is formed to have the same depth as the thickness of the epitaxial layer 23. Thereafter, channel control ion implantation 29 is performed on this N well region 28 by known photolithography and ion implantation. After that, the sacrificial oxide film is removed. The state after removing this sacrificial oxide film is depicted in FIGS.

Next, the exposed surfaces of the P-well region 24 and the N-well region 28 are oxidized at 850° C. or less (see FIG. 1).
As shown in c), the gate oxide film 30 is formed to a thickness of about 100 to 2
000 or so. Furthermore, the gate oxide film 30
Then, an oxide film 31 is formed to a thickness of 100 to 200 layers on the field oxide film 26 by the LP-CVD method. Further, a polysilicon film 3 as a gate electrode is formed on the oxide film 31.
2 is shaped to a thickness of about 3,000 by LP-CVD, and 31p+ is thermally diffused into this.

This polysilicon film 32 is then patterned by known photolithography and etching, leaving gate electrodes only on the gate regions of each well region 24, 28, as shown in FIG. 1(d).

After that, photolithography, ion implantation, and annealing are performed to form the source
Drain regions 33 and 34 are formed in the P well region 24 and the N well region 28, as shown in FIG. 11(d). As a result, an N-channel MOS transistor is placed on the P-well region 24 side, and an N-channel MOS transistor is placed on the P-well region 24 side.
A P-channel MOSI transistor is completed on the 8 side. Note that the source/drain region 33 of the N-channel MOS transistor has a DDD structure (Double Doped Drain structure) using double diffusion. The source/drain regions 33 and 34 can also be formed in an LDD structure (Lightly Looped Drain structure).

Next, apply a NSC film (1000 to 2000 thick) on the entire surface and B.
By forming a PSG film (6000 to 8000 Å thick) and performing reflow, an intermediate insulating film 35 is formed over the entire surface as shown in FIG. 1(e).

Thereafter, a contact hole 3.6 is formed in the intermediate insulating film 35, the oxide film 31, and the gate oxide film 30 using known photolithography and etching techniques, as shown in FIG. Metal wiring 37 connected to source/drain regions 33 and 34 is similarly formed using photolithography and etching techniques.

In the first embodiment described above, the epitaxial layer 23 of the semiconductor substrate 21 is as thin as 4 to 6 μm, and has a structure equal to the depth of each well region 24 and 28 formed therein. Also,
The field oxide film 26 is also as thin as 4,000 to 5,000 A, and the gate oxide film 30 is also made as thin as 100 to 200 A by using wet oxidation at 850° C. or lower. Then, a thin oxide film 31 of 100 to 200 layers formed by the LP-CVD method is overlapped on the gate oxide film 30 and the field oxide film 26.

FIG. 2 shows a second embodiment of the invention. In this second embodiment, the field oxide film and gate oxide film are formed in the same manner as in the first embodiment, and their surfaces are damaged by plasma treatment.

In this second embodiment, as shown in FIGS. 2(a) and 2(b), the same steps as in the first embodiment are performed up to the step of removing the sacrificial oxide film after the channel control ion implantation 29. However, in this second embodiment, LOGOS
Through the process, the field oxide film 26 is made thin with a thickness of approximately 50,000 mm. Therefore, the process of partially etching the field oxide film 26 after the LOGO3 process is omitted. Therefore, before the step of forming the N well region 28, ra
When the S i 3tJ a film used in the cos process is removed, the pad oxide film underneath is also removed.

After the sacrificial oxide film is removed by performing the same process as described above, next, as shown in FIG. The gate oxide film 30 is reduced by 500 to 1
000 people thick.

Next, this gate oxide film 30 is thinned to 100 to 200 Å by dry etching as shown in FIG. 2(d). At this time, a portion of the field oxide film 26 is also etched by this dry etching. Furthermore, this dry etching causes damage to the surfaces of field oxide film 26 and gate oxide film 30.

In this example, the di-oxide film 30 is thinned by dry etching, and the surfaces of the gate oxide film 30 and the field oxide film 26 are damaged at the same time.
The gate oxide film 30 may be formed as thin as 100 to 200 degrees by wet oxidation at temperatures below .degree. C., and only the surfaces of the gate oxide film 30 and the field oxide film 26 may be damaged by plasma.

Next, an oxide film 38 is formed on the damaged gate oxide film 30 and field oxide film 26, as shown in FIG. 2(d). Here, the oxide film 38 can be formed by forming a thermal oxide film of 100 to 200 layers using the same method as the gate oxide film 30, or by forming an oxide film of 100 to 200 layers using the LP-CVD method.
Form people. The total thickness of this oxide film 38 and gate oxide film 30 is determined depending on the device as required.

After forming the oxide film 38 in this way, the process from the step of forming the polysilicon film 32 as a gate electrode is similar to that of the first embodiment, as shown in FIGS. 2(e) to 2(b). to complete the device. Explanation of this part will be omitted. Note that the gate electrode can also be formed of a polycide film.

(Effects of the Invention) As described in detail above, according to the manufacturing method of the present invention, the field oxide film is formed thinly, and the gate oxide film is further formed thinly by wet oxidation at 850° C. or lower. By overlaying an oxide film using the LP-CVD method or by damaging the surface with plasma, it is possible to obtain strong resistance to the effects of hole traps caused by the total dose of radiation.Also,
In the method of damaging the surfaces of the field oxide film and gate oxide film, if an oxide film of the L P-CVD method is formed as an oxide film on top of them to ensure gate breakdown voltage, it will be more resistant to the effects of hole traps. You can get a lot of resistance.

In addition, in this invention, the epitaxial layer is thin and has a structure approximately equal to the depth of each well region formed thereon on the semiconductor substrate. Good results can also be obtained for the Lattsier-Knob phenomenon caused by holes and electrons.

In addition, if the field oxide film is made thinner as mentioned above, the step difference will be smaller (and if the field oxide film and the gate oxide film, that is, the entire surface are covered with an oxide film such as L P-CVD method), the step difference will become more gentle. Therefore, the coating state of the upper layer film can be improved.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing a first embodiment of the method for manufacturing a semiconductor device of the present invention, FIG. 2 is a process sectional view showing a second embodiment of the invention, and FIG. 3 is a conventional manufacturing method. FIG. 21... Semiconductor substrate, 22... Substrate part, 23...
Epitaxial layer, 24...P well region, 26...
・Field oxide film, 28...N well region, 30・
...Gate oxide film, 31...LP-CVD oxide film, 32...Polysilicon film, 33.34...=Source/drain region, 38...Oxide film. 3 figures with conventional 1st floor

Claims (3)

[Claims] (1) (a) A step of preparing a semiconductor substrate having an epitaxial layer on the substrate portion, and (b) forming a P-well region, an N-well region, and a field oxide film in the epitaxial layer of the semiconductor substrate, in particular, forming a field oxide film. (c) Then, forming a thin gate oxide film on the surface of each well region by wet oxidation at 850° C. or lower; (d) After that, forming a thin gate oxide film on the gate oxide film and the field oxide film; (e) forming a gate electrode on the oxide film in the gate region of each well region; (f) further forming a P channel in each well region; MOS transistor, N channel MOS transistor source
A method for manufacturing a semiconductor device, comprising the step of forming a drain region. (2) (a) preparing a semiconductor substrate having an epitaxial layer on the substrate; (b) forming a P-well region, an N-well region, and a field oxide film in the epitaxial layer of the semiconductor substrate, particularly field oxidation. (c) After that, a thin gate oxide film is formed on the surface of each well region by wet oxidation and plasma treatment at 850° C. or lower, and the field oxide film is formed on the surface of the gate oxide film. (d) Thereafter, forming a thin thermal oxide film or a thin oxide film by low pressure chemical vapor deposition on the gate oxide film and the field oxide film; (e) Step (f) of forming a gate electrode in the gate region of each well region on a thermal oxide film or an oxide film formed by low pressure chemical vapor deposition;・
A method of manufacturing a semiconductor device, comprising the step of forming a drain region. (3) The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the epitaxial layer of the semiconductor substrate is as thin as the depth of a well region formed in the epitaxial layer.