TW525266B - A dual gate oxide process with reduced thermal distribution of thin-gate channel implant profiles due to thick-gate oxide - Google Patents

Abstract

A new method is provided for the creation of layers of gate oxide of different thickness. A substrate is provided, the surface of the substrate is divided into a first surface region over which a thick layer of gate oxide has to be created and a second surface region over which a thin layer of gate oxide is to be created. Thick gate-oxide implants are performed into the surface of the substrate. A thick layer of gate oxide is created over the surface of the substrate, the thick layer of gate oxide is successively patterned for thin gate-oxide implants, comprising thin gate-oxide n-well/p-well, threshold, punchthrough, implants, into the second surface region of the substrate. The thick layer of gate oxide is removed from the second surface region of the substrate. The (now contaminated) top layer of the thick layer of gate oxide is removed, a thin layer of gate oxide is grown over the second surface region of the substrate.

Description

525266 V. Description of the invention α) [Background of the invention] (1) Field of the invention The present invention relates to the manufacturing of integrated circuit elements, and relates to a method for improving channel ion implantation in a double gate oxide layer process. (2) Description of the know-how. The manufacturing of complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) is well known in the technology of manufacturing semiconductor components. By means of P-channel (pM0s) and ^ channel (NMOS) Two types of components are manufactured on the surface of the silicon substrate at the same time. The simultaneous manufacturing of PMOS and NMOS components provides significant advantages in reducing manufacturing costs, as well as reducing the total heat to be manufactured due to its dual operation. Wide; Lack: Can be used as =: Application 'It will operate low current, high performance components due to i high structure: the most effective application of components' The popularity of FET components is due to structure, low power consumption, and high yield There is no small one. CMOS 7L parts are usually manufactured by defining the main part of the substrate, and the components to be fabricated on the substrate are made of the substrate two gasification isolation layer in the second region of the substrate: the FOX or shallow trench isolation (STI) region. 'By doping the substrate with a -P-type impurity, various p-type well regions have been formed in the surface of the -layer substrate,-or -indium, to cover the surface Y of the -single-crystal semiconductor substrate. The layer is a short channel effect caused by the characteristic size of the closed oxide system. It reduces the superoxide oxide layer and uses lithography imaging to reduce the heart: the second system is deposited on the _ Xi said Layer, then

Page 6 (LDD) and implanted source and drain regions. I >: sub-implanted lightly doped 525266

Non-isotropic polycrystalline stone worms on the polar oxide layer can easily become a problem in plate making. An example of a thin gate oxide layer of anisotropic polycrystalline silicon. The etching of polycrystalline silicon gates usually stops in the gate. The gate-to-gate gaps between the gates of the base implanted substrate are filled with impurities for the majority of the gate implants. However, the current “such as thin gate oxidation energy” is used. Need to enter the production gap wall (electrically on the side wall, * isolation gate electrode) is formed to cover the gate into the gate n IU straw from the heating substrate to a temperature of 700 and 900 forces before closing the gap wall On the surface, the LDD may lead to further-surface damage. Etching back :::: Repairs all areas of any ion gap wall material, except for the side wall of the pole electrode on the interrogation structure. This non-respective application of non-isotropic dry-wall material is performed, leaving only the dichroic dry-back The etch removes most of the copper-separated dense ground, and the force is two. The V 'gap wall is in the appropriate place (its 2 5 is the electrode, /, is attached to the side wall of the inter-electrode. OK, it is used Follow-up: Second plant: f is made of an impurity that does not provide a higher doping concentration = in: sample θ phase w is made of implants with this impurity compared to the second set of implants. Impurities in deeper areas. ::: Oxidation layer: manufacturing, including 'doing many layer areas and [sub-implantation and vt implantation, • before forming :: bi-interlayer. For best results The elementary ion ion m or eight smaller channel lengths considered for the high penetration: cloth 'However, (furnace tube base) thick gate oxidation generation = pre #: will be for thin gate oxidation Effect of channel ion implantation in the region. The present invention proposes this consideration by providing a

525266 V. Description of the invention (3) Low-impact method of P-bold 'The impact is a channel under the thin gate oxide layer. The thin gate oxide has been treated on the implant distribution. National Patent No. 6,171,9 (UBlmYu) shows a double interlayer process, and there are P-type and N-type well areas. U.S. Patent No. 6,033,943 (Gardner) discloses a gate oxide process using a mask step. U.S. Patent No. 5,989,949 (Vines), U.S. Patent No. = 4,674Bl (TUng), and U.S. Patent No. 6,268,250 (bi) all relate to gate oxide and well area processes. [Objective of the invention] One of the main objectives of the invention is to provide a double-gate oxide, which can reduce the impact of the gate oxide oxidation treatment on the channel ion implantation knife cloth under the thin interpolar region. F1: According to the above-mentioned purpose of f & Ming 'provide-a kind of manufacture of different thicknesses of taxis 2 Do not: Zhixinfang' to provide a substrate, the surface of the substrate-surface area (on which a thick layer is manufactured Intermetallic oxide), and a thin layer of gate oxide). Field isolation is provided on the surface of the substrate, including N-well or P-well, threshold, acoustic = sub-plant) 2 thick open-pole oxide ion implantation A 'system, closed-end oxidation implanted into the substrate rUf The system manufactures a thick layer of gate gaseous material on the surface of the substrate, which is implanted with patterned gaseous ions in iridium (for the first-thin gate oxygen-curtain). The N-well area, the threshold, and the penetrating M-station system include a gate electrode sclerosis (thoron implantation) into the second surface area of the substrate. 525266 V. Description of the invention (4) The first thin gate oxide ion implantation is performed, and a second photoresist mask is used instead of the first photoresist mask for ion implantation of the second thin gate oxide layer (system It includes a thin gate oxide P well region, a threshold, and a penetrating ion implantation) into the second surface region of the substrate. A second thin gate ion implantation is performed, and a third photoresist mask is used instead of the second photoresist mask to remove the thick gate oxide of the second surface area of the substrate and the second surface area of the substrate And removing the third photoresist mask to expose the thick gate oxide covering the first surface area of the substrate. The (now contaminated) top layer of the thick gate oxide is removed, and a thin layer of gate oxide is grown overlying the second surface area of the substrate. [Comparison of drawing number] 10 A single crystal silicon substrate 11 Surface area 12 Gate oxide 13 Surface area 14 Shallow trench isolation (STI) area 15 Opening 16 N-well or P-well 18 First photoresist mask 17 Opening 20 Thin gate N well area 22 Second photoresist mask 24 Thin gate oxide P well area

525266

26 The third photoresist mask 28 New layer [Description of the preferred embodiment] The performance of the CMOS device is inversely proportional to the thickness. Therefore, the high-performance device in the region of the gate oxide layer under the gate electrode of the device The thickness of the inter-electrode oxide layer, the inter-electrode dielectric value of 100 Angstroms or less will be more common and more advanced. Advanced components) Manufacturing has a thickness of 20 A. The advantages of 4 well-known applications are to reduce power. ί Complementary Metal Oxide Semiconductor (CM0S) device access / 1, Congbian, Gu4, 'It can be obtained from these components, this

Reduction of power consumption is achieved by CM0S 缂 钫 缂 钫 Where all the devices use N-channel and P-channel CMOS devices, two days-μ, from, 7 4 inches, only one of the two transistors is set in time, and due to the high resistance of the element There are several reasons why there is no current flow in defending Tai A's daily income. The present invention will be described in detail using the 1st m ζ ^ 4 person w ☆-brother figure to brother figure 7. Dou Cun Bie Cha is shown in the first cross section of the same _1Q, a 1 %% A & 1, which shows: 1 a cross section of an early and early silicon substrate, double gate oxide layer; /, τ ™ Design strategy -11, the surface area of substrate 10, complex ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, and ^ ^ ^. The surface area of 10, i selects a seedling a, and /, Yuan selects to make a thin layer of gate oxide compound; the surface area on it; -1 2, a layer of gate oxide, potted system ^ /, 1 is shown in the surface area 1 1 and 1 3, the gate oxide layer 12 is a phase report, and this question is asked ^ ^ sn on, the gate oxide of the α phase field layer , Which has a thickness between 80 and 120 angstroms;

525266 V. Description of the invention (6) -14 'Shallow trench isolation (STI) region, which is manufactured on the substrate 10 to electrically isolate adjacent gate electrodes from each other; you-16, -N well region or P well Area, which is carried on the substrate 10 and is covered with a thick layer of gate oxide; Below, the ion implantation in the N-well region or the ρ-well region mentioned here does not need to distinguish these two types of ion implantation, which reflects that the surface covered with a relatively thick gate oxide can be manufactured to cover a P-well region) and PM 0s (coverage-N well area) two. The present invention also does not mean that these two forms of ion implantation need to be performed in a different way than the NMos / pM0s hetero-implantation step covering a relatively thick layer of gate oxide. Prior to the fabrication of the thick gate oxide layer 12, conventional ion implantation (such as threshold voltage ion implantation) has been performed in the surface area u of the substrate, this = is the surface covering manufacturing of the substrate-thick layer Gate oxide layer, these ion implantations are not further emphasized in the cross-sectional view shown in FIG. 1. At this time, the parallel f ion implantation is performed on the surface 13 of the substrate, which is to cover the surface area to produce a gate oxide layer. Suppose that in order to specifically explain one of these ion implants, it covers the problem that the CMOS elements with ... U-meter element characteristics are subject to source-to-drain region penetration, especially in MOSFETs with short channel sizes. Device, the short channel can reduce the isolation characteristics of the element. The source / drain penetration problem is usually determined by implanting a penetration stopper before the gate electrode of the CMOS element is formed in the meta substrate. The implantation is performed before the interrogation electrode is formed. "% Lice deposited gate oxide layer 12 can then be subjected to any layer of gate oxide formation. Page 11 525266 5. Description of the invention (7) Conventional methods of materials such as thermal oxidation treatment of silicon at the bottom (in an oxidizing steam environment, The layer 12 may also be formed at a temperature between 8500 and 10,000.00 in a combination of a deposited silicon dioxide layer, a mixed oxide or nitride layer, or any suitable dielectric for a gate dielectric layer. Materials. The gate oxide can be grown at a temperature between 800 and 1,000 to reach a thickness between 80 and 120 angstroms. 'STI region 14 can be manufactured using a variety of methods Come out, one-, one " into the heart y, u — path

The method is a buried trench (BOX) isolation of shallow trenches. This method includes filling trenches with chemical vapor deposition (CVD) silicon oxide (SiO2), etchback after mechanical failure or mechanical / chemical polishing. To make a flat surface. The shallow trench isolation system used for the cashback BOX process is a non-isotropic plasma etched to the Shixi substrate, which usually reaches a depth between 2,000 and 5,000 angstroms, and forms a surround active The active element can be manufactured in or on the surface of the substrate. In a p jWtCM () S ^ type semiconductor device, the NGMS device is formed to cover one well / σ, while the PMOS device system is formed to cover an N well area. The single well area, the mouth structure system, and the Too high impurity concentration will result in lower element speed f :::: For high-speed operating elements, it is necessary to manufacture components with the structure of the beautiful Θ; ^, ,, °, so that P well area and N well area Germline formed

"M = seed well area has a low impurity f concentration. In this case, n and p wells ° σ, ^ / Chen must perform the component performance most effectively. Well-known C-face M well area and: Well area in this technique The system is based on the p-well area of the hard substrate ^: f and NMOb 7L pieces in the N-well area of the substrate, and the P-well area is formed in the active device area in the silicon UMOS component.

Page 12 525266----V. Description of the invention (8) The plutonium is formed by ion implantation of a p-type meal doped region 1 well region formed in the active element region (β1) or indium) in p Well :: Miscellaneous "ηΑ or Phosphine Well Area *, 'feather line borrowed, ion implantation-N is used to form the implantation mask, in order to prevent ^ # 影像 技术 系 入 和 在] ^ 洗 在Ρ 形 旅 难 士 古 # # # μ / in the Ν well area is implanted with N-type doping, but H λ # ρ 払 払 希, heterogeneous distribution to activate doping = plate annealing to obtain The region is deep at = doped ion implantation loss ^ Ca 5 to uE17 atGms / me ^ 'and is doped to —a ,, — in the cross section H shown in FIG. 2, an important element. 13; The first screen that has been made is to manufacture the surface covering the thin interlayer oxide layer area, and it is absolutely impossible to open the opening 15 in the photomask of the first photomask. It is a thin gate N well area that must be made and penetrated ^^ 1 〇 / soil implantation place; 1 ^ tooth penetration and power limit ~ 2 Q, .¾ BB 13 table: Zhong Biao well area ' It is formed in the thin gate oxide region of the substrate at 1 ° surface Threshold voltage implants performed in the United States Table φ t ^ shoulder oxide region 13. 4 Ding on the substrate 10 Table Conventional lithography and masking methods for grass blocking, *

'Η2〇2 ^ νηοη; " Opening 15 in 1 ^ 7J layer 18, 俜 Wu :,', formula π division, manufactured in this method in a photoresist system to perform the above mentioned :; The surface of the interlayer oxide layer 12 is implanted with the structure shown in the figure ... ^ The first photoresist mask 18 on the surface of the pre-emulsification layer 12 is removed from the factory, so that

525266 V. Description of the invention (9) The general ash plasma deashing method is followed by a complete surface treatment. Ί: fThe second photoresist mask 22 (Fig. 3) covers the surface of the "intermediate electrode oxide layer 22." In the above, the opening 17 is manufactured in the photoresistance opening Η and the surface area of the substrate 10 is aligned in a straight line. This area, the penetration and the threshold voltage jm are entered. P _ Let Ψ on the surface of the well: 2 Send = Department: gate. The well area is emphasized, and after medium = second impurity, the surface of the thick oxide layer 12 is removed from the screen (Figure 1), and the third photoresist mask 26 is replaced ( (Picture), the cross-sectional view of Figure 4 shows how to make a third 26 'third photoresist mask 26 covering the surface of the thick gate oxide ", to expose the thin gate oxide region 13. Conventional The method of manufacturing the photoresist mask is applicable to the manufacture of the third photoresist mask 26. Figure 5 shows how the present invention performs the removal of the photoresist mask 26: the layer electrode 2 should be used to remove the substrate The thick oxide layer on the surface is widely oxidized. It is necessary to manufacture a gate oxide layer, and the third photoresist mask 2 on the surface of the thick gate oxide stay layer 12 is removed. After 6th, the etching layer 12 not shown in the cross-section of FIG. 2 is coated with dilute hydrofluoric acid (DHF) (diluted with about 100: 〇), and the conventional photoresist removal method is performed again. At this time, Briefly recall the various implanted well areas in the substrate surface 10, as shown in Figure 5, as follows: 1 · Area 16 is a thick gate oxide N well area or p well area 2 · Area 2 4. It is a thin gate oxide p-well area;

525266 V. Description of the Invention (ίο) 3. Area 20 is a thin gate oxide N well area. The cross-sectional view shown in FIG. 6 shows a cross-sectional view, in which only the removal of the third photoresist mask 2 6 is emphasized. In addition, the cross-sectional view in FIG. 6 also emphasizes the process steps, so that it is used at 1 0 0 · Dilution of hydrofluoric acid (DHF) between 1 and 2000: 1 to remove contaminated top surface of thick gate oxide retention layer 12. The thickness of layer 12 was reduced from an initial value between 80 and 120 Angstroms to a value between 40 and 70 Angstroms to make a new layer 28 of gate oxide, which is still a comparable Thick gate oxide. After completing the reduction of the thickness of the layer 12, a thin gate RCA pre-cleaning is performed on the surface of the structure, which is shown in the cross-sectional view of Figure 6, and then the structure is ready to make a thin layer The gate oxide covers the surface area 13 of the substrate 10. The preferred embodiment of the present invention for manufacturing a thin oxide layer 30 is a rapid oxidation process, which uses a separate process chamber, thereby reducing the thermal budget of this process step. The second gate dielectric layer is fabricated to a second thickness between 10 and 50 angstroms. From the detailed description above, it is clear that the present invention has provided a method for manufacturing two layers of gate oxides with different thicknesses, and the present invention does not inhibit or damage the threshold and similar impurities from being implanted on the substrate surface. . The present invention manufactures a thermally redistributable double-gate oxide layer with reduced gate implantation caused by thick gate oxidation, which will be summarized as follows: • The present invention begins with a substrate and covers the surface of the substrate. A first surface area (on which a thick gate dielectric layer is fabricated) and a second surface area (on which a thin gate dielectric layer is fabricated) are designed. The required impurity ions have been implanted. Surface isolation region

525266 V. Description of the invention (11) is provided in the surface of the substrate; a first layer door with a thickness of one brother is on the surface of the substrate; The first exposure mask includes a surface layer to the electric layer. The second exposure mask is used to implant at least—the axis covers the substrate and implants the second impurity ion. The first exposure mask is used as the cover. -The first layer of the closed dielectric layer is planted on the surface. The first exposure mask system is made of a cover film; the second exposure mask system includes the following; "on the surface of the first layer of the layer, The upper system is manufactured with at least the second table covering the substrate. The second impurity ion is performed on the NMOS element; the mask is used, and the system is used as the second exposure mask as the -planting · removing gate electrode The first layer of the electrical layer—the second one is a second exposure mask made by the gate; the second layer of the gate dielectric layer; ::: on the surface of the first layer of the dielectric layer, the second layer of the substrate is removed. On the second surface of the substrate; 幕 ~ f screen is used as the -etching mask H1: the first layer of the electrical layer, which is removed using The first dielectric layer of the first circuit exits the first surface of the substrate; the gate dielectric exhibition of the first layer: the third military curtain on the t-plane; the measured quantity; and the electrical layer, which is manufactured to cover the substrate. The thickness of the second thick sound is reduced by the second and second layers of the gate electrode on the second surface of the plate. Although the present invention has been described with reference to its preferred embodiment, it is particularly shown and said. Page 16 525266

Page 17 525266 Brief description of the drawing. Figure 1 is a cross-sectional view of a substrate. The field isolation region has been formed on the surface of the substrate. The substrate is divided into a first surface on which a thick gate oxide is fabricated. Area, and a second surface area having a thin layer of gate oxide fabricated thereon, thick gate oxide ion implantation has been performed on the surface of the substrate, and a thick layer of gate oxide is fabricated to cover the surface of the substrate . Figure 2 is a cross-sectional view illustrating the patterning of the surface of a thick gate oxide to implant a first thin gate oxide ion onto the surface of a substrate. Fig. 3 shows a cross-sectional view illustrating the patterning of the surface of the thick gate oxide to implant the second thin gate oxide into the surface of the substrate. Figure 4 shows a cross-sectional view illustrating that after the surface of the patterned thick gate oxide is removed from the substrate surface, a thin layer of gate oxide is manufactured on the surface of the substrate. Fig. 5 is a cross-sectional view illustrating that after the thick gate oxide is removed from the surface of the substrate, a thin layer of gate oxide is manufactured on the surface of the substrate. Figure 6 shows a cross-sectional view after removing the photoresist mask and removing the top surface of the thick gate oxide. Fig. 7 is a cross-sectional view illustrating the fabrication of a thin gate oxide covering the second surface region of the substrate.

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Claims (1)

525266 VI. Scope of patent application1. A method for manufacturing a double-gate oxide layer with reduced heat redistribution double-gate oxide layer implanted by a thin gate channel caused by thick gate oxidation, comprising: providing a The substrate is covered on the surface of the substrate. The substrate has a first surface area designed thereon, and a thick gate dielectric layer and a second surface area need to be manufactured thereon. A polar dielectric layer is implanted into a first surface region of a substrate, and a field isolation region is provided in the surface of the substrate. A first-layer gate dielectric layer is fabricated with a first Covering the surface of the substrate with a thickness: manufacturing a first exposure mask covering the surface of the gate dielectric layer of the first layer, the first exposure mask including at least one opening covering the second surface of the substrate Overlying and manufacturing at least one PMOS element; performing the first impurity ion implantation using the first exposure mask as an ion implantation mask; removing the surface of the gate dielectric layer of the first layer First exposure mask A second exposure mask is manufactured to cover the surface of the gate dielectric layer of the first layer. The second exposure mask includes at least one opening to cover the second surface of the substrate, and the at least one NMOS device; performing a second ion implantation using the second exposure mask as an ion implantation mask; removing the second exposure mask on the surface of the gate dielectric layer of the first layer Page 19, 525266 VI. Patent application scope Manufacturing a third exposure mask covering the surface of the gate dielectric layer of the first layer, the third exposure mask exposing the surface of the gate dielectric layer of the first layer , The gate dielectric layer on the first layer covers the second surface of the substrate; the gate dielectric layer of the first layer on the second surface of the substrate is removed, and the third mask is used as An etching mask to expose the second surface of the substrate; Removing the third mask on the surface of the gate dielectric layer of the first layer; reducing the thickness of the gate dielectric layer of the first layer to a measurable amount; and manufacturing a gate dielectric layer of the second layer , Has a second thickness covering the second surface of the substrate. 2. The method according to item 1 of the scope of patent application, wherein the first exposure mask and the third exposure mask include a photoresist. 3. The method according to item 1 of the scope of patent application, wherein the gate dielectric layer of the first layer includes an oxide. 4. The method according to item 1 of the scope of patent application, wherein the gate dielectric layer of the first layer is manufactured to a first thickness between 80 and 120 angstroms. degree. 5. The method according to item 1 of the scope of patent application, wherein the desired ion implantation patterned to the first surface region of the substrate is selected from the group consisting of ion implantation in the N-well region and ion implantation in the P-well region. Groups of implanted and penetrating ion implantation and threshold voltage ion implantation. 6 · The method described in item 1 of the scope of patent application, wherein Page 20 525266 6. Scope of patent application The field isolation region in the substrate surface includes a shallow trench isolation region. 7. The method according to item 1 of the scope of patent application, wherein the first impurity ion implantation is selected from the group consisting of N-well area ion implantation, penetrating ion implantation, and threshold voltage ion implantation. . 8. The method according to item 1 of the scope of patent application, wherein the second impurity ion implantation is selected from the group consisting of P-well area ion implantation, penetrating ion implantation, and threshold voltage ion implantation. 9. The method according to item 8 of the scope of patent application, wherein the threshold voltage ion implantation uses indium as an impurity ion. 10. The method according to item 1 of the scope of patent application, wherein removing the first gate dielectric layer of the second surface of the substrate comprises using HF chemistry, whereby the HF is 1 0 0: 1 dilution. 11. The method according to item 1 of the scope of patent application, wherein the reduction of the thickness of the gate dielectric layer of the first layer is a measurable amount, which includes the use of HF chemistry, whereby the HF system is 1 0 0: 1 and 2 0 0: 1 ratio dilution 0 1 2 · The method described in item 1 of the patent application range, wherein the reduction of the thickness of the gate dielectric layer of the first layer is a measurable amount, which includes a reduction The first thickness is a thickness between 40 and 70 Angstroms. 13. The method according to item 1 of the scope of patent application, wherein a second layer of the gate dielectric layer is manufactured to cover the second surface of the substrate, and includes rapid heating and oxidation of the second surface of the substrate. Processing uses a single process room. 14. The method described in item 1 of the scope of patent application, which also includes Page 21 525266 6. Scope of patent application An additional step for pre-cleaning of thin gate RCA. This additional step is performed before manufacturing a second gate dielectric layer to cover the second surface of the substrate. 15. The method as described in item 1 of the scope of the patent application, wherein the gate dielectric layer of the second layer is manufactured to a second thickness between 10 and 50 angstroms. 16. · A method for manufacturing a gate dielectric layer of a double gate layer, comprising: (a) providing a substrate, the surface of the substrate is divided into surface regions, and the surface regions are electrically isolated from each other; the surface region (1) Region 1 covers the PMOS device manufactured with a thick gate dielectric layer; (2) Region 2 covers the NMOS device manufactured with a thick gate dielectric layer (3) Region 3 covers the PMOS device with a thin gate dielectric layer; (4) Region 4 covers the NMOS device with a thin gate dielectric layer (B) performing a first impurity ion implantation on the surface of region 1; (c) performing a second impurity ion implantation on the surface of region 2; (d) fabricating a first gate dielectric layer, Having a first thickness covering the surface of the substrate; (e) performing a third impurity ion implantation on the surface of the region 3; (f) performing a fourth impurity ion implantation on the surface of the region 4; 525266 The 23rd tribute 525266 6. The scope of patent application includes the rapid heating and oxidation treatment of the second surface of the substrate, which uses a single process chamber. 24. The method as described in item 16 of the scope of patent application, which further includes an additional step of pre-cleaning the thin gate RCA. This additional step is performed in manufacturing a second gate dielectric layer. The younger brother covering the substrate has the same surface. 25. The method as described in item 16 of the scope of the patent application, wherein the gate dielectric layer of the second layer is manufactured to a second thickness between 10 and 50 angstroms. 26. The method according to item 16 of the scope of patent application, wherein performing the first and second impurity ion implantation includes implanting impurity ions into the bare surface of the substrate. 27. The method according to item 16 of the scope of patent application, wherein the third impurity ion implantation on the surface of the area 3 includes: manufacturing a first exposure mask covering the gate electrode of the first layer On the dielectric layer substrate, the first exposure mask includes at least one opening covering the surface of the gate dielectric layer of the first layer, and the at least one opening covering the surface of the region 3; performing a third impurity; Ion implantation uses the first exposure mask as an ion implantation mask; and removes the first exposure mask from the gate dielectric layer of the first layer. 28. The method according to item 27 of the scope of patent application, wherein the first exposure mask includes a photoresist. 2 9 · The method described in item 16 of the scope of patent application, wherein the fourth Page 24 525266 VI. Patent application The implantation of impurity ions on the surface of area 4 includes the steps of: manufacturing a second exposure mask covering the surface of the gate dielectric layer of the first layer, and the second exposure mask The curtain system includes at least one opening covering the surface of the gate dielectric layer of the first layer, the at least one opening covering the surface of the region 4; performing a fourth impurity ion implantation using the second The exposure mask is used as an ion implantation mask; and the second exposure mask on the surface of the gate dielectric layer of the first layer is removed. The method described in item 29 of the scope of patent application, The second exposure mask includes a photoresist. 3 1. The method as described in item 16 of the scope of patent application, wherein removing the first gate dielectric layer on areas 2 and 4 includes the steps of: manufacturing a third curtain covering the first On the surface of the gate dielectric layer of one layer, the third mask exposes the surface of the gate dielectric layer of the first layer, which is in a region where the gate dielectric layer of the first layer covers the surface of the substrate. At places 3 and 4, the gate dielectric layer of the first layer on areas 3 and 4 of the surface of the substrate is removed, and the third mask is used as an etch stop layer to expose areas 3 and 4 of the substrate. 4 of the surface; and removing the third mask on the gate dielectric layer of the first layer. 3 2 · The method as described in item 31 of the scope of patent application, wherein the third mask system includes a photoresist. 3 3 · The method described in item 19 of the scope of patent application, which also includes Page 25 525266 6. The scope of the patent application has an additional step of reducing the thickness of the first gate dielectric layer to a measurable amount. This additional step is performed in the manufacture of a second gate dielectric layer. Covering the surfaces of the substrate regions 3 and 4 before this step. 3 4 · The method described in item 33 of the scope of patent application, wherein the reduction of the thickness of the gate dielectric layer of the first layer is a measurable amount, which includes the use of HF chemistry, whereby the HF system is 100: 1 and 2 0 0: 1 dilution. .: 3 5 · The method according to item 33 of the scope of patent application, wherein reducing the thickness of the first gate dielectric layer by a measurable amount includes reducing the first thickness to a thickness of one. Thickness between 40 and 70 Angstroms. 36. The method according to item 16 of the scope of patent application, wherein the removing of the first gate dielectric layer on the substrate regions 3 and 4 includes using HF chemistry, whereby the HF system is used. Take 100 ·· 1. Page 26