JPH033978B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal transmission device in a data processing system that processes multi-channel data via a transmission relay circuit.

When transmitting data between multiple devices such as a disaster prevention warning system and processing the data, in other words, when multi-channel data grouped at distance intervals is processed by a central processing unit.
Data signal lines from each channel must be wired separately, requiring a large number of signal lines. Therefore, there was a problem in that the equipment was complicated.

This invention was made by focusing on the above-mentioned conventional problems, and it connects a single control line and a single data transmission line in parallel to a central processing unit, and also connects the control line and data transmission line in parallel. A transmission line is connected to a plurality of transmission relay circuits to which data output lines of each channel are connected, and three types of control signals including timing signals with different pulse widths are output from a central controller to the control line. select each transmission relay circuit, and the data of each channel of the selected transmission relay circuit is sequentially transmitted to the central processing unit via the data transmission relay circuit in synchronization with a timing signal transmitted from the control line. In this way, the purpose is to solve the above problems.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1, 1... are a plurality of transmission relay circuits to which data output lines 3 of each channel 2 are connected;
4 is a central processing unit that processes the data of each channel 2, 2..., and 5 and 6 are single control lines and data transmission lines that are connected in parallel to this central processing unit 4, respectively, and are connected to each transmission relay circuit. It's connected. That is, the central processing unit 4 and each transmission relay circuit 1 are connected in the form of a bus.

Three types of control signals with different pulse widths are sent from the central processing unit 4, namely, a start signal Ss with a pulse width To that indicates the starting point for selecting the transmission relay circuit 1, and an address signal with a pulse width T1 that selects the transmission relay circuit ₁ . Sa and a timing signal Sd with a pulse width T ₂ that informs when to sequentially switch the digital signals that are the data of each channel 2, 2, etc. input to the selected transmission relay circuit 1 and output them to the data transmission line 6 in a time-division manner. The three types of control signals are sequentially output to the control line 5.

First, a start signal Ss is output to reset each transmission relay circuit 1, 1, etc., and an address signal Sa is then output to select the transmission relay circuit 1 to be output.
prepare for the reception. Then, it outputs the address signal Sa, and selects the transmission relay circuit 1 that matches the address of the address signal Sa. At this time, the channel counter of the selected transmission relay circuit 1 is reset, making it ready to receive the timing signal Sd. Next, the timing signal
Sd is output, but after the start signal Sa is output, the number of address signals Sa represents the address,
The transmission relay circuit 1 whose address signal Sa matches the set address is selected, and the selected transmission relay circuit 1 sequentially centrally processes each data of each channel 2, 2, etc. via the data transmission line 6. Transmit to device 4. Thereafter, similarly, the central processing unit 4 sequentially selects each transmission relay circuit 1, 1..., and the selected transmission relay circuit 1 similarly transmits the data of each channel 2, 2... to the central processing unit 4. To go.

In this way, the data of the multi-channels 2, 2, . . . can be processed by the central processing unit 4.

Next, an example of the transmission relay circuit 1 will be described in detail based on the drawings.

Figure 2 is an electrical circuit diagram of this transmission relay circuit 1.
In the figure, P ₁ is an input terminal connected to the control line 5, P ₂ is an output terminal connected to the data transmission line 6,
IC ¹ is a buffer for waveform shaping, 7 is a pulse width discrimination circuit, and the first delay circuit 8 is composed of a resistor R ₁ , a capacitor C ₁ , a buffer IC ₂ and a diode D ₁
and a second delay circuit 9 composed of a resistor R ₂ , a capacitor C ₂ , a buffer IC ₃ and a diode D ₂ , and each of the delay circuits 8 and 9 is connected to a DC power supply. R ₃ is a resistor connected to the DC power supply, C ₃ is a capacitor, IC ₄ is an inverter,
IC ₅ is an OR gate, 10 is an address counter for determining addresses, and 11 is an address setting circuit, which has a plurality of switches (four in this embodiment) for setting addresses in binary numbers. IC ₇ is NAND
gate, IC ₉ is an AND gate, IC ₈ is a plurality of (three in this embodiment) channel selectors IC ₁₀ to which data output lines 3 of each channel 2, 2... are connected;
IC ₁₁ , channel counter that controls IC ₁₂ , IC ₁₃ ,
IC ₁₄ and IC ₁₅ are OR gates, IC ₁₆ and IC ₁₇ are inverters, IC ₁₈ is an AND gate, and IC ₁₉ is a three-cheat buffer.

Further, FIG. 3 shows a time chart of each point shown in FIG. 2.

The operation will be explained based on the above configuration. Note that the relationship between the pulse widths of the start signal Ss, address signal Sa, and timing signal Sd is T ₀ >
This will be explained as T ₁ > T ₂ .

Three types of control signals shown in FIG. 3A are input from the central processing unit 4 to the input terminal _P1 via the control line 5. This control signal, the pulse signal, is
It is input to the NAND gate IC ₇ and the pulse width discrimination circuit 7 via IC ₁ . This pulse signal is processed by the first delay circuit 8 of the pulse width discrimination circuit 7 for a time T ₃ by adjusting the charging time using a resistor R ₁ and a capacitor C ₁ .
A pulse signal is output from buffer IC ₂ with a delay of . (In this example, the delay circuit T _{3 is}
It is set so that T ₃ > T ₂ . ) i.e.
As shown in FIG. 3C, a start signal Ss and an address signal Sa are obtained by removing the timing signal Sd from the control signal. At this time, diode _D1 closes the capacitor at the falling edge of the input pulse signal.
The charge on _C1 is discharged to match the falling edge of the output pulse signal. Similarly, the second delay circuit 9 delays the control signal by a time T ₄ (in this embodiment, the delay circuit T ₄ is set so that T ₈ > T ₄ > T ₁ ). Of these, only the start signal Ss can be obtained.

On the other hand, resistor R ₃ , capacitor C ₃ and buffer
The IC ₅ obtains an H level voltage for a time T ₅ from the time of power-on, and this signal is ORed with the start signal Ss obtained from the pulse width discrimination circuit 7 to perform a power-on reset of the address counter 10. . This is to prevent data output from each transmission relay circuit 1, 1, . . . to the data transmission line 6 when the power is turned on. In addition, since each transmission relay circuit 1, 1... is addressed by the address setting circuit 11, the address signal among the control signals
Sa is counted by the address counter 10, and when it matches the set address, it can be identified that the own transmission relay circuit 1 has been selected.

To explain the above process in more detail, first, prior to data transmission on each channel 2, 2..., the central processing unit 4 outputs a start signal Ss, and the address counters 10 of all transmission relay circuits 1 are reset. This means that the central processing unit 4 has selected the transmission relay circuit 1 with address zero. (Actually, each transmission relay circuit 1 is not set to address zero.) At this time, the address counter 10 outputs the output of the pulse width discrimination circuit 7.
Since it is connected to the CLOCK terminal, it will count +1, but will be reset immediately afterwards.

When selecting the transmission relay circuit 1 with the n-th address, successively the n address signals Sa ₁ , Sa ₂ , . . .
_Output Sao. Since the address setting circuit 11 has an address set in binary by the SW, when this address and the output of the address counter 10 match, the signal at point 2 shown in FIG. 2 will be changed to the signal shown in FIG. Thus, the voltage remains at H (high) level until the next address signal Sa is output, and the address selection signal Sc is obtained. This address selection signal Sc and the output signal C of the pulse width discrimination circuit 7 are ANDed.
AND is performed by gate IC ₉ , and channel counter IC ₃ is reset by this output signal H. An output signal obtained by NANDing the address selection signal Sc and the control signal A is input to the CLOCK terminal of _{the channel counter IC 3 .}
Since the counter operates at the falling edge of the CLOCK pin input signal, the channel counter
IC ₈ counts +1. But at the same time RESET
Since the reset signal H is input to the terminal, the output Q ₀ ,
Q ₁ ,...Q ₆ are reset. The outputs Q ₀ , Q ₁ , ...Q ₆ of the channel counter IC ₈ are connected to the respective select terminals A, B, and C of the channel selectors IC ₁₀ , IC ₁₁ , and IC ₁₂ , and the outputs Q 0 , Q 1 , ... The signal is output from output terminal Z. Also,
When the Dis terminal is set to an H (high) level voltage, the output terminal Z becomes high impedance.

When the nth address signal Sa.n is output and its own relay circuit 1 is selected, the channel counter
IC ₈ is reset and channel selector IC ₁₀ is X ₀
, IC ₁₁ selects X ₈ , IC ₁₂ selects X ₁₆ .

In addition, the outputs Q ₃ and Q ₄ of channel counter IC ₈
Channel selector via OR gate IC ₁₃
Channel selector to the Dts terminal of IC ₁₀ , similarly via inverter IC ₁₆ and OR gate IC ₁₄
The channel counter is connected to the Dts terminal of IC ₁₁ and to the Dts terminal of channel selector IC ₁₂ via inverter IC ₁₇ and OR gate IC ₁₅ .
When the output of IC ₆ is decimal, from 0 to 7, only the Dts terminal of IC ₁₀ has an L level voltage (Figure 3), and from 8 to 15, the voltage is low (Figure 3).
The Dts terminal of IC ₁₁ is set to an L (low) level voltage (FIG. 3, h), and the Dts terminal of IC ₁₂ is set to an L (low) level voltage (FIG. 3, h) from 16 to 23. Then, the output of channel counter IC ₈ is the above 0~7, 8~15, 16
~23, terminals A, B, C of channel selectors IC ₁₀ , IC ₁₁ , IC ₁₂ from channel counter IC ₈
Since the output pattern to each channel is the same, it is possible to switch each channel signal X ₀ , X ₁ , . . . , X ₂₃ .

In this way, when the address signal Sa.n is output, the n-th transmission relay circuit 1 of the address is selected, and the channel signal _X0 of the channel selector IC ₁₀ is first output from the output terminal Z, and the As shown in , the timing signal among the sequential control signals
As _{Sd . 1} , Sd _{. 2 ,} . IC ₁₉ is a three-state buffer, and its control terminal C has an address selection signal Sc and an AND gate IC _7.
Since the signal _that is ANDed with the output of _Sa.
The gate of three-state buffer IC ₁₉ opens only when Sa. ₂ , ... Sa. _o , Sa.n+1 or the timing signals Sd. ₁ , Sd ₂ ... Sd. ₂₃ are at L (low) level voltage, and the output is output. A digital signal (FIG. 3 O), which is the data of each channel 2, 2, . . . , is sequentially output from the terminal P ₂ to the data transmission line 5.

As described above, when the transmission of the digital signal which is the data of each channel 2 in which the data output line 3 is connected to the transmission relay circuit 1 at the n-th address is completed,
The n+1st address signal Sa.n+1 is output from the central processing unit 4 again, and the address selection signal Sc becomes an L (low) level voltage and the timing signal Sd
Incorporation is prohibited. Then, the data transmission line 5 and the output terminals Z of the channel selectors IC ₁₀ , IC ₁₁ , and IC ₁₂ are electrically disconnected, and the address n+1 is
Control is transferred to the second transmission relay circuit 1.

As described above, according to the present invention, a single control line and a single data transmission line are connected in parallel to the central processing unit, and the control line and data transmission line are connected to the data output of each channel. The central processing unit outputs three types of control signals including timing signals with different pulse widths to the control lines to select each transmission relay circuit, and selects each transmission relay circuit. The data of each channel of the selected transmission relay circuit is sequentially transmitted to the central processing unit via the data transmission relay circuit in synchronization with the timing signal transmitted from the control line. There is no need to wire the data signal lines of the channels separately, and data can be easily transmitted using two signal lines, which has the effect of simplifying the equipment.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a multi-channel digital signal transmission system according to the present invention, Fig. 2 is an electric circuit diagram of a transmission relay circuit according to the invention, and Fig. 3 is a time chart of each point shown in Fig. 2. be. 1...Transmission relay circuit, 2...Channel, 3...
...Data output line, 4...Central processing unit, 5...Control line, 6...Data transmission line, 7...Pulse width discrimination circuit, 10...Address counter, 11...Address setting circuit, IC ₈ ... channel counter,
IC ₁₀ , IC ₁₁ , IC ₁₂ ...Channel selector, Ss...
... Start signal among control signals, Sa ... Address signal among control signals, Sd ... Timing signal among control signals.

Claims (1)

[Claims] 1. In a data processing system having a plurality of transmission relay circuits to which data output lines of each channel are connected, and a central processing unit that processes data of each channel, the central processing unit has a single control line and a single data transmission lines are connected in parallel, and the control line and data transmission line are respectively connected to the plurality of transmission relay circuits, and three types of control signals including timing signals with different pulse widths are transmitted from the central processing unit. By outputting to the control line, each transmission relay circuit is selected,
A digital signal characterized in that the data of each channel of the selected transmission relay circuit is sequentially transmitted to the central processing unit via the data transmission line in synchronization with a timing signal transmitted from the control line. Transmission device.