SU966898A1

SU966898A1 - Switching apparatus

Info

Publication number: SU966898A1
Application number: SU813263627A
Authority: SU
Inventors: Виктор Борисович Моисеенко; Иван Семенович Кузнецов; Андрей Владимирович Вапельник; Александр Николаевич Сибилев
Original assignee: Специальное Конструкторское Бюро Производственного Объединения "Виброприбор"
Priority date: 1981-01-04
Filing date: 1981-01-04
Publication date: 1982-10-15

Description

Изобретение относится к области автоматики и коммутационной техники.,The invention relates to the field of automation and switching equipment.,

Известны коммутаторы, содержащие генератор и счетчики flj.Known switches containing a generator and counters flj.

Недостатком известных устройств является низкое быстродействие.A disadvantage of the known devices is the low speed.

Наиболее близким к предложенному по техническому решению является коммутатор, содержащий первый счетчик, счетный вход которого соединен с выходом генератора, а выходы - с первой группой выходных шин, а также второй счетчик, выходы которого подключены к второй группе выходных шин f 2,].Closest to the proposed technical solution is a switch containing a first counter, the counter input of which is connected to the output of the generator, and the outputs are connected to the first group of output buses, as well as the second counter, the outputs of which are connected to the second group of output buses f 2,].

Недостатком такого устройства является низкое быстродействие.The disadvantage of this device is the low speed.

Цель изобретения - повышение быстродействия коммутатора.The purpose of the invention is improving the performance of the switch.

Указанная цель достигается тем, что в коммутатор, содержащий первый счетчик, счетный вход которого соединен с выходом генератора, а выхо2 ды - с первой группой выходных шин, а также второй счетчик, выходы которого подключены к второй группе выходных шин, введены управляемый делитель,два элемента сравнения, два элемента задержки, два элемента И и элемент И-НЕ, первый вход которого соединен с выходом генератора и тактирующим входом управляемого делитеio ля, второй вход - с выходом первого элемента сравнения, третий входс выходом второго элемента сравнения, четвертый вход - со счетным входом второго счетчика и через первый эле15 мент задержки с выходом управляемого делителя, а выход подключен к первому входу первого элемента Й, второй вход которого соединен с шиной сброса, а выход подключен к установлен²⁰ ному входу второго счетчика и первому входу второго элемента И, второй вход которого через второй элемент задержки соединен с выходом управля3 966898 емого делителя, а выход - с установочным входом первого счетчика, выходы которого подключены к информационным входам управляемого делителя и первым входам первого элемента сравнения, вторые входы которого подключены к первой группе входных шин, при этом управляющие входы управляемого делителя соединены с второй группой входных шин, а выходы второго счетчика подключены к первым вхо-, дам второго элемента сравнения, вторые входы которого соединены с тре* тьей группой входных шин.This goal is achieved by the fact that in the switch containing the first meter, the counting input of which is connected to the output of the generator, and the outputs — with the first group of output buses, as well as the second counter, the outputs of which are connected to the second group of output buses, a controlled divider is introduced, two comparison element, two delay elements, two AND elements, and the NAND element, the first input of which is connected to the output of the generator and the clock input of the controlled divider, the second input is the output of the first comparison element, the third input is the output of the second element and in comparison, the fourth input is with the counting input of the second counter and through the first delay element with the output of the controlled divider, and the output is connected to the first input of the first element,, the second input of which is connected to the reset bus, and the output is connected to the installed ^20th input of the second counter and the first input of the second element And, the second input of which through the second delay element is connected to the output of the controlled3 966898 removable divider, and the output to the installation input of the first counter, the outputs of which are connected to the information inputs of the controlled case the first inputs of the first comparison element, the second inputs of which are connected to the first group of input buses, while the control inputs of the controlled divider are connected to the second group of input buses, and the outputs of the second counter are connected to the first inputs of the second comparison element, the second inputs of which are connected with a third group of input buses.

На фиг. 1 представлена функциональная схема коммутатора) на фиг.2функциональная схема управляемого , делителя.In FIG. 1 is a functional diagram of a switch) in FIG. 2 is a functional diagram of a controlled divider.

Коммутатор содержит, счетчик 1, выходы 2-1, 2-2,...2-И которого сое-, _:динены с выходными шинами 3, а счетный вход,- с выходом генератора 4, счетчик 5, выходы которого подключены к выходным шинам 6, элемент И-НЕ 7». первый вход которого соединен с выхо- 25 дом генератора 4 и тактирующим входом управляемого делителя 8, второй вход - с выходом элемента 9 сравнения, третий вход - с выходом элемента 10 сравнения, четвертый вход - со счет- ₃₀ным входом счетчика 5 и через элемент 11 задержки с выходом управляемого делителя 8, а выход подключен к первому входу элемента И 12, второй вход которого соединен с шиной 13 сброса, а выход подключен к установочному входу счетчика 5 и первому входу элемента И 14, второй вход которого через элемент 15 задержки соединен с выходом управляемого делителя 8, а выходс установочным входом счетчика 1, выходы 2-1, 2-2,...,2-И которого подключены к информационным входам управляемого делителя 8 и первым входам . элемента 9 сравнения, вторые входы которого подключены к входным шинам 1.6, управляющие входы управляемого делителя 8 соединены с входными шинами 17“1,172,...,17W, θ выходы счетчика 5 подключены к первым входам элемента 10 сравнения,, вторые входы которого соединены с входными шинами 18.The switch comprises a counter 1 outputs 2-1, 2-2, ... 2-I which _soe-,: dineny with output lines 3, and the counter input - with the output of the generator 4, the counter 5, the outputs of which are connected to the output tires 6, the element AND NOT 7 ". the first input of which is connected to the output 25 of the generator 4 and the clock input of the controlled divider 8, the second input - with the output of the comparison element 9, the third input - with the output of the comparison element 10, the fourth input - with the counter input _{30 of the} counter 5 and through the element 11 the delay with the output of the controlled divider 8, and the output is connected to the first input of the element And 12, the second input of which is connected to the reset bus 13, and the output is connected to the installation input of the counter 5 and the first input of the element And 14, the second input of which is connected through the delay element 15 with control output emogo divider 8, and mounting vyhods input counter 1 outputs 2-1, 2-2, ..., 2 and which are connected to the data inputs managed divider 8 and the first input. comparison element 9, the second inputs of which are connected to the input buses 1.6, the control inputs of the controlled divider 8 are connected to the input buses 17 “1,172, ..., 17W, θ the outputs of the counter 5 are connected to the first inputs of the comparison element 10, the second inputs of which are connected to input buses 18.

(О(ABOUT

Управляемый делитель 8 содержит элементы И-НЕ 19, элементы И 20, выходную шину 21.Managed divider 8 contains the elements AND 19, elements AND 20, the output bus 21.

Коммутатор работает следующим образом.The switch operates as follows.

При подаче по шине 13 сброса нулевого логического уровня происходит ; установка счетчика 1 в исходное нулевое состояние, а счетчика 5 ~ в состояние формирования адреса первой группы. Далее, при подаче по шине 13 сброса единичного логического уровня счетчик 1 начинает работу. В первом режиме функционирования коммутатора по входным шинам 18 поступает двоичный код, соответствующий адресу первой группы, а на входные шины 16 устанавливается любой адрес канала, меньший или равный по численному значению количеству каналов в группе, подаваемый в унитарном коде по входным шинам 171,,17^_2,...17-Щ· В момент поступления первого отрицательного импульса на выходах 2-1, 2-2,...,2-и счетчика 1 формируется адрес первого канала, выраженный в двоичном коде, а при поступлении следующих импульсов на выходах последовательно формируются адреса других каналов.When applying on the bus 13 reset zero logic level occurs; setting counter 1 to the initial zero state, and counter 5 ~ to the state of forming the address of the first group. Further, when applying on the bus 13 reset a single logical level, the counter 1 begins to work. In the first mode of operation of the switch, the binary code corresponding to the address of the first group is received through the input buses 18, and any channel address less than or equal in number to the number of channels in the group, supplied in the unitary code via the input buses 171, 17, is set to the input buses 16 ^_ 2, ... 17-Щ · At the moment the first negative pulse arrives at the outputs 2-1, 2-2, ..., 2 of the counter 1, the address of the first channel is formed, expressed in binary code, and when the next pulses arrive at the outputs the address is sequentially formed other channels.

С выхода элемента 10 сравнения единичный логический уровень поступает на элемент И-НЕ 7 с момента установки счетчиков 1 и 5 в исходное состояние.. При появлении на выходах 2-.From the output of the comparison element 10, a single logical level is supplied to the AND-NOT 7 element from the moment the counters 1 and 5 were set to their initial state. When outputs 2- appear.

1,2-?...,2-ц счетчика 1 адреса канала, совпадающего с адресом, поступающим по входным шинам 16, на выходе элемента 9 формируется единичный ’ логический уровень,.и в момент, κοι— да на вход элемента И-НЕ 7 поступает положительный фронт следующего импульса от генератора 4, на выходе Элемента И-НЕ 7 формируется нулевой логический уровень, который через элементы И 12 и 14 устанавливает счетчики в исходное состояние. По отрицательному фронту этого импульса на выходах 2-1, 2-2,...,2-и счетчика 1 заново формируется адрес первого канала, и цикл работы повторяется аналогично описанному.1,2 -? ..., 2-c counter 1 of the channel address, which coincides with the address received on the input buses 16, at the output of element 9 a single 'logic level is formed, and at the moment, κοι - yes to the input of the And NOT 7 receives a positive edge of the next impulse from the generator 4, at the output of the AND-NOT 7 element, a zero logic level is formed, which sets the counters to the initial state through the AND 12 and 14 elements. On the negative edge of this pulse at the outputs 2-1, 2-2, ..., 2 of the counter 1, the address of the first channel is re-formed, and the operation cycle is repeated as described.

В другом режиме по входным шинам 18 подается двоичный код адреса любой другой группы. Когда адрес канала по численной величине совпадает с количеством каналов, определенным унитарным кодом по входным шинам 17“ 1, 17“2,... 17hl, по положительному фронту импульса генератора 4 на выходе управляемого делителя 8 формируется нулевой логический уровень, который с задержкой через элемент 11 задержки поступает на входы счетчика 5 и элемент И-НЕ /. При этом на вы5 966898 6 ходах счетчика 5 формируется адрес второй группы. Указанный нулевой логический уровень через элемент 15 задержки и элемент И 14 устанавливает счетчик 1 в исходное состояние. 5 С приходом отрицательного фронта импульса счетчик 1 формирует адрес первого канала и начинается новый цикл формирования адресов каналов второй группы. Аналогично описанному; на 10 выходе управляемого делителя 8 формируется сигнал, записывающий в счетчик 5 адрес третьей группы и устанавливающий счетчик 1 в исходное состояние. Далее, по выходам счетчика 15 1 формируются адреса каналов, апо. выходам счетчика 5 - адреса групп, к которым относятся каналы. Это продолжается до тех пор, пока адреса каналов и групп не совпадут с адре- 20 сами каналов и групп, подаваемыми по входным шинам 16 и 18. _х In another mode, a binary address code of any other group is supplied via the input buses 18. When the channel address in numerical value coincides with the number of channels determined by the unitary code on the input buses 17 “1, 17“ 2, ... 17hl, a zero logic level is formed at the output of the pulse of the generator 4 at the output of the controlled divider 8, which is delayed by the delay element 11 is supplied to the inputs of the counter 5 and the element AND-NOT /. At the same time, at high 5 966898 6 moves of counter 5, the address of the second group is formed. The specified zero logic level through the delay element 15 and the AND element 14 sets the counter 1 to its initial state. 5 With the arrival of the negative edge of the pulse, counter 1 generates the address of the first channel and a new cycle of forming the addresses of the channels of the second group begins. Similar to that described; at 10 the output of the controlled divider 8, a signal is generated that records the address of the third group in counter 5 and sets the counter 1 to its initial state. Further, at the outputs of the counter 15 1 the channel addresses are formed, apo. counter outputs 5 - addresses of groups to which the channels belong. This continues until the addresses of the channels and groups coincide with the addresses of the channels and groups supplied via the input buses 16 and 18. _x

Таким образом, введение управляемого делителя, элементов сравнения, 25 задержки, И и И-НЕ, позволяет повысить быстродействие коммутатора.Thus, the introduction of a controlled divider, elements of comparison, 25 delays, AND and NAND, improves the performance of the switch.

Claims

The invention relates to the field of automation and switching technology. Switches are known that contain a generator and counters. A disadvantage of the known devices is the low speed. The closest to the proposed technical solution is a switch containing the first counter, the counting input of which is connected to the generator output, and the outputs to the first group of output buses, as well as the second counter, the outputs of which are connected to the second group of output buses f 2 /. The disadvantage of such a device is low speed. The purpose of the invention is to increase the speed of the switch. This goal is achieved in that the switch containing the first counter, the counting input of which is connected to the generator output, and the outputs to the first group of output buses, as well as the second counter, the outputs of which are connected to the second group of output buses, are entered the comparison element, two delay elements, two AND elements and the NAND element, the first input of which is connected to the generator output and the clocking input of the controlled divider, the second input to the output of the first comparison element, the third input to the output of the second element In comparison, the fourth input is with the counting input of the second counter and, through the first deceleration, with the output of the controlled divider, and the output is connected to the first input of the first element I, the second input of which is connected to the reset bus, and the output is connected to the set input of the second counter and the first input of the second element I, the second input of which is connected to the output of the controlled divider through the second element of the delay, and the output to the set input of the first counter, the outputs of which are connected to the information inputs of the controlled divider and comparing the first inputs of the first element, the second inputs of which the first group podklkzcheny input lines, while the control inputs of the controllable conductive divider connected to the second group of input | 1x buses, and the outputs of the second counter are connected to the first inputs of the second comparison element, the second inputs of which are connected to a third group of input lines. FIG. 1 shows a functional diagram of a switch) FIG. 2 is a functional diagram of a controllable divider. The switchboard contains, counter 1, outputs 2-1, 2-2, ... 2-Vi of which are connected to output buses 3, and the counting input, with generator output k, counter 5, whose outputs are connected to output buses 6, element NAND 7 the first input of which is connected to the generator output k and the clocking input of the controlled divider 8, the second input to the output of the comparison element 9, the third input to the output of the comparison element 10, the fourth input to the counting input of the counter 5 and through element 11 the delay with the output of the controlled dl 8, and the output is connected to the first input of the element 12, the second in the stroke of which is connected to the reset bus 13, and the output is connected to the installation input of counter 5 and the first input of the AND element, the second input of which through the delay element 15 is connected to the output of the controlled divider 8, and the output to the installation input of the counter 1, outputs 2 -1, 2-2, ..., 2-D of which are connected to the information inputs of the controlled divider 8 and the first input of the element 9 of the comparison; however, the second inputs of which are connected to the input buses of 1.61 the control inputs of the controlled divider 8 are connected to the input buses, ..., and the outputs of counter 5 are connected to the first input The element 10 of the comparison, the second inputs of which are connected to the input webs 18. Managed divider 8 contains the elements AND-NOT 19, elements AND 20, output bus 21. The switch operates as follows. When feeding through the reset bus 13 to zero of its logical level, the counter 1 is set to the initial, zero state, and the counter 5 is set to the formation state of the address of the first group. Further, when feeding through the bus 13 for resetting a single logic level, the counter 1 starts operation. In the first operation mode of the switch, the binary code corresponding to the address of the first group enters the input buses 18, and any channel address is set to the input buses 16 less than or equal in number to the number of channels in the group supplied in the unitary code through the input buses 17-1, , 17-2, ... 17-P. At the moment the first negative pulse arrives at outputs 2-1, 2-2, ..., 2 of counter 1, the address of the first channel is generated, expressed in binary code, and when the next pulses arrive, the addresses of other channels are sequentially generated at the outputs. From the output of the comparison element 10, a single logical level arrives at the NE-7 element from the moment of the installation of the counters 1 and 5 to the initial state. When appearing at the outputs 2-. 1,2 -..., 2-V) of the counter 1 of the channel address coinciding with the address received on the input buses 1b, at the output of element 9 a single logic level is formed, and at the moment when the input of the AND-NE element 7 arrives the positive edge of the next pulse from the generator ea, at the output of the element IS-NOT, 7 a zero logic level is formed, which through the elements 12 and k sets the counters to the initial state. On the negative front of this pulse, at the outputs 2-1, 2-2, ..., 2-I of counter 1, the address of the first channel is formed again, and the operation cycle repeats as described. In another mode, the input bus 18 provides the binary code of the address of any other group. When the channel address coincides in numerical value with the number of channels determined by the unitary code on the input buses 171, 17-2, ... 17-Vvi, a zero logical level is formed on the positive edge of the generator pulse at the output of the controlled divider 8, which is delayed through The delay element 11 is fed to the inputs of the counter 5 and the NAND element 7. At the same time, the address of the second group is formed at the outputs of the counter 5. The indicated zero logic level through the delay element 15 and the AND element T sets the counter 1 to the initial state. With the arrival of a negative pulse front, the counter 1 forms the first channel address and a new cycle of forming channel addresses of the second group begins. Similar to that described; At the output of the controlled divider 8, a signal is formed that records the address of the third group in the counter 5 and sets the counter 1 to the initial state. Further, the outputs of the counter 1 form the addresses of the channels, and by. the outputs of counter 5 are the addresses of the groups to which the channels belong. This continues until the channel and group addresses match the channel and group addresses supplied to the input buses 16 and 18. Thus, the introduction of a controlled divider, delay comparison elements, and AND-NOT allows for increased performance. switch. Claims. The switch, containing the first counter, the counting input of which is connected to the generator output, and the outputs to the first group of output buses, and the second counter, the outputs of which are connected to the second group of output buses, characterized in that, in order to improve speed, a controllable divider, two comparison elements, two delay elements, two AND elements and the NAND element, the first input — of which is connected to the generator output and the clocking input of the controlled divider, the second input - with the output of the first comparison element, the third input output Ohm second element. And compare, the fourth input - with the counting input of the second counter and through the first element | ki with the output of the controlled divider, and the output is connected to the first input of the first element And, the second input of which is connected to the reset bus, and the output is connected to the installation input of the second counter and the first input of the second element And, the second input of which through the second delay element is connected to the output of the controlled divider, and the output with the installation input of the first counter, the outputs of which are connected to the information inputs of the controlled divider and the first inputs of the first comparison element, the second inputs of which are connected to the first group input busbars, while the control inputs of the controlled divider are connected to the second group of input buses, and the outputs of the second counter are connected to the first inputs of the second comparison element, the second inputs of which are connected to the third group of input buses. Sources of information taken into account in the examination 1, USSR Copyright Certificate W 516192, cl. H 03 K 17/00, 03.06.7,

2.Avtokrase Certificate of the USSR No. 632087, cl. H 03 K 17/00, 10.05.77 (prototype).