SU894865A1 - Distributor - Google Patents

Description

(5) DISTRIBUTOR

I

The invention relates to automation and computing.

Known pulse distributors, containing a ring counter on the trigger and a decoder p.

The disadvantage of such a distributor is the impossibility of changing the period (time) of the distribution cycle.

The closest technical solution to the proposed is a pulse divider that contains a generator, a shift register whose outputs are connected to output buses, AND, OR elements, a switch and additional generators zero and units 23.

A disadvantage of the known distributor is also the impossibility of implementing variable distribution modes, which reduces the functional capabilities of the device.

The purpose of the invention is the expansion of functional and ionic capabilities.

To achieve this goal, a distributor containing the generator element OR and the first main register, the bit outputs of which are connected to the output buses, the second and the third main registers connected in series, the second OR element, frequency dividers, write, set and start drivers , a group of elements AND-NOT and connected in series the first and second additional registers, and

Claims (2)

-X generator output is connected to the first inputs of the main registers, the first inputs of the frequency dividers, and the write, set, and start pulse generators, the output of which is connected to the first inputs of the OR elements, the outputs of which are connected to the inputs of the first and second additional registers, respectively, and the output outputs additional registers are connected to the first inputs of the first and second groups of NAND elements, the outputs of which are connected to the first inputs of the third and fourth groups of NAND elements, respectively, and the second inputs of the p first and third main registers, while the third inputs are connected to the outputs of the third and fourth groups of NAND elements, in addition, the output of the first frequency divider is connected to the second input of the trigger pulse generator, and the output of the second frequency divider is connected to the second inputs of the write pulse shaper and settings, the output of the last of which is connected to the second inputs of the first and second groups of NAND elements, and the second input of the first main register and the second inputs of additional registers. are connected to the output of the recording pulse generator b, the second inputs of the frequency dividers, the third inputs of the first additional register, the second inputs of the third group AND –NE and the second input of the second element OR are connected to the first control bus, the third inputs of the frequency dividers and the second input of the first element OR are connected to the second control bus, and the fourth input of the first splitter, the third inputs of the first, second and third groups of AND-NOT elements and the second inputs of the fourth group of AND-II elements are connected to the third control bus, while the output of the first main register is connected to the third input of the second main register, the outputs of which, as well as the outputs of the third Main Register, are connected by the corresponding output buses. The drawing shows a functional diagram of the distributor. The circuit contains generator 1, element 2 OR, main shift registers 3-5, additional shift registers 6 and 7, output buses (outputs) elements OR 9 groups of AND-NOT elements .10-13, shaper I write pulses, shaper 15 pulse co-installations, a driver of 16 trigger pulses, dividers of 17 and 18 h and control buses 19-21. The operation of the distributor is carried out as follows. In the first mode of operation of the device, the sequential distribution of pulses is carried out, when the control bus 21 constantly has a zero level, and on the control buses 19 and 20 - a single level. At the inputs of groups of elements 10–12, zero levels are set, therefore, at the inputs of the main registers t and 5, unit levels are constantly present. The frequency division factor of the frequency divider 17 is set at the controlled input equal to the sum of the bit outputs (number of flip-flops) of the main registers 3-5. With the arrival of the first pulse from the output of the generator 1, a pulse of zero level and duration not exceeding the output pulse generator 1 is output. the duration of one clock pulse from the output of the generator 1, which is recorded by the zero level in the first trigger of the main register 3. With the arrival of the second clock, the second trigger of the main register 1 is shifted to zero PICs are set, and the first - in a unit, etc., until the output line 8 of the distributor from the last discharge outlet Vits not zero. This ends the first distribution cycle. The second distribution cycle is similar to the first. In the second mode of operation, a zero level is established on the control bus 20, and a single one on the control buses 19 and 21. Therefore, a unit level is set at the input of the OR 9 element, which prohibits the passage of pulses through this element, and zero at the input of the OR 2 element. On the single inputs of the triggers of the additional register 6 and the inputs of the group of elements AND-NOT 12, the unit levels are set. At the inputs of groups of elements AND-NOT 10-13, the unit level is constantly present, therefore, in the initial state, on the unit inputs of the trigger registers of the main registers j and 5, the zero level is constantly present, and on the zero inputs - the unit level. For this reason, the bit outputs 8 of the main registers 3 and 5 are in a single state. The division factor of the frequency divider 17 is set larger by a unit of the sum of the bit outputs of the main register 3, and the division factor of the frequency divider 18 is equal to the product of the sum of the bit outputs of the main register 3 and the sum of the bit outputs of the main registers 4 and 5. With the arrival of the first clock cycle from the generator output 1, at the outputs of the formers It and the 16th pulses of recording and triggering, pulses are produced with zero levels, which are recorded in the triggers of the main and auxiliary registers 3 and 6. With the arrival of the second pulse c in The output of the generator 1, another trigger of the main register 3 is shifted to the zero state, and its first trigger to the single state, and so on, until the last output 8 of the register 3 is not aligned with the zero level. The next cycle at the output of the generator 15 of the pulses of the installation is allocated a pulse by a unit level, which passes through the first element of the groups of elements AND-NE 10 to the zero level. Therefore, a single level is set at the single input of the first trigger of the main register, and zero at the zero input, which leads to the transfer of this trigger to the zero state. This ends the first subcycle of the allocation. At the beginning of the second sub-cycle of the first distribution cycle, from the output of the generator T of the write pulses, a pulse is again allocated, which is recorded in the first trigger of the main register 3. At the same time, the first trigger of the additional register 6 is transferred to the single state, and the second trigger is in the zero state. condition. At the end of the second distribution sub-cycle, i.e. after the zero signal appears from the last bit output of the main register 3 by the next clock pulse from the generator output 1 at the output of the imaging unit 15 pulses of the installation, re-allocate it with a pulse with a unit level that passes through the second element of the group of NAND elements 10 zero level at the zero input of the second trigger of the main register 4 and the first input of the second element of the group of elements AND-NOT 12, which leads to the appearance of a unit level at the single input of the second trigger of the main register which is thrown a zero state. This ends the second distribution sub-cycle. The first distribution cycle ends with the fact that after the zero level appears on the last bit during 8 main register 3, the setup pulse selected by the next clock will transfer the last trigger of the main register 5 from the single state to the zero state. 8 5 "In the third mode of operation, a zero level is established on the control bus 19, and on buses 20 and 21 a single level is established. Therefore, the inverse bit outputs of the auxiliary register 6 are set to the zero state, and the inputs of the group of elements AND-NOT 12 arrive at the zero level. For this reason, at the zero and single inputs of the triggers of the main register U there will be permanently single levels and the distribution of pulses will be performed (as in the main register 3) only over the controlled inputs. The division factor of the frequency divider 17 is set larger by a unit of the sum of the bit outputs of the main registers 3, and the division factor of the frequency divider 18 is equal to the product of the sum of the bit outputs of the main registers 3 and f and the sum of the bit outputs of the main register 5 This distribution mode is similar to the second mode only with the difference that the distribution sub-cycle ends with the successive generation of signals from the bit outputs of 8 main registers 3 and one of the bit outputs of the main register country 5. The introduction of additional registers, frequency dividers, drivers for recording, setting and triggering, AND-NOT and OR elements allows forming a variable pulse distribution cycle, since, in addition to equal distribution of pulses from the bit outputs of the main registers, which are the outputs of the distributor , variable distribution modes are performed, in which the distribution signals from different outputs of one main registers are generated more often than from the bit outputs of other main registers. Claims of the invention A distributor comprising an oscillator, an OR element and the first main register, the bit outputs of which are connected to the output buses, differing in that, in order to expand the functionality, the second and third 7 main registers connected in series are entered into it, the second element of the IL frequency dividers, pulse drivers for recording, setting and starting, groups of NAND elements and the first and second additional registers connected in series, the generator output being connected to the first inputs the main registers to the first inputs of the frequency dividers and shapers of recording pulses, installation and start, the output of the last of which is connected to the first inputs of the OR elements, the outputs of which are connected to the inputs of the first and second additional registers, respectively, and the output outputs of the additional registers are connected to the first the inputs of the first and second groups of NAND elements, the outputs of which are connected to the first inputs of the third and fourth groups of NAND elements, respectively, and the second inputs of the second and third main register Ori, the third inputs of the latter are connected to the outputs of the third and fourth groups of NAND elements, in addition, the output of the first frequency dividers is connected to the second input of the trigger pulse generator, and the output of the second frequency divider is connected to the second inputs of the recording and setting pulse drivers, output the last of which is connected to the second inputs of the first and second groups of NAND elements, and the second input of the first main register and the second inputs of the additional registers are connected to the output of the write pulse generator, the second the moves of the frequency dividers, the third inputs of the first additional register, the second inputs of the third NAND group and the second input of the second OR element are connected to the first control bus, the third inputs of the frequency dividers AND the second input of the first OR element are connected to the second control bus, and the fourth input the first frequency divider, the third inputs of the first, second and third groups of NAND elements and the second inputs of the fourth group of NAND elements are connected to the third control bus, while the output of the First main register is connected to the third input the main register, the outputs of which, as well as the outputs of the third main register are connected to the corresponding output buses. Sources of information taken into account in the examination 1. USSR author's certificate number 372690, cl. H 03 K 17/62, 1971. 2. USSR author's certificate number 617843, cl. H 03 K 17/62, 1978. 63