JPH0338850A - Method for apparatus for selecting semiconductor chip - Google Patents

Abstract

PURPOSE:To eliminate a useless process by a method wherein an aging operation and a test of many semiconductor chips which are arranged on a wafer are executed in parallel and the semiconductor chips are selected in a wafer state. CONSTITUTION:Terminals 111, 121,... are extracted respectively at peripheral parts of semiconductor chips 11, 12, 13,... which have been arranged on a wafer 10. Normally, 200 to 300 pieces of such semiconductor chips are arranged on the wafer 10; an arrangement interval between the individual terminals is several tens of mmu to several hundred mmu. An aging operation and a test of the many semiconductor chips 11, 12, 13,... which are arranged on the wafer 10 are executed in parallel. When the semiconductor chips 11, 12, 13,... are decided to be defective in a state that they are arranged on the wafer 10, they are thrown away; thereby, it is possible to eliminate a useless operation that the defective semiconductor chips are sent to a bonding process of connection pins and a packaging process.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method and apparatus for sorting semiconductor chips.

Conventional technology In the manufacture of IC devices such as memories and LSI locks made of semiconductor chips, a large number of semiconductor chips are formed on a silicon wafer through various processes such as photo printing and etching, and then each semiconductor chip is separated into individual semiconductor chips. It is manufactured by dicing, packaging, etc. Currently, 200 to 300 semiconductor chips are arranged on a wafer. In the general manufacturing process, each semiconductor chip on the wafer is tested one by one using a combination of a wafer prober and a tester, and semiconductor chips that deviate from the standard at this stage are marked with ink and defective. Therefore, the chip was discarded as a defective semiconductor chip without going into any further process. Semiconductor chips determined to be non-defective at this stage are separated into individual semiconductor chips by wafer dicing, and the necessary connection pins are connected to each terminal of the semiconductor chip by bonding, and then packaged by molding to form an IC. It is considered to be an element.

The IC element thus formed is aged. If shipped without aging, even if the IC element was determined to be good in the final test, it would still be 100%
If the device is operated for 0 hours, many items will develop initial defects, which is problematic, so it is necessary to age the device in this way before shipping. This aging is
This is done by heating the IC element to a high temperature (125° C.) and applying a DC voltage for about 24 hours. After such aging, a final test is performed, and those that pass the standards are shipped as final products.

Problems to be Solved by the Invention In the above-mentioned IC device manufacturing method, a considerable number of IC devices are found to be defective in the final test after aging, and these defective IC devices are not made into products. It had to be discarded. Even these defective IC elements that are discarded have gone through processes such as bonding connection pins to diced semiconductor chips and packaging them with molds, so it is difficult to discard them. The time, effort, and money spent on this process would have been a complete waste.

Therefore, if a large number of semiconductor chips are arranged on a wafer, aging as described above is performed, and then a test is performed using a combination of a wafer prober and a tester, and only those that are determined to be good are individually diced. It is thought that if the semiconductor chip is made into an IC element by bonding the connection pins and packaging, the above-mentioned waste can be eliminated.

However, there are three types of aging that are currently being performed:

(1) DC aging, in which a semiconductor chip is brought to a high temperature (for example, 125°C) and a DC voltage is applied.

(2) In addition to the DC aging described in (1) above, dynamic aging involves applying pulses to necessary connection pins.

(3) Read from the output pin and monitor (test)
Monitored aging or test aging.

In order to perform such aging on a large number of semiconductor chips arranged on a wafer, it is necessary to apply a necessary DC voltage or pulse to each terminal of each semiconductor chip. If this can be done for each semiconductor chip on a wafer one by one, it can be done and is still done today by connecting the chip terminals to a tester using a conventional device called a wafer prober. However, aging a large number of 200 to 300 semiconductor chips on a wafer one by one in this way takes too much time and effort and is not practical.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method and apparatus for sorting semiconductor chips that can solve the problems of the conventional techniques as described above.

Means for Solving the Problems The method for sorting semiconductor chips according to the present invention performs sorting of semiconductor chips in a wafer state by aging and testing a large number of semiconductor chips arranged on a wafer in parallel. It is characterized by

Further, the semiconductor chip sorting apparatus according to the present invention includes a base for placing a wafer on which semiconductor chips to be sorted are arranged, and a base for placing a wafer placed on the base and having a predetermined elasticity. an elastic conductive member whose portion becomes electrically conductive when subjected to a compressive force; a terminal extraction means comprising a plurality of printed circuit board layers laminated on the elastic conductive member; a pressing means for pressing the terminal extracting means against the wafer; and a connecting means for connecting the terminal extracting means to an aging and testing device, the plurality of printed circuit boards of the terminal extracting means On the surface of the printed circuit board layer closest to the elastic conductive member among the layers, there are conductive protrusions corresponding to each terminal, the number being equal to the total number of terminals of the semiconductor chip that need to be taken out for aging or testing. Each printed circuit board layer has a
A conductive wiring pattern and a through hole are provided, and the wiring pattern and through hole connect each of the terminals of the semiconductor chip to the plurality of terminals via the elastic conductive member and each of the conductive protrusions. It is characterized in that it is arranged so that it can be taken out to the connection means while being dispersed in the printed circuit board layer.

Embodiments Next, the present invention will be described in more detail with reference to embodiments of the present invention based on the accompanying drawings.

FIG. 1 is a schematic diagram showing the configuration of an embodiment of a semiconductor chip sorting apparatus according to the present invention. As shown in FIG. 1, the apparatus of this embodiment has semiconductor chips 11 to be sorted.
．． A base 1 on which wafers 10 arranged with wafers 12, 13, etc. are placed; A conductive rubber sheet 20 as an elastic conductive member that conducts electrically, a terminal extraction means 30 consisting of nine printed circuit board layers 31 to 39 laminated on the conductive rubber sheet 20, and a conductive rubber sheet 20 and Pressing plate 40 for pressing the terminal extraction means 30 against the wafer 10
and an edge connector 50 as a connection means for connecting the terminal extraction means 30 to an aging and testing device (not shown).

On the bottom surface of the lowermost printed circuit board layer 31, conductive protrusions 311 are provided at positions corresponding to each terminal, the number being equal to the total number of terminals of the semiconductor chip that need to be taken out for aging or testing. , each printed circuit board layer is provided with a conductive wiring pattern and through holes, as will be described later.

Next, an example of the arrangement of conductive wiring patterns and through holes provided in each printed circuit board layer will be described.

As partially enlarged in FIG. 2, semiconductor chips 11, 12 and 13, 14 are arranged on a wafer 10.
．． 15, . . . each have a terminal 111 .
121,... are issued. There are, for example, 20 terminals provided on the periphery of each of these semiconductor chips, as shown by terminal numbers 1 to 20 in FIG. There are usually 200 to 300 such semiconductor chips on the wafer 10, and the arrangement interval of each terminal is several inches.
The range is from 0 microns to several hundred microns. On the other hand, according to the semiconductor chip sorting method of the present invention, a large number of semiconductor chips arranged on a wafer are aged in parallel,
By testing, semiconductor chips can be sorted in a very short time and with simple operations. However, in order to perform such parallel aging, it is necessary to simultaneously apply a DC voltage or pulse voltage to each terminal of 200 to 300 semiconductor chips on the wafer 10. And for this purpose, it is necessary to take out each terminal of each semiconductor chip so that it can be connected to aging and testing equipment. It is difficult to erect connection contacts directly to a large number of terminals of semiconductor chips arranged on a wafer IO at narrow intervals of several tens of microns to several hundreds of microns. Therefore, in the embodiment of the sorting device of the present invention shown in FIG. It is arranged so that it can be taken out to the edge connector 50 while being distributed among the nine printed circuit board layers 31 to 39.

That is, since it is not possible to expose all the terminals of the semiconductor chips arranged on the wafer 10 on the negative layer surface, the following method is used.

In FIG. 3, semiconductor chips arranged on a wafer are divided into nine groups, and each semiconductor chip is shown with the number of the group to which it belongs. In FIG. 3, the terminals of the semiconductor chips in the group designated by number 1 are taken out using the printed circuit board layer 31, and the terminals of the semiconductor chips in the group designated by number 2 are taken out using the printed circuit board layer 31. The terminals of the semiconductor chips in the group marked with number 3 are taken out using the printed circuit board layer 33, and the terminals of the semiconductor chips in the group marked with number 4 are taken out using the printed circuit board layer 34. The terminals of the semiconductor chips in the group numbered 5 are taken out using the printed circuit board layer 35, and the terminals of the semiconductor chips in the group numbered 6 are taken out using the printed circuit board layer 36. The terminals of the semiconductor chips in the group designated with number 7 are taken out using the printed circuit board layer 37, and the terminals of the semiconductor chips in the group designated with number 8 are taken out using the printed circuit board layer 38. The terminals of the semiconductor chips in the group indicated by number 9 are taken out using the printed circuit board layer 39.

In the case of DC aging, the conductive wiring pattern and through-holes provided in the printed circuit board layer 31 can be as schematically shown in plan in FIG. 4. In FIG. 4, the semiconductor chips on the wafer below this printed circuit board layer 31 are indicated by two dotted lines. As shown in FIG. 1, conductive protrusions 311 are provided on the lower surface of this printed circuit board layer 31 at positions corresponding to terminals that need to be taken out among the terminals of the semiconductor chips on the wafer 10. , conductive through-holes 312 extending from the positions of these conductive protrusions 311 to the upper surface of the printed circuit board layer 31 are provided, and as shown in FIG. A conductive wiring pattern 313 is provided to interconnect each through hole 312. These wiring patterns 313 terminate at connection terminals 333 provided at the edges of the printed circuit board layer. Similarly, printed circuit board layers 32 to 39 are also provided with through holes and wiring patterns for connecting to terminals from which semiconductor chips of group numbers 2 to 9 need to be taken out. The electrical connections between printed circuit board layers 31 to 39 are
This is done through appropriately placed through holes in each printed circuit board layer. The terminals required to take out all the semiconductor chips on the wafer 10 are the necessary number of connection terminals 333 arranged on the edge of the bottom surface of the bottom printed circuit board layer 31 and the printed circuit board layer 333 on the top layer. It is taken out to the necessary number of connection terminals 393 disposed on the edge portion of the upper surface of the substrate layer 39.

As shown in FIG. 1, the edge connector 50
When fitted, the housing 51 of the edge connector 50
Each corresponding contactor 53 and 54 disposed within contacts each corresponding connection terminal 333 and 393, respectively. Each contact 53 and 5 of the edge connector 50
4 is connected to an electrical cable 52, which connects it to aging and testing equipment.

In the state shown in FIG. 1, when the press plate 40 is pressed downward as indicated by the arrow P, the conductive rubber sheet is The corresponding portions of 20 are elastically compressed, and the portions of the conductive rubber sheet thus elastically compressed with a predetermined compression force of 4 become conductive. Therefore, each corresponding terminal 111 of each semiconductor chip 11, 12, . . . on the wafer 10
．． 121, . . . are connecting terminals 333 through the compressed portion of the conductive rubber sheet 20, the conductive convex portion 311, conductive through holes 312 and wiring patterns 313 appropriately arranged in each of the printed circuit board layers 31 to 39, etc. and 39
It will be electrically connected to 3. By applying an appropriate C voltage for aging from the aging device to the connection terminals 333 and 393 via the electric cable 52 and the edge connector 50, all semiconductor chips on the wafer 10 can be aged in parallel. .

Furthermore, even when aging memory, such as dynamic aging and monitored aging, by appropriately designing the conductive wiring pattern and through-hole arrangement on the printed circuit board layer as described above, it is possible to By connecting the pins in parallel and applying 5 pulses to their terminals, all semiconductor chips can be aced simultaneously.

Furthermore, we also carry out monitored aging while testing.
This can be easily done using a similar method.

Effects of the Invention According to the semiconductor chip sorting method and apparatus of the present invention as described above, various types of aging and monitored aging of semiconductor chips on a wafer can be performed very easily in a short time while the semiconductor chips are on the wafer. Therefore, it is possible to significantly reduce the manufacturing cost of the IC. Furthermore, semiconductor chips that are determined to be defective while still on the wafer are discarded at that point, eliminating waste such as subjecting defective semiconductor chips to processes such as bonding of connection pins and packaging. can be done, so I
The yield of C manufacturing can be further increased, and manufacturing costs can be further reduced.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the configuration of an embodiment of a semiconductor chip sorting device according to the present invention, FIG. 2 is a schematic diagram showing a partially enlarged view of semiconductor chips on a wafer, and FIG. FIG. 4 is a schematic diagram for explaining grouping of semiconductor chips on Ueno\-. FIG. 4 is a schematic plan view showing an example of a printed circuit board layer used in the semiconductor chip sorting apparatus of FIG. 1. 1... Base, 10... Ueno\-11
, 12, 13, 14, 15... semiconductor chip,
20... Conductive rubber sheet, 30... Terminal extraction means, 31-39... Printed board layer, 40...
... Pressing plate, 50 ... Edge connector, 111
．． 1.21131...Terminal, 311...
Conductive convex portion, 312... Through hole, 313... Wiring pattern, 333.393... Connection terminal. 7 This 0th Country Entada En Enku Yen Rolo En Taku En En Ta En Ta En En Exec El [] Tan Enda Prisoner OB No. 4 1 Difficult Yen Prisoner Day Yen Yen Yen Yen En Entrance Mouth EIEIEI E 1 Yen Tayen daily yen daily yen daily mouth map

Claims (2)

[Claims] (1) A semiconductor chip sorting method characterized by sorting semiconductor chips in a wafer state by aging and testing a large number of semiconductor chips arranged on a wafer in parallel. (2) A base for placing a wafer on which semiconductor chips to be sorted are arranged, and a portion of the wafer placed on the base when the wafer is placed on top of the wafer and subjected to a predetermined elastic compressive force. an elastic conductive member that is electrically conductive; a terminal extraction means comprising a plurality of printed circuit board layers laminated on the elastic conduction member; and a terminal extraction means that connects the elastic conduction member and the terminal extraction means to the wafer. and a connecting means for connecting the terminal extracting means to an aging and testing device, and the terminal extracting means is provided with a pressing means for pressing the elastic conductive member among the plurality of printed circuit board layers. On the side of the nearest printed circuit board layer,
A number of conductive protrusions equal to the total number of terminals of the semiconductor chip that need to be taken out for aging or testing are provided at positions corresponding to each terminal, and each printed circuit board layer is provided with a conductive wiring pattern. and a through hole are provided, and the wiring pattern and the through hole distribute each of the terminals of the semiconductor chip to the plurality of printed circuit board layers via the elastic conductive member and each of the conductive convex portions. 1. A semiconductor chip sorting device, wherein the semiconductor chip sorting device is arranged such that it can be taken out to the connecting means while being removed.