JPH0629361A - Wafer-level burn-in for non-mounting die - Google Patents

Abstract

PURPOSE: To improve efficiency of handling and to reduce the necessary size of a testing facility. CONSTITUTION: A reusable burn-in/testing facility for testing not unified dices on a semiconductor wafer 30 comprises a pair of halved bodies 11 and 12. A first half body 11 of the testing facility is a die hollow plate, that accepts the wafer 30, and a second half body 12 establishes electrically conducted states 31 and 23 between the wafer 30 and an electric testing equipment. The opening of the testing facility is not necessary before the completion of the burn in test and an electrical test. Mutual connection is established between the unified dices or the different dices, after a burn-in tension test and an electrical test, and these as unit components or the row of components can be mounted on the inside of separate components, the row or the cluster.

Description

Detailed Description of the Invention

FIELD OF THE INVENTION The present invention relates to electrical test equipment for semiconductor devices. More particularly, the present invention relates to an apparatus and method for performing dynamic burn-in and complete electrical / performance / speed testing on a row of semiconductor dice on a wafer.

2. Description of the Related Art Semiconductor devices are subjected to a series of test methods for the purpose of confirming functionality and yield, and ensuring quality and reliability. This test method conventionally includes a "probe test" in which individual dice are first tested to determine functionality and speed while still on the wafer. A probe card is used to electrically test the die at that level. The electrical connections interface with only one die at a time in the wafer before the dice are singulated from the wafer. If the wafer has a yield of functional dies that indicates that the quality of the functional dies is good, then each individual die is wholly assembled in a package to form a semiconductor device. Conventionally, the package includes a lead frame and a plastic or ceramic housing. The packaged device is then subjected to another series of tests, including burn-in and isolation tests. Isolation testing allows the device to be tested for speed and errors that occur after assembly and after burn-in. Burn-in accelerates the defect mechanism by electrically exciting the device (device under test or DUT) in the elevated temperature, elevated dynamic biasing process. This induces an early fatal defect mechanism as well as a latent defect that is otherwise not apparent at nominal test conditions. By modifying these methods, it is possible to burn-in the device on a circuit arrangement such as a memory board together with the memory board for the purpose of ensuring the reliability of the circuit board and the method of assembling and manufacturing the circuit board as generalized in the device. I can. This closed assembly test assumes that the devices are implemented separately to make this easier. Semiconductor mounting is the "level" of mounting
Was explained by. The chip capsules generally constitute the first level of packaging, the second level is a "card" or printed circuit board, the third level includes the second level packaging combined with the motherboard, and the fourth level is the fourth level. It is the third level. Implementation for all levels in each case is costly.

It has been proposed to implement the device without the use of conventional lead frames. This implementation presents two problems with conventional test methods. The first problem is that separate testing is more difficult because conventional lead frame packaging is not used. Moreover, multiple devices are incorporated into a single package, thus reducing the performance of the package to that of the die with the lowest performance. The reason for this is that the ability to pre-separate individual dies is limited to that obtained in the probe test. A second problem is to have a mounting assembly defect mechanism, which is another limiting content that is exacerbated by the burn-in stress conditions so that the packaging is marginal to the burn-in test. Alan Wood and Chim Corbette, U.S. Pat. No. 4,899,107.
In accordance with the invention represented by the issue, a reusable burn-in / test structure for separate dies is provided. The structure consists of two halves, one half of which is the die cavity plate that receives the semiconductor die as a device under test (DUT) and the other half is the electrical die and burn-in furnace. To establish physical contact. The first half of the test structure contains a cavity in which the die is inserted circuit side up. The die is mounted on a floating platform. The support mechanism below the die platform is the DUT for the exploratory tip on the second half.
It provides a uniform pressure or force that maintains proper electrical contact to the upper die contact. The support mechanism compensates for variations in overall die thickness. The second half has a rigid, high temperature rated substrate on which the corresponding die pad stylet is mounted. Each probe is connected to an electrical trace on a substrate (similar to a PC plate) so that each die pad of each die is electrically isolated from each other for high speed functional testing purposes. is there. The probe tip is planar so that contact with each die pad occurs simultaneously.
The stylet tips are arranged in a row to accommodate eight or more dice. The trace from the stylet terminates in an edge finger to accept a conventional card edge connector. The stylet and edge finger geometries are optimized to avoid electrical test products. The two halves of the test structure are bonded so that each pad on each die aligns with its corresponding electrical contact. The test structure is configured to accommodate groups of 6 or 16 dies for maximum output of the functional test equipment. The test structure is
There is no need to open until the in and electrical tests are complete.
After burn-in stress and electrical testing, the die is removed from the test structure and separated accordingly. Fully burned in and tested dies are available for all types of subsequent assembly applications. Burn-in /
All elements of the test structure are 100% reusable, while allowing individual dice to be tested in a fashion similar to that achieved with separate packaged semiconductor devices. Accelerated burn-in while the die is still on the wafer and the ability to extend to accelerated burn-in and functionality / parametric / speed testing, including functionality, parametric and speed testing, has many advantages. Ah Since each step in the assembly and packaging method is methodologically limited, the ability to determine defects or predict defects in the conventional burn-in step is advantageous. It would be even more advantageous to be able to predict defects during the burn-in stage prior to assembly. Obviously, a high percentage of good parts can be provided with assembly means if a portion is defective before assembly. There are many markets for non-cut manufactured wafers. These wafers are referred to as "probe wafers" because they are delivered after the probe test that continues to manufacture. The purchase of a stylet wafer is a conventional mounting component that includes parts that are traditionally considered "commodity" chips.
SIC assembly factory ”. The purchase of non-cut wafers is usually based on the recent yields of semiconductor manufacturers, but recent yields do not strongly indicate the yield of a given wafer lot.
In addition, the assembly processing technology used in the assembly factory has a significant yield effect. The characterization called "speed grading" is more variable than the yield. Although the mounted DRAM is purchased by the consumer side based on the speed stage of the parts, the speed stage of the probe wafer is almost a speculation issue. This is because the assembly factory has "-10" parts (100n
s) or whether to purchase a wafer of almost "-6" parts (60 ns) means that it is a matter of probability. As a result of recent developments in production technology, such speed characteristics have become more common for a given wafer. Thus, a wafer can be provided in which most good dies are equipped with speed steps that do not significantly exceed the average speed of the wafer. This uniformity, along with fuse repair and patch achievability, makes wafer-scale integration and cluster implementation of arrays practical.
Other developments include the ability to track individual dice on a wafer starting with a probe. Traditionally, the stylus identifies a bad die (eg: ink spot). The assembly method can only be continued for dies that do not have ink spots. Computer tracking makes ink spots unnecessary as good and bad die maps are stored and sent to subsequent assembly stages. Although the dice are singulated, separate parts may be reassembled into the array after assembly.
One example is in computer memory,
In this case, one or more memory banks are organized in rows of memory chips. It would be advantageous to be able to select good dies on a wafer and assemble the dies into an array without singulating the dies. This would allow a dense array of well-assembled dice on a single piece of silicon. It is an object of the present invention to increase handling efficiency and reduce the required size of test structures.

SUMMARY OF THE INVENTION In accordance with the present invention, burn-in and testing is performed on non-cut wafers by placing the wafer in a reusable burn-in / test structure. Contact pads are provided on the test structure to establish electrical contact to the individual dice on the wafer. This structure consists of two halves,
One of the halves is a wafer cavity plate that receives the wafer as a device under test (DUT) and the other half establishes electrical contact with the wafer and the burn-in furnace. The first half of the test structure contains a cavity into which the wafer is inserted. The wafer is placed in the cavity and the platform on the second half applies pressure to the half of the stationary structure that establishes electrical contact. In the preferred embodiment, the support mechanism below the platform provides the probe tip on the second half with a constant and uniform pressure or force that maintains proper electrical contact to the die contacts on the DUT. The support mechanism can include pneumatic-mechanical, elastomeric or any other suitable biasing mechanism. The stylet tip is an electrical contact point where electrical contact is established by a fixture. These chips can be ridges on the wafer, raised electrical ridges, or flat contact areas that mate with elastic fingers. The wafer substrate can use either flat bond pads or raised raised contacts. According to one embodiment, a TAB interconnect circuit is used for the electrical contact points. After burn-in, the TAB interconnect can be retained on the completion circuit or the TAB interconnect can be removed after testing. If the TAB interconnect circuitry is retained, the final interconnect of the wafer will be modified as needed for testing. The second half has a rigid, high temperature rated substrate on which is placed electrically conductive electrical contacts or pads for each corresponding die on the wafer.
Each contact (eg probe) is an electrical trace on a substrate so that each die pad of each die is electrically isolated from each other (similar to a PC board) for high speed functional test purposes. It is connected. The stylet tip is planar so that contact with each die pad occurs simultaneously. The trace from the stylet terminates in an edge finger to accept a conventional card edge connector. The stylet and edge finger geometries have been optimized to eliminate electrical testing personnel. The two halves of the test structure are connected so that each pad of each die on the wafer is aligned with a corresponding electrical contact chip. Burn
The test structure does not need to be opened until the in and electrical tests are complete. After burn-in stress and electrical testing, the wafer is removed from the test structure and singulated or interconnected as desired. Fully burned-in and tested die wafers are available for a variety of end uses that next require semiconductors with high yield and high reliability. The resulting dice are applicable for any type of subsequent assembly / implementation application. In configurations where wafer scale integration is used, the circuits connect the dice according to the circuit row protocol, and these circuits are selectively cut to provide the functional rows. Functional clusters or rows for functionality and speed (good dice)
Once is tested and burned in, these columns are then diced accordingly. The diced clusters or rows of dies can then be densely packaged using various interconnection techniques such as wire bonds, ribbons, TABs, tapes or conductive elastomers. While this technique makes most or all of the components of the burn-in / test structure 100% reusable, it achieves each die with a separate packaged semiconductor device while on the wafer. It can be done in a similar fashion. The present invention also enhances handling efficiency and reduces the required size of the test structure by performing functional testing and burn-in at the wafer level.

1 and 2, the burn-in structure of the present invention includes a first plate 11 for a wafer cavity shown in FIG. 1 and a second plate as a support plate shown in FIG. 12 are included. First for wafer cavity
Plate 11 includes a wafer receiving cavity 17, which is sized to receive a semiconductor wafer. The first plate 11 as a wafer cavity plate includes a main plate portion 21 from which a plurality of edge portions for electrical connection terminals 23 extend. Other devices can be used for electrical communication instead of the connection terminals 23 at the edge. The first plate 11, which is the plate for the wafer cavity, is aligned with the second plate 12, which is the support plate, so that the bottom surface 25 of the main plate portion 21 is aligned with the wafer receiving cavity 17 on the first plate 11, the wafer cavity plate. Alignment devices such as dowels 27 and dowel receiving cavities 28 are used to establish alignment between the second plate 12, which is a support plate, and the first plate 11, which is a wafer cavity plate. The alignment of the first plate 11 and the second plate 12 is shown in FIG. 3, in which the wafer 30 is shown between both plates 11, 12. In the preferred embodiment, the stylet plate is made on a rigid substrate and has a conductive pattern therein. The conductive pattern terminates in (for example) a conductive ridge or pad. A form of TAB technology can be used to connect the wafer to external circuitry. (This external circuit can be any circuit connected to the wafer 30, which is typically test equipment or burn-in equipment.) The particular TAB technology used is the technique of temporarily attaching the wafer contact pads to the TAB circuit. Is. The TAB circuit is temporarily bonded for the purpose of providing burn-in and test capability, but
It can be removed continuously following the test and test method. Wafer 3
T so that the die on 0 can be connected to an external circuit
The AB circuit is connected to the connection terminal 23 which is an edge connector.
The TAB circuit can then be modified to compensate for the test results or removed from the wafer 30. Since the wafer 30 is tested before being divided into individual dice, the wafer 30
Interconnects can be provided between the top dies. This will facilitate connection to each die somewhat without the need to establish contact pin locations for each individual die. memory·
In the case of a chip, the method of manufacturing the chip includes providing an address circuit, so that the address circuit can be easily provided on the wafer 30. A circuit of similar type could easily be produced simultaneously, except that this particular circuit would address the dice rather than parts of the die. The "on-board" driver circuit helps to simplify the need for redundant I / O lines and can be abandoned if it is not suitable for end use applications. The second plate 12, which is a support plate, includes a bias platform 41, which is a floating platform supported by a bias platform 43, which is a bias mechanism. The wafer 30 is held in place within the wafer receiving cavity 17 by a floating platform 41. In the illustrated embodiment, the biasing mechanism 43 is an elastomeric polymer but coil springs can be used. The purpose of the biasing mechanism 43 is to bias the floating platform 41 upward so that the wafer 30 contacts the contact 31, which is a stylet tip, when the wafer 30 is inserted into the wafer receiving cavity 17 and the fixture is assembled. Bias mechanism 4
The biasing force of 3 and the movement of the floating platform 41 should be sufficiently uniform so that when the wafer receiving cavity 17 receives the wafer and the second plate 12, which is the supporting plate, is installed on the first plate 11, which is the wafer cavity plate, The chip 31 must be moved sufficiently to contact each die pad. As a result of the uniformity of movement and biasing, the combination of the first plate 11, which is the wafer cavity plate, and the second plate 12, which is the support plate, is sufficient to cause each probe tip contact 31 to contact its respective die pad. It is only necessary to compensate for the need to evenly bias the wafer 30 with respect to the contact chips 31. This is dowel 27 and dowel receiving cavity 2
Lateral alignment as established at 8 with the second plate, which is the support plate, against the first plate, which is the wafer cavity plate 11.
It is more important than the exact closeness of the plate 12. In the illustrated example, a large number of edge connection terminals 2
3, each edge connection terminal 23 is in optimum proximity with the end 51 of the wafer receiving cavity 17. Since the die pad is normally located at the end 51, the edge connecting terminal 23 is in close proximity to the die pad and thus the circuit length between the die pad and the edge connecting terminal 23 is very short. Become. Of course, less or more edge connection terminals 23 can be provided, as is conventional from design considerations. Since there are multiple contacts on each semiconductor die, multiple edge connection terminals 23 will be provided. The address circuit can be used to reduce the number of external connection terminals otherwise required for the purpose of performing a complete test of the circuit of the wafer 30. In this way, the entire wafer can be tested with a small number of connections. An example of a suitable address circuit would be the address and self-test circuit arrangement used on a computer memory board. The assembled structure is applied in conventional test equipment such as a burn-in furnace. In the case of a burn-in furnace, it is desired to connect the edge connector to the burn-in circuit, where a common connector is used for many devices. In any case, connection terminals 23, which are edge connectors, can be used to connect the die in the test structure to separate existing equipment (not shown). In the alternative embodiment shown in FIG. 4, the bottom surface 61 of the support plate 12 ′ is shown.
Has a number of contact tips 31 'extending therefrom. Contact chip 31 'is sufficiently flexible to compensate for die pad height variations. The contact tips 31 'are aligned with the wafer receiving cavities 17' in such a manner that the contact tips 31 'are in electrical communication with the individual contact pads on the die when the wafer is positioned within the wafer receiving portion 17'. is doing. An elastomeric mat 63 can be disposed between the wafer 30 and the support plate 12 '.
The elastomeric mat 63 will operate in a pattern corresponding to the conductive ridges or pads on the contact area of the wafer 30 to provide positive electrical contact between the support plate 12 'and the wafer 30. In an alternative embodiment, the main plate portion 21 'of the support plate 12' includes a series of circuit traces (not shown). This circuit trace communicates with the individual contacts for the edge connector 23 '. This allows the edge connector 23 'to be used to connect the contact pads on the die to the test structure configuration.

[Brief description of drawings]

FIG. 1 illustrates a wafer cavity plate of the present invention.

2 shows a support plate used in connection with the wafer cavity plate of FIG.

FIG. 3 is a view showing an aligned state of the plates of FIGS. 1 and 2.

FIG. 4 shows an alternative embodiment of the invention in which the probe contacts are located on the support plate.

[Explanation of symbols]

 11 First Plate 12 Second Plate 12 'Support Plate 17 Wafer Receiving Cavity 17' Wafer Receiving Cavity 21 Main Plate 21 'Main Plate 23 Connection Terminal 23' Edge Connector 25 Bottom 27 Aligning Means (Dowel) 28 Aligning Means (Dowel) Receiving cavity) 30 Wafer 31 Contact 31 'Contact chip 41 Bias platform 43 Bias platform 51 End 61 Bottom 63 Elastomeric mat

 ─────────────────────────────────────────────────── --Continued Front Page (72) Inventor Tim J. Corbett, Hidden Valley Rim Road, Boyes, 83709 Idaho, USA 11629

Claims (8)

[Claims] 1. A plurality of semiconductors made in the form of dies from a wafer (30) while the dies remain on the wafer to perform electrical testing in a manner similar to that performed in discretely mounted semiconductor devices. A wafer level testing device for testing the device, comprising: a) a first plate (11); b) a wafer receiving cavity (17) in the first plate; and c) a second plate (12) mating with the first plate. D) aligning means (27, 28) for aligning the first plate with the second plate; and e) a plurality of wafer contact conductive members extending from one of the first plate and the second plate. A body is provided, the wafer contact conductor extending to the contact (31) to achieve electrical communication with a contact location on the wafer; f) aligning the first plate and the second plate. The wafer contact conductors are positioned so that the contacts are aligned with the contact points on the wafer when aligned by the mating means and the wafer is positioned in the wafer receiving cavity; g) in electrical communication with the wafer contact conductors. A wafer level test apparatus comprising a connection terminal (23) and the connection terminal provided on one of the plates. 2. A wafer level tester for testing a plurality of semiconductor devices in die form to perform electrical testing in a manner similar to that performed on a discretely mounted semiconductor device, comprising: a) first plate (11). ) And b) a wafer receiving cavity (17) in the first plate; and c) a second plate (1) in combination with the first plate.
2) and; d) alignment means (27, 28) for aligning the first plate with the second plate; and e) one of the first plate and the second plate is provided with a plurality of wafer contact conductors. The conductor terminates in a plurality of contact pins (31); f) the contact pins are on the wafer when the first plate and the second plate are aligned by alignment means and the wafer is positioned in the wafer receiving cavity. Conductors are positioned on the plate having a plurality of wafer contact conductors to align with the contact points; g) connection terminals in electrical communication with contact pins (2
3), the connection terminals are mounted on the plate having a plurality of wafer contact conductors; and h) the wafer receiving cavity has a bias platform therein and a plurality of wafer contact conductors. A wafer level tester consisting of a biasing platform (41, 43) applying to the wafer a biasing force sufficiently uniform to bring the individual contact pins on the plate into contact with the wafer. 3. The wafer contact conductor further comprises: a plurality of contact pads aligned with the wafer receiving cavity after the first plate and the second plate are combined, the alignment comprising a pattern of contact locations on the wafer. The wafer level test apparatus according to claim 1 or 2, which corresponds to the above. 4. The wafer contact conductor further comprises: an elastomeric conductor extending into the wafer receiving cavity after the first plate and the second plate are combined.
Alternatively, the wafer level test apparatus according to claim 2. 5. A method of testing a wafer level array of a plurality of semiconductor devices in the form of a die on a wafer (30) in a manner similar to that achieved in a separately mounted semiconductor device: a) providing a semiconductor wafer (30) having a plurality of semiconductor dice thereon and having electrical contact locations; b) providing a first plate (11) and a second plate (12); A plurality of wafer contact conductors (31) from which one of the plate and the second plate extends
C) placing the wafer in a wafer receiving cavity (17) in the first plate; d) aligning the first plate and the second plate; e) electrical contact locations on the wafer and a plurality. Establishing an electrical contact between the individual wafer contact conductors; f) contact pins on the wafer when the first plate and the second plate are aligned by alignment means and the wafer is positioned in the wafer receiving cavity. The wafer contact conductors are positioned to align with; and g) electrical communication with the wafer contact conductors is provided at the contact terminals (2).
The test method provided in 3), wherein the contact terminal is provided on one of the plates. 6. A wafer substrate on which a wafer-level semiconductor array is formed, which is a semiconductor circuit array device that is composed of a plurality of substantially similar semiconductor dice and is substantially complete when each die is unified. A method of manufacturing a wafer-level semiconductor array comprising a plurality of unsingulated dies mounted together on a material, comprising: a) having a plurality of semiconductor dice on top of electrical contact locations. B) providing a first plate (11) and a second plate (12), a plurality of one of the first plate and the second plate extending therefrom. Wafer contact conductor (31)
C) placing the wafer in the wafer receiving cavity (17) in the first plate; d) aligning the first plate with the second plate; e) electrical contact locations on the wafer and a plurality. Establishing an electrical contact between the individual wafer contact conductors; f) contact pins on the wafer when the first plate and the second plate are aligned by alignment means and the wafer is positioned in the wafer receiving cavity. Positioning the wafer contact conductors to align with; g) connecting terminals (27) in electrical communication with the wafer contact conductors, the connecting terminals being located on one of the plates; h) wafer Testing the dice on the wafer in the receiving cavity, said testing being performed in a manner similar to that achieved in a discrete mount semiconductor device; i) a wafer. Determining the locations of the functional parts of the h; and j) selecting the dice to be interconnected. 7. The method further comprises: a) providing electrically conductive interconnects on the wafer for interconnecting dice on the wafer; b) determining the location of functional portions of the wafer; and providing functional arrays. 7. A method according to claim 5 or claim 6 comprising selectively disabling the interconnects. 8. The method further comprising: a) determining the location of functional portions of the wafer; b) selectively providing conductive interconnects on the wafer for interconnecting dice on the wafer. The method according to claim 5 or claim 6.