JPH07231021A - Wafer burn-in apparatus - Google Patents

Abstract

PURPOSE:To make it possible to connect all of array pads of an IC wafer to an external apparatus by an interconnecting wafer by forming an electric wiring circuit with an intermediate connecting pad and an external apparatus connecting pad at the position corresponding to the array pads of each semiconductor chip for the intermediate connecting wafer. CONSTITUTION:For an wafer burn-in apparatus 100, an intermediate connecting wafer 40 is superimposed on an ultra-high density, anisotropic, conductive film 30. An intermediate connecting wafer 40 is formed with the same material as IC wafer 1 and matched to the coefficient of thermal expansion of the IC wafer 1. On one surface of the intermediate connecting wafer 40, intermediate connecting pads 43 and a required number of external apparatus connecting pads 44 are formed along the outer periphery with an increased diameter at the position corresponding to respective array pads 2 of the IC wafer 1. And also electric wiring circuits 41 and 42 connected between the intermediate connecting pads 43 and external apparatus connecting pads 44 are formed inside the intermediate connecting wafer 40.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer burn-in device used when an IC wafer having a large number of semiconductor chips is subjected to aging or testing.

[0002]

2. Description of the Related Art In the manufacture of memory devices such as semiconductor chips and IC devices such as LSI locks, a large number of semiconductor chips are diced and packaged through various steps such as photoprinting and etching on silicon called a wafer. Etc. are manufactured. At present, 200 to 300 semiconductor chips are arranged on a wafer. In a general manufacturing process, the finished wafer is tested one by one with a combination of a wafer prober and a tester, and the semiconductor chips that are out of the standard at this stage are marked with ink and defective. Therefore, it was discarded as the defective semiconductor chip without entering the subsequent steps. The semiconductor chips that are judged to be good products at this stage are separated into semiconductor chips one by one by dicing the wafer, and the necessary connection pins are connected to each terminal of the semiconductor chip by bonding and packaged by post-molding to form an IC. It is regarded as an element.

The IC element thus formed is aged. If it is shipped without aging, even if it is judged as a non-defective product in the final test, there will be many problems that will cause initial failure after operating for about 1000 hours. It needs to be aged before. This aging is performed by a method in which the IC element is kept in a high temperature state (125 ° C.) and a DC voltage is applied for about 100 hours. After such aging, a final test is performed, and products that pass the standard are shipped as final products.

In the method of manufacturing an IC element as described above,
A considerable number of defective IC elements were found in the final test after aging, and these defective IC elements had to be discarded without being regarded as products. Even these defective IC elements that have been discarded have undergone the process of bonding the connecting pins to the diced semiconductor chip and packaging by molding. The time, labor, and money spent in such a process would be completely wasted.

Therefore, if a large number of semiconductor chips are arrayed on a wafer, the aging as described above is performed, and then the wafer is tested with a combination of a wafer prober and a tester. If the individual semiconductor chips are bonded by dicing and the connecting pins are bonded and packaged to form the IC element, the waste as described above can be eliminated.

However, in order to perform such aging on a large number of semiconductor chips arranged on a wafer, it is necessary to apply a necessary DC voltage or pulse to each terminal of each semiconductor chip. If it suffices to do this one by one for each semiconductor chip on the wafer, it is possible by connecting the chip terminal and the tester with a device called a conventional wafer prober, and it is still being done. However, 200 to 300 on the wafer
Aging a large number of semiconductor chips, one by one, in this way is too time-consuming and impractical.

[0007]

Therefore, a so-called wafer burn-in system has been developed which is capable of simultaneously aging a large number of semiconductor chips arranged on a wafer and performing monitored aging while testing. It is starting. According to these conventional wafer burn-in devices that have been developed, various aging and monitored aging of semiconductor chips on a wafer can be performed very easily in a short time while being on the wafer. It is possible to significantly reduce the manufacturing cost. In addition, since it is possible to eliminate waste such as subjecting a semiconductor chip, which is defective on the wafer, to the process of bonding and packaging the connection pins, it is possible to reduce the yield of IC manufacturing. The cost can be further reduced.

However, the wafer burn-in apparatus which has been developed so far has a large number of semiconductor chip array pads (terminals) distributed on a wafer by using a plurality of printed circuit board layers for aging and testing. That is, the device configuration was very complicated, such as taking it out.

As the number of semiconductor chips arrayed on a wafer increases, the number of array pads to be taken out also increases, and the number of printed circuit boards required also increases, so that alignment between them becomes difficult. There will be problems such as becoming. In addition, since the arrangement density of contact terminals that can be formed on a printed circuit board is limited, ICs to be aged
There was also a problem that it could not be handled depending on the array density of array pads on the wafer.

An object of the present invention is to provide a wafer burn-in system which can solve the above-mentioned problems of the prior art.

[0011]

A wafer burn-in system according to the present invention comprises a base for mounting an IC wafer on which a large number of semiconductor chips are arranged, and a periphery of the IC wafer mounted on the base. A container having an inner wall surrounding it, an ultra-high density anisotropic conductive film overlaid on the IC wafer mounted on the base in the inner wall of the container, and the ultra-high density anisotropic conductive film A wafer for intermediate connection which is overlaid on the substrate, and a holding means which is bonded to the container and presses the ultra-high density anisotropic conductive film and the wafer for intermediate connection onto the IC wafer on the base. The intermediate connection wafer includes an intermediate connection pad formed at a position corresponding to an array pad of each semiconductor chip provided on the IC wafer, A pad for device connection, and an electrical wiring circuit between the pad for intermediate connection and the pad for external device connection, wherein the wafer for intermediate connection is in the ultra high density on the inner wall of the container. When stacked on the anisotropic conductive film, a terminal portion is formed which is in contact with each of the external device connecting pads of the intermediate connecting wafer, and the container is provided with each of the terminal portions. It is characterized in that a connecting means for electrically connecting to the device is provided.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a schematic sectional view showing the structure of a wafer burn-in system as an embodiment of the present invention. Figure 1
As shown in, the wafer burn-in apparatus 100 of this embodiment includes a base 10 made of marble, metal, or the like. On the upper surface of the base 10, there is formed a positioning annular projection 11 having an inner diameter slightly larger than the outer diameter of the IC wafer 1 which is the wafer to be measured. The surface of the base 10 on the inner side of the positioning annular projection 11 is preferably a hard and flat surface having high flatness. This is necessary in order to keep the IC wafer 1 placed on it highly flat. On the side of the base 10 on which the IC wafer 1 is mounted, for example, some holes or grooves are formed, and the IC wafer 1 can be held in close contact therewith by utilizing aerodynamic force. Although not shown in FIG. 1, it is also possible to embed a heating heater in the base 10 and supply the electric power to the heating heater to heat the IC wafer 1. In this case, In addition, the base 10 constitutes a so-called heat sizing plate.

The IC wafer 1 to be mounted on the surface of the annular positioning protrusion 11 of the base 10 is a circular silicon wafer in which a large number of semiconductor chips are arranged and formed as usual. Arrangement pad 2 which is the terminal portion of the circuit element
Are formed on one side. These IC wafers 1
Are placed on the base 10 with the array pad 2 facing upward.

Wafer burn-in system 10 of this embodiment
0 comprises a container 20 which is joined onto the base 10. The container 20 is made of an insulating material and is formed into a disc shape or a cylindrical shape as a whole, and has an inner wall surrounding the IC wafer 1 mounted on the base 10.
An inner wall shoulder 21 is formed in the middle of the inner wall of the container 20, and a threaded portion 22 is formed on the upper part of the inner wall of the container 20. Furthermore, a large number of terminal portions 23 having the functions described below are provided on the inner wall shoulder portion 21 of the container 20, and external devices such as an aging device and a testing device are provided on the outer peripheral portion of the container 20. An electrical connector 24 is provided for making an electrical connection with. Each terminal portion 23 and each corresponding contact terminal of the electric connector 24 are connected to each other by an electric lead wire 25 that is wired through the inside of the wall of the container 20.

Further, the wafer burn-in apparatus 100 of this embodiment is provided with an ultra high density anisotropic conductive film 30 which is superposed on the IC wafer 1 placed on the base 10 in the inner wall of the container 20. There is. This ultra-high density anisotropic conductive film 30 is disclosed, for example, in “Nitto Giho, Vol. 30, N.
o.1 (May. 1992) ", pages 45 to 47. As shown in the partially enlarged cross-sectional view of FIG. 2, this film is formed by forming fine through holes in a polyimide film 31 having excellent electrical insulation and filling the holes with metal columns 32. The pillars 32 are formed into bumps 33 and 34 on both front and back surfaces of the film to form an ultra-high density anisotropic conductive film having electrical conduction only in the thickness direction of the film 31.

Such an ultra-high density anisotropic conductive film 3
No. 0 has high reliability and high dimensional stability because it is composed only of a polyimide film and a metal column.
And 34 can be arranged on the order of several tens of μm pitch, so that even if the arrangement density of the arrangement pads arranged on the IC wafer becomes considerably high, selective electrical contact to each of the arrangement pads can be made with sufficient resolution. You can do it.

Although the ultra high density anisotropic conductive film having such a structure can be used as it is, in this embodiment, it is processed into a shape as shown in FIGS. 3 and 4. I'm using it. That is, as shown in FIG. 3, the bumps 33 in the portions corresponding to the array pads 2 of the IC wafer 1 are left, and the other bumps 33 are etched off and removed, as indicated by reference numeral A. The ultra-high density anisotropic conductive film 30 is relatively hard and less flexible as a whole, but the height of the bump 33 is 1
Since the thickness is about 0 μm, it is possible to absorb whether or not the array pad 2 of the IC wafer 1 has a thickness (height) of about several μm. Figure 4
Is an ultra-high density anisotropic conductive film 3 treated in this way
The contact state between the bumps 33 of 0 and the array pads 2 of the IC wafer 1 is illustrated. As can be seen from FIG. 4, the portions where the bumps 33 are etched off have no electrical continuity, and the unevenness can be absorbed without difficulty.

Further, the wafer burn-in apparatus 100 of this embodiment is provided with a wafer 40 for intermediate connection which is superposed on the ultra high density anisotropic conductive film 30. The intermediate connecting wafer 40 is formed of the same material as the IC wafer 1 so as to match the thermal expansion coefficient of the IC wafer 1. This intermediate connecting wafer 40 has the array pad 2 of the IC wafer 1 and the ultra high density anisotropic conductive film 30.
It is to be taken out to the outside through the through-hole and is formed in the same manner as the IC wafer 1, but its diameter is slightly increased. On one surface of the intermediate connecting wafer 40, I
An intermediate connecting pad 43 and a required number of external device connecting pads 44 are formed along the outer periphery of the enlarged diameter at positions corresponding to the respective array pads 2 of the C wafer 1. Inside the wafer 40, electric wiring circuits 41 and 42 connected between the intermediate connection pad 43 and the external device connection pad 44 are formed.

FIG. 5 is a circuit block diagram showing in detail a part of the intermediate connection pad 43, the external device connection pad 44, and the electric wiring circuits 41 and 42 formed on the intermediate connection wafer 40. . As shown in FIG. 5, the electric wiring circuit is necessary to perform aging and testing of the IC wafer 1, and the IC circuit 41.
Is a multiplexer or PLA for selecting some of the semiconductor chips of a plurality of connectors arranged on the IC wafer 1, and the wiring 42 is a power supply line, G
Some lines, such as ND lines and signal lines, are connected to a common line. In addition, a resistance R
Is also connected.

Furthermore, the wafer burn-in apparatus 100 of this embodiment is overlaid on the intermediate connecting wafer 40 and holds the intermediate connecting wafer 40 so as to maintain the flat state thereof. 50 and the first pressing plate 50 are superposed on the first holding plate 50 and fixedly coupled to each other via the container 20 so that the ultra-high density anisotropic conductive film 30 and the intermediate connecting wafer 40 are attached to the IC wafer 1.
And a second pressing plate 60 for pressing the first pressing plate 50. In this embodiment, the first holding plate 50 is made of a flat metal plate, and the second holding plate 60 is also made of a flat metal plate.
A threaded portion 61 that engages with the threaded portion 22 of the container 20 is formed on the periphery.

Next, an assembling method for using the wafer burn-in apparatus 100 having the above-mentioned structure will be described. First, the IC wafer 1 is placed in the positioning annular projection 11 of the base 10, and then the IC wafer 1 is placed.
A super high density anisotropic conductive film 30 is placed on top of the above.
In this case, the alignment with the IC wafer 1 is performed with reference to a predetermined mark or the like.

On the other hand, the intermediate connection wafer 40 is placed in the container 20.
Put. At this time, the external device connection pads 44 arranged on the outer periphery of the intermediate connection wafer 40 and the terminal parts 23 arranged on the inner wall shoulder 21 of the container 20 corresponding to each other are in contact with each other. Align in the same manner as above. Further, the first holding plate 50 is overlaid on the intermediate connecting wafer 40, and the second holding plate 60 is screwed into the threaded portion 22 of the container 20.
The holding plate 50 is temporarily fixed to the container 20.

Finally, the container 20 in which the wafer 40 for intermediate connection, the first holding plate 50 and the second holding plate 60 are assembled in the temporarily fixed state in this way is used as the IC wafer 1 and the ultra high density anisotropic conductive material. Base 10 on which the flexible film 30 is placed
The second presser plate 6
By further screwing 0 into the threaded portion 22 of the container 20,
Make the final fixation. Then, a corresponding lead wire of an external device required for aging or testing is connected to the connector 24 arranged on the outer periphery of the container 20.

In this state, each array pad 2 of the IC wafer 1 is connected to each corresponding intermediate connection of the intermediate connection wafer 40 through each corresponding conductive metal pillar 32 of the ultra high density anisotropic conductive film 30. The pad 43 is connected to the corresponding electric wiring circuits 41 and 42, and further, the corresponding terminal device 23 of the container 20 is connected to the external device through the connector 24 through the corresponding external device connecting pad 44. Of.

In the above-mentioned embodiment, the ultra-high density anisotropic conductive film 30 is used for the connection between the IC wafer 1 and the intermediate connection wafer 40. The density is not limited to the anisotropic conductive film, and conductive rubber or the like having the same super-high density anisotropic conductivity can be used instead. Further, although it has been described that the intermediate connection wafer 40 is formed of the same material as the IC wafer 1 by the same IC manufacturing method,
The present invention is not limited to this, and the intermediate connection wafer is an IC
Other materials may be used as long as the material has a coefficient of thermal expansion substantially the same as that of the wafer 1.

[0027]

According to the wafer burn-in system of the present invention,
Since all the array pads of the IC wafer 1 can be connected to the external device by the single wafer for intermediate connection, the structure can be made very simple and inexpensive. Further, even if the arrangement density of the arrangement pads of the IC wafer becomes high, it is possible to cope with the arrangement density, and the alignment work between each pad and the terminal portion becomes easy.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing the structure of a wafer burn-in system as one embodiment of the present invention.

2 is a partially enlarged cross-sectional view showing a state structure of an ultra-high density anisotropic conductive film used for the wafer burn-in apparatus of FIG. 1 before processing.

FIG. 3 is a partially enlarged cross-sectional view showing a state of the ultra-high density anisotropic conductive film of FIG. 1 after processing.

4 is a partially enlarged cross-sectional view showing a contact state between an ultra-high density anisotropic conductive film and an IC wafer in the wafer burn-in system of FIG.

5 is a circuit block diagram showing details of a portion of an intermediate connection pad, an external device connection pad, and an electric wiring circuit formed on the intermediate connection wafer of the wafer burn-in system of FIG.

[Explanation of symbols]

 1 IC Wafer 2 Array Pad 10 Base 11 Positioning Annular Projection 20 Container 21 Inner Wall Shoulder 22 Screw Part 23 Terminal Part 24 Connector 25 Electrical Lead Wire 30 Ultra High Density Anisotropic Conductive Film 31 Polyimide Film 32 Metal Pillar 40 Intermediate Connection wafer 41 IC circuit 42 Electric wiring 43 Intermediate connection pad 44 External device connection pad 50 First pressing plate 60 Second pressing plate 61 Screw part

Claims (4)

[Claims] 1. A base for mounting an IC wafer on which a large number of semiconductor chips are arranged, and an I mounted on the base.
A container having an inner wall surrounding the C wafer, and the I mounted on the base in the inner wall of the container.
C ultra-high density anisotropic conductive film overlaid on the wafer, intermediate connection wafer overlaid on the ultra-high density anisotropic conductive film, and the ultra-high density anisotropic film bonded to the container. A conductive film and a pressing means for pressing the intermediate connection wafer against the IC wafer on the base, the intermediate connection wafer being an array of semiconductor chips provided on the IC wafer. An intermediate connection pad formed at a position corresponding to each pad, an external device connection pad, and an electric wiring circuit between the intermediate connection pad and the external device connection pad, When the wafer for intermediate connection is stacked on the ultra-high density anisotropic conductive film, the pad for external device connection of the intermediate connection wafer is formed on the inner wall of the container. A wafer burn-in apparatus, characterized in that terminal portions are formed in contact with each other, and the container is provided with connecting means for electrically connecting each of the terminal portions to an external device. . 2. The wafer burn-in apparatus according to claim 1, wherein the intermediate connection wafer is formed of a material having a thermal expansion coefficient substantially the same as that of the IC wafer. 3. The intermediate connection wafer is formed of the same material as the IC wafer, and the intermediate connection pad, the external device connection pad and the electric wiring circuit are arranged on a semiconductor chip and an array of the IC wafer. The wafer burn-in apparatus according to claim 1, wherein the wafer burn-in apparatus is formed by the same manufacturing method as the pad. 4. The wafer burn-in apparatus according to claim 1, 2 or 3, wherein a surface of the base on which the IC wafer is mounted is hard and flat, and a heater is provided on the base. .