JPH0335833B2 - - Google Patents
Info
- Publication number
- JPH0335833B2 JPH0335833B2 JP56202288A JP20228881A JPH0335833B2 JP H0335833 B2 JPH0335833 B2 JP H0335833B2 JP 56202288 A JP56202288 A JP 56202288A JP 20228881 A JP20228881 A JP 20228881A JP H0335833 B2 JPH0335833 B2 JP H0335833B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon film
- film
- region
- substrate
- island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 16
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- 230000010354 integration Effects 0.000 description 4
- 238000010894 electron beam technology Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は半導体装置の製造方法のうち、特に新
規な単結晶シリコン領域の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to a novel method for forming a single crystal silicon region.
(2) 技術の背景
IC、LSIなどの半導体装置は、高集積化させる
ため、半導体製造の各プロセスにおいて、それぞ
れ鋭意検討が行われて、その成果が例えば高集積
メモリ素子などに現われていることは周知のとお
りである。半導体装置は高集積化されると、機能
の高速化、消費電力の減少、機器の小型化をはじ
めとして、信頼性の向上など多くの利点が生じ、
電子機器の発展に大きく役立つため、これは当然
のことと言える。(2) Background of technology In order to increase the degree of integration of semiconductor devices such as ICs and LSIs, intensive research has been carried out in each semiconductor manufacturing process, and the results of these efforts are appearing in, for example, highly integrated memory elements. As is well known. When semiconductor devices become highly integrated, they have many advantages, including faster functions, lower power consumption, smaller equipment, and improved reliability.
This is natural since it greatly helps the development of electronic devices.
(3) 従来技術と問題点
しかしながら、従来の半導体装置は、通常シリ
コン（Si）単結晶からなる基板面を、例えばリソ
グラフイ技術などの精密加工処理技術により微細
な半導体素子に形成せしめているが、一般に１つ
の平面上に多数の半導体素子を高密度に形成する
製法であるから、その高密度化、高集積化にも自
ら限度がある。(3) Conventional technology and problems However, in conventional semiconductor devices, fine semiconductor elements are formed on a substrate surface usually made of single crystal silicon (Si) using precision processing techniques such as lithography. Since this is generally a manufacturing method in which a large number of semiconductor elements are formed at high density on one plane, there is a limit to how high the density and integration can be achieved.
(4) 発明の目的
したがつて、本発明はこのような平面上に半導
体素子を形成するだけの製造方法、即ち二次元的
な構造方法から更に前進させた立体的（三次元
的）な製造方法を提案するもので、かくすること
によつて更に集積度を向上させることができ、既
にSOI（Si On Insulator）として注目されている
立体構造の１つの具体的な製法である。(4) Purpose of the invention Therefore, the present invention is a manufacturing method that only forms semiconductor elements on such a plane, that is, a three-dimensional (three-dimensional) manufacturing method that is further advanced from a two-dimensional structure method. This paper proposes a method that can further improve the degree of integration, and is one specific method for producing a three-dimensional structure that is already attracting attention as SOI (Si On Insulator).
(5) 発明の構成
本発明の半導体装置の製造方法は、シリコン基
板に低熱伝導性絶縁膜からなる島状領域を選択的
に形成した後、該基板の表面及び島状領域の表面
に多結晶シリコン膜を披着する工程と、該基板の
表面に形成されている多結晶シリコン膜と該島状
領域の表面に形成されている多結晶シリコン膜と
にビームアニールを施して、上記基板表面の多結
晶シリコン膜を残し、島状領域上の多結晶シリコ
ン膜のみを選択的に溶融してこれを多結晶シリコ
ン膜となす工程と、次いで該基板の熱酸化により
前記単結晶シリコン膜の表面、並びに前記基板表
面の多結晶シリコン膜の全部を同時に酸化してシ
リコン酸化膜を形成する工程と、該シリコン酸化
膜をほぼ均一な厚さで除去して前記島状領域上の
単結晶シリコン膜を表出する工程とを含むことを
特徴とする。(5) Structure of the Invention In the method for manufacturing a semiconductor device of the present invention, after selectively forming an island-like region made of a low thermal conductivity insulating film on a silicon substrate, a polycrystalline region is formed on the surface of the substrate and the surface of the island-like region. The step of depositing a silicon film and beam annealing are performed on the polycrystalline silicon film formed on the surface of the substrate and the polycrystalline silicon film formed on the surface of the island-shaped region. A step of selectively melting only the polycrystalline silicon film on the island-like region while leaving the polycrystalline silicon film to form a polycrystalline silicon film, and then thermally oxidizing the substrate to form a surface of the single crystal silicon film; and a step of simultaneously oxidizing all of the polycrystalline silicon film on the surface of the substrate to form a silicon oxide film, and removing the silicon oxide film to a substantially uniform thickness to form a single crystal silicon film on the island-like region. It is characterized by including the step of expressing.
(6) 発明の実施例
第１図ないし第４図は本発明にかゝる一実施例
の工程順断面図を示しており、先づ第１図に示す
ようにSi基板１上に化学気相成長（CVD）法あ
るいは高温酸化法の何れかで、膜厚5000〓の
SiO2膜を形成し、これをリソグラフイ技術によ
りパターンニングして、例えば数μｍ角の島状領
域２とした後、更にその全面にCVD法又はスパ
ツタ法にて膜厚5000〓程度の多結晶シリコン膜８
を被着させる。(6) Embodiment of the Invention FIGS. 1 to 4 show step-by-step sectional views of an embodiment of the present invention. First, as shown in FIG. A film with a thickness of 5000 mm can be produced using either the phase epitaxy (CVD) method or the high-temperature oxidation method.
After forming a SiO 2 film and patterning it using lithography technology to form, for example, an island-like region 2 of several μm square, a polycrystalline film with a thickness of about 5000 mm is formed on the entire surface by CVD or sputtering. Silicon film 8
to be coated with.
次いで、第２図に示すように、その上面から電
子ビームを照射し、スキヤニングして、上記島状
領域２上に被着している多結晶シリコン膜を溶融
する。そうすると、これが凝固する際に単結晶シ
リコン膜４に生成される。一方、Si基板に直接被
着している多結晶シリコン膜３は多結晶膜のまゝ
残こる。これは下層がSiとSiO2との相異から、
多結晶シリコン膜の上昇温度が異なるためで、Si
は熱伝導が良く、SiO2は熱伝導が悪いから、
SiO2膜からなる島状領域上は多結晶シリコン膜
を溶融させても、Si基板上は熱放散が良くて、温
度が上昇しないから多結晶シリコン膜は溶融しな
い。更に詳しく述べると、ビームを固体表面に照
射したときの温度上昇θは
θ＝Ｗ／πKa
であらわされ、式中Ｗは入射エネルギー（ワツ
ト）、Ｋは熱伝導率、ａはビーム径を示すが、熱
伝導率ＫはSiでは0.84ジユール／cm・Ｓ・Ｋ、
SiO2では7.5×10-3ジユール／cm・Ｓ・Ｋで、両
者は２桁の相異があり、例えばSiO2膜からなる
島状領域２上が1000℃であつても、Si基板１上で
は僅か10℃しか温度上昇が生じない。この場合、
電子ビームの照射量は通常のビーム溶接時の照射
量と同程度の過大なエネルギーで、ビーム径は
100μｍが適当である。又、このようなビームア
ニール（ビーム熱処理）は電子ビームに限るもの
ではなく、レーザビームなど他のビーム系で照射
してもよい。 Next, as shown in FIG. 2, an electron beam is irradiated from the top surface and scanned to melt the polycrystalline silicon film deposited on the island-like region 2. Then, when this is solidified, it is generated in the single crystal silicon film 4. On the other hand, the polycrystalline silicon film 3 directly deposited on the Si substrate remains as a polycrystalline film. This is due to the difference between Si and SiO 2 in the lower layer.
This is because the temperature rise of the polycrystalline silicon film is different;
has good heat conduction, and SiO 2 has poor heat conduction, so
Even if the polycrystalline silicon film is melted on the island-shaped region made of the SiO 2 film, the polycrystalline silicon film will not melt because heat dissipation is good on the Si substrate and the temperature does not rise. To explain in more detail, the temperature rise θ when a beam is irradiated onto a solid surface is expressed as θ=W/πKa, where W is the incident energy (watts), K is the thermal conductivity, and a is the beam diameter. , thermal conductivity K is 0.84 Joule/cm・S・K for Si,
For SiO 2 , it is 7.5×10 -3 Joule/cm・S・K, and there is a difference of two orders of magnitude between the two. In this case, the temperature rises by only 10°C. in this case,
The irradiation amount of the electron beam is about the same excessive energy as the irradiation amount during normal beam welding, and the beam diameter is
100 μm is appropriate. Furthermore, such beam annealing (beam heat treatment) is not limited to electron beams, and irradiation may be performed using other beam systems such as laser beams.
このようにして、島状領域上に単結晶シリコン
膜４を生成した後、高温度に加熱し、加湿酸化す
れば第８図に示すように単結晶シリコンと多結晶
シリコンとでは酸化速度が異なり、多結晶シリコ
ンの方が酸化しやすいため、多結晶シリコン膜は
SiO2膜５に変化するが、単結晶シリコン膜４は
僅かに表面が酸化されるだけとなる。 After forming the single crystal silicon film 4 on the island-like region in this way, it is heated to a high temperature and subjected to humid oxidation. As shown in FIG. 8, the oxidation rate is different between single crystal silicon and polycrystalline silicon. , since polycrystalline silicon is more easily oxidized, polycrystalline silicon films are
Although it changes to a SiO 2 film 5, the surface of the single crystal silicon film 4 is only slightly oxidized.
次いで、第４図に示すようにフレオン（CF4）
ガスによるドライエツチングを行うと、表面の
SiO2膜がエツチング除去されて、SiO2膜２およ
び５上に多結晶シリコン膜４を露出させることが
できる。 Next, as shown in Figure 4, freon (CF 4 )
When dry etching with gas, the surface
The SiO 2 film is etched away to expose the polycrystalline silicon film 4 on the SiO 2 films 2 and 5.
このようにして形成した多結晶シリコン膜４に
半導体素子を形成すれば、素子分離帯を必要とし
ない二層目のICを形成することができる。 By forming a semiconductor element on the polycrystalline silicon film 4 thus formed, a second layer IC can be formed that does not require an element isolation band.
(7) 発明の効果
以上の説明は二層目のIC素子領域を形成する
実施例であるが、勿論Si基板面にも従前通りにIC
素子を形成することが可能であるから、二層に積
み上げた立体構造のICとすることができて、し
たがつて本発明は著しく集積度を向上させる効果
のあるものである。(7) Effects of the invention The above explanation is an example of forming a second layer IC element region, but of course, ICs can also be formed on the Si substrate surface as before.
Since it is possible to form an element, it is possible to form an IC with a three-dimensional structure stacked in two layers, and therefore, the present invention has the effect of significantly improving the degree of integration.
尚、上記実施例は島状領域２としてSiO2膜を
用いたが、その他の材料からなる低熱伝導性絶縁
膜を被着し、それにより島状領域を形成しても、
同様の結果が得られることは言うまでもない。 Incidentally, in the above embodiment, a SiO 2 film was used as the island-shaped region 2, but even if a low thermal conductivity insulating film made of other materials is deposited and the island-shaped region is formed thereby,
Needless to say, similar results can be obtained.
第１図ないし第４図は本発明にかゝる製造方法
の工程順断面図で、図中１はSi基板、２はSiO2
膜からなる島状領域、３は多結晶シリコン膜、４
は単結晶シリコン膜、５はSiO2膜を示す。
1 to 4 are cross-sectional views of the manufacturing method according to the present invention in the order of steps, in which 1 is a Si substrate, 2 is an SiO 2
3 is a polycrystalline silicon film; 4 is an island-like region made of a film;
5 indicates a single crystal silicon film, and 5 indicates a SiO 2 film.
Claims (1)
状領域を選択的に形成した後、該基板の表面及び
島状領域の表面に多結晶シリコン膜を被着する工
程と、 該基板の表面に形成されている多結晶シリコン
膜と該島状領域の表面に形成されている多結晶シ
リコン膜とにビームアニールを施して、上記基板
表面の多結晶シリコン膜を残し、島状領域上の多
結晶シリコン膜のみを選択的に溶融してこれを単
結晶シリコン膜となす工程と、 次いで該基板の熱酸化により前記単結晶シリコ
ン膜の表面、並びに前記基板表面の多結晶シリコ
ン膜の全部を同時に酸化してシリコン酸化膜を形
成する工程と、 該シリコン酸化膜をほぼ均一な厚さで除去して
前記島状領域上の単結晶シリコン膜を表出する工
程とを含むことを特徴とする半導体装置の製造方
法。[Claims] 1. A step of selectively forming an island-like region made of a low thermal conductivity insulating film on a silicon substrate, and then depositing a polycrystalline silicon film on the surface of the substrate and the surface of the island-like region; Beam annealing is performed on the polycrystalline silicon film formed on the surface of the substrate and the polycrystalline silicon film formed on the surface of the island-like region, leaving the polycrystalline silicon film on the surface of the substrate and forming the island-like region. A step of selectively melting only the polycrystalline silicon film on the region to form a single crystal silicon film, and then thermally oxidizing the substrate to melt the surface of the single crystal silicon film and the polycrystalline silicon film on the surface of the substrate. a step of simultaneously oxidizing all of the silicon oxide film to form a silicon oxide film; and a step of removing the silicon oxide film to a substantially uniform thickness to expose the single crystal silicon film on the island-like region. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20228881A JPS58102517A (en) | 1981-12-14 | 1981-12-14 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20228881A JPS58102517A (en) | 1981-12-14 | 1981-12-14 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58102517A JPS58102517A (en) | 1983-06-18 |
| JPH0335833B2 true JPH0335833B2 (en) | 1991-05-29 |
Family
ID=16455051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20228881A Granted JPS58102517A (en) | 1981-12-14 | 1981-12-14 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58102517A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56111239A (en) * | 1980-01-07 | 1981-09-02 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Preparation of semiconductor device |
-
1981
- 1981-12-14 JP JP20228881A patent/JPS58102517A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56111239A (en) * | 1980-01-07 | 1981-09-02 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Preparation of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58102517A (en) | 1983-06-18 |
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