JPH0334464A - Thin film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a highly reliable TFT with small off current and easy to manufacture by a method wherein reactive ion etching is done on only parts of a gate insulation film, a semiconductor layer of amorphous silicon, an insulation film and a pair of source and a drain electrodes laminated on a gate electrode. CONSTITUTION:A thin film transistor mentioned in the title comprises a gate insulation film 2, a semiconductor layer 3 of amorphous silicon, an insulation film 4 and a pair of a source and a drain electrodes 5 laminated on a gate electrode 1. The surface of the semiconductor layer 3 of amorphous silicon on a part with the source and drain electrodes 5 formed is subjected to reactive ion etching while the insulation film 4 is formed only on an upper part of the semiconductor layer 3 of amorphous silicon which is a channel 8 between the pair of the source and drain electrodes 5. By performing reactive ion etching, ohmic junction between the semiconductor layer 3 of amorphous silicon and the source and drain electrodes 5 is realized, and the surface of the semiconductor layer 3 of amorphous silicon at the channel 8 part is protected by the insulation film.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Applicability 9!'-) The present invention is directed to a thin film transistor (hereinafter abbreviated as TPT) used in a contact image sensor, an active matrix liquid crystal display device, etc. The present invention relates to writing and manufacturing methods, and particularly relates to TPT which is easy to manufacture and exhibits high performance.

(Prior Art) In recent years, thin film transistors (TPT) formed from multi-crystalline or amorphous semiconductors have been used. This T
Although the characteristics of FT are inferior to those using single-frame semiconductors, they are low cost and can form elements on large-area substrates, so they are used for example in contact image sensors,
Application as a switch element for active matrix liquid level display devices is being considered.

As shown in FIG. 3, the structure of a commonly used TPT includes an insulating substrate 10'', a gate electrode 1, a gate insulating film 2, an amorphous silicon semiconductor layer 3, and a pair of sources. - The drain 71F electrode 5 is laminated in order, and the semiconductor layer 3 and source/drain electrode 5 are made of n+ type silicon made of non-'II'l silicon doped with a large amount of phosphorus.
By forming the layer 6, an ohmic connection is achieved. In addition,
Conventionally, in such an inverted staggered TPT, the fourth
As shown in FIG. 4A, first, a gate electrode 1 with a predetermined pattern is formed on an insulating substrate 10-A, and then, as shown in FIG. After forming the n+ layer 6 on the upper surface of the third layer, the entire surface is further covered with a bridge metal 5a, and a source layer 6 is formed as shown in FIG. 4C.
Only the desired portion where the drain electrode 5 is to be formed is masked with photoresist 9, and the electrode metal 5a in the unmasked portion is etched as shown in FIG. 4d, and then the masked portion is further etched as shown in FIG. 4e. After removing n+Jm6 in the areas where it was not present, photoresist 9
is removed to form a desired shape as shown in Fig. 4f.

In such a TPT, electrons injected from the source electrode traverse the amorphous silicon semiconductor layer 3 and are applied to the voltage applied to the gate electrode 1 at the interface between the amorphous silicon semiconductor Jf43 and the gate insulating film 2. It passes through the correspondingly formed channel region 7, crosses the amorphous silicon semiconductor layer 3 again, and reaches the drain electrode. Here, n”Jf46
forms an ohmic layer with the semiconductor layer 3 and the source/drain electrode 5, and allows exchange of electrons from the source electrode to the amorphous silicon semiconductor layer 3 and from the amorphous silicon semiconductor layer 3 to the drain electrode. It has a role to play. However, if an n+ layer 6 exists in the amorphous silicon semiconductor layer 3L of the channel portion 8 between the source and drain t+IA, the resistance of the n+ layer 6 is very low, so electrons flow through the n+ layer 6, and the transistor is It stops working. Therefore, as described above, the n1 layer in the channel portion 8 between the source and drain electrodes is formed in the same layer after patterning the source and drain electrodes 5, as shown in FIG. 4e. - Etched and removed using resist 9 (for example, PG Reconbare and Double E Spare, Semiconductor and Semimetals, Vol. 21, Bar 1-D, 1984, p. 89 [P, G, L)
cCombcr and W, IE, 5pear,
SEMICONDUCTORAND SL:MIMI
ETALS, VOL, 21. PART D, 1
984, p89]). However, such T
In FT, when the n+ layer 6 is removed by etching, the surface of the amorphous silicon semiconductor layer 3 is also etched.
The surface of the amorphous silicon semiconductor layer 3 has many defects, and leakage current flows through the defects. Further, since phosphorus contained in the n+ layer 6 of the channel portion 8 diffuses into the surface of the amorphous silicon semiconductor layer 3 before etching the n+ layer 6 of the channel portion 8, the amorphous silicon semiconductor layer 3 surface resistance becomes lower. Due to these problems, a problem has arisen in ordinary TPTs that when a voltage of about 20 V or more is applied between the source and drain electrodes, the off-state current becomes extremely large.

(Problems to be Solved by the Invention) Therefore, the present invention solves three problems in the prior art as described in 2.
The purpose of the present invention is to provide a TPT that solves the problem, has a low off-state current, is easy to manufacture, and has high reliability.

(Means for Solving the Problems) A thin film transistor of the present invention that solves the problems as described in item 1-1 is provided by forming a gate bridge, a gate insulating film, and a surface area of a portion where a source/drain electrode is formed in order on an insulating substrate. an amorphous silicon semiconductor layer which is partially subjected to reactive ion etching, a pair of source/drain electrodes, and a part of the amorphous silicon semiconductor layer and the pair of source/drain electrodes
It is characterized by consisting of an insulating film formed between drain electrodes.

Further, the present invention is characterized in that the amorphous silicon semiconductor layer is an amorphous silicon layer doped with at least one impurity selected from the group consisting of boron, germanium, carbon, nitrogen, and oxygen. This shows a thin film transistor.

[Furthermore] The second problem is the process of forming a gate electrode on an insulating substrate, the step of forming a gate insulating film to cover the gate electrode, and the step of forming an amorphous silicon layer on the gate insulating film. In the process of forming the semiconductor layer, the area other than the area where the source/drain electrodes will be formed is covered with photoresist, and the CF
By performing reactive ion etching using four gases, the insulating film is removed from the part where the source/drain electrodes will be formed, and the pair of source/drain electrodes sandwiching the insulating film that was not removed from the left and right is removed. The problem is also solved by a method of manufacturing a thin film transistor, which is characterized in that the manufacturing process of a thin film transistor is omitted.

(Function) According to the present invention, the TFT is composed of a gate insulating film laminated on a gate tube, a semiconductor layer of amorphous silicon, an insulating film, and a pair of source/drain electrodes. By using reactive ion etching to remove the insulating film only in the part where the electrode is to be formed, and then forming a pair of source and drain electrodes,
This allows the source/drain electrode to form an ohmic contact with the amorphous silicon semiconductor layer without sandwiching the n'' layer.

Here, reactive ion etching is a dry etching method in which etching gas is decomposed by high-frequency discharge and etching is performed using the ions and radicals generated at that time, but reactive ion etching is not used. When applied to crystalline silicon, the amorphous silicon is etched, creating many dangling bonds on the surface. This dangling bond becomes a deep level in the forbidden band of the semiconductor, and easily exchanges electrons with amorphous silicon and metal electrodes. Therefore, in the TPT having the above-described structure, the source/drain electrodes and the amorphous silicon semiconductor layer can be connected to each other without sandwiching the n+ layer doped with a large amount of phosphorus between the amorphous silicon semiconductor layer and the source/drain electrodes. The layers can form ohmic connections.

In this way, an n layer doped with a large amount of phosphorus is not formed on the surface of the amorphous silicon semiconductor layer, and reactive ion etching is performed only on the regions where the source and drain electrodes 5 are to be formed, and on the other regions. Since the portion is covered with an insulating film, the surface of the amorphous silicon semiconductor layer in the channel portion between the source and drain electrodes is not subject to lower resistance due to phosphorus diffusion or increase in defects due to etching. As a result, leakage current due to these influences can be eliminated, and the off-state current can thereby be made extremely small. Furthermore, since the surface of the amorphous silicon semiconductor layer in the channel portion between the source and drain electrodes is protected by an insulating film, the TPT has extremely high reliability.

Furthermore, the structure of the present invention is effective even when the amorphous silicon semiconductor jd is doped with at least one kind of impurity such as boron, germanium, carbon, nitrogen, or oxygen, and is expected to find wider application. Become what you can.

Hereinafter, the present invention will be explained in detail with reference to the drawings. 1st
The figure is a sectional view schematically showing the structure of an embodiment of the TPT according to the present invention.

As shown in FIG. 1, the TPT of the present invention has a gate electrode 1L.
It is composed of a gate insulating film 2, an amorphous silicon semiconductor layer 3, an insulating film 4, and a pair of source/drain electrodes 5, which are stacked on top of each other. However, in the TPT of the present invention,
The surface layer of the amorphous silicon semiconductor layer 3 where the source/drain electrodes 5 are formed is subjected to reactive ion etching, and the insulating film 4 is formed on the top of the amorphous silicon semiconductor layer 3. Further, it is formed only in the channel portion 8 between the pair of source/drain electrodes 5.

As described above, in the TPT of the present invention, nod doped with a large amount of phosphorus is not formed between the amorphous silicon semiconductor layer 3 and the source/drain electrode 5 as in the conventional TPT. By performing reactive ion etching on the surface jd portion of the amorphous silicon semiconductor layer 3, the amorphous silicon can be etched without intervening the n layer, as is clear from the results shown in the examples described later. An ohmic connection is made between the semiconductor layer 3 and the source/drain electrode 5. In addition, since the surface of the amorphous silicon semiconductor 1-3 in the channel portion 8 between the source and drain electrodes is protected by the insulating film 4, even after TPT fabrication, the amorphous silicon semiconductor 1-3 in the channel portion 8 There is very little possibility that defects will occur in the silicon semiconductor layer 3.

Note that in the TPT of the present invention, the amorphous silicon semiconductor layer 3 may be doped with at least one impurity such as boron, germanium, carbon, nitrogen, or oxygen. When this amorphous silicon semiconductor layer 3 is doped with boron, carbon, nitrogen, or oxygen, it is possible to manufacture a TPT that operates up to a higher drain voltage than when it is not doped. Further, by doping with germanium, a TPT with low off-state current can be manufactured even under optical lighting conditions.

The TPT of the present invention having any of the above configurations can be manufactured as follows. That is, first, as shown in FIG. 2a, a gate electrode in a predetermined pattern is formed on an insulating substrate 10. Next, as shown in FIG. 2b, a gate insulating film 2, an amorphous silicon semiconductor layer 3, and an insulating film 4 are formed in this order so as to cover this gate electrode 1. Next, as shown in FIG. 2C, portions of the insulating film 4 other than those where the source/drain electrodes 5 are to be formed are covered with a photoresist 9, and reactive ion etching using CF4 gas is performed. As a result, the insulating film 4 is removed only in the portion where the source/drain electrode 5 is to be formed. Furthermore, in the area where the source/drain electrodes 5 are to be formed, the surface layer of the amorphous silicon semiconductor layer 3 that existed under the removed insulating film 4 is etched with a large number of dangling holes due to the reactive ion etching. A ring bond is formed. Note that the reason why only the portion where the source/drain electrode 5 is to be formed is etched is to prevent the amorphous silicon semiconductor layer 3 in the channel portion 8 between the source/drain electrode from being damaged by etching. This is for the purpose of After this reactive ion etching, as shown in FIG. 2d, a part of the stack formed as described above is covered with an electrode metal 5a, and then the photoresist 9 is removed. 5a is also removed at the same time, and as shown in FIG.

(Example) EXAMPLES Hereinafter, the present invention will be explained in more detail with reference to Examples.

First, in order to investigate the bonding characteristics between an amorphous silicon semiconductor layer and aluminum total bending, an aluminum metal electrode was formed on the amorphous silicon semiconductor in a cove-lar shape, and a voltage was applied between the aluminum electrodes to generate a current. It was measured. The results are shown in FIG.

The broken line in Figure 5a shows the characteristics when an aluminum electrode is formed on the amorphous silicon semiconductor without any treatment, and the solid line in Figure 5b shows the characteristics when CF4 gas is used on the amorphous silicon semiconductor. This figure shows the characteristics of an aluminum car frame formed by reactive ion etching.

As is clear from Figure 5, an ohmic junction is formed between the amorphous silicon semiconductor layer and the electrode by applying reactive ion etching to the amorphous silicon semiconductor layer to form the electrode. I understand. Although this example shows only the case where aluminum is used as the electrode metal, various characteristics can be obtained even if chromium, indium tin oxide (ITO), molybdenum, etc. are used as the electrode metal. .

Furthermore, the drain voltage (Vo)-drain current (ID) characteristic was actually investigated using the gate voltage (Vc) as a parameter in the inverted staggered TPT structure shown in FIG.

In addition, in the created TPT, the channel length is 20μ
m, and the channel width was 1000 μm.

The film thickness of the amorphous silicon semiconductor layer is 0.3 μm, and the gate insulating film is an amorphous silicon nitride film with a film thickness of 0.3 μm.
It was set as m. The results are shown in Figure 6.

The value shown by the broken line in FIG. 6 is the gate voltage (v6) in the conventional TPT which is exactly the same in shape as the TPT according to the present invention, but uses n layers to obtain an ohmic contact. Parameterized drain voltage (V
D) - drain current (II)) characteristics (Off 7 of the gate voltage OV showed almost the same characteristics as 161 except for the current, so it is omitted).

As is clear from FIG. 6, the off-state current is
T was improved by about two orders of magnitude at an applied voltage of 25 V compared to the conventional one.

(Effects of the Invention) As described below, according to the present invention, by ohmic contacting an amorphous silicon semiconductor layer and a metal electrode without using an n+ layer, a TPT with significantly lower off-current can be created. Contact image sensor-1
Extremely f
-It is beneficial.

Furthermore, in the case of the TPT of the present invention, in the production process,
Conventionally, the human body (11
Since there is no need to use 'F' phosphine gas, there are also advantages in terms of working environment and the configuration of the TPT manufacturing equipment.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view schematically showing the structure of an embodiment of the TFT according to the present invention, FIGS. 2a-e are cross-sectional views showing the structure of the TFT according to the present invention, and FIG. 3 is a typical example of the conventional TFT. TPT
Figures 4a-f are cross-sectional views schematically showing the structure of an example; Figures 4a-f are cross-sectional views showing typical conventional TPT manufacturing processes;
Figures a and b are diagrams showing the bonding characteristics between an amorphous silicon semiconductor and aluminum metal, and Figure 5a is a diagram showing the bonding characteristics between an amorphous silicon semiconductor and aluminum metal, and Figure 5a is a diagram showing the bonding characteristics when an aluminum electric bridge is formed without any treatment on the amorphous silicon semiconductor. Characteristics, and Figure 5b shows aluminum by applying reactive ion etching to an amorphous silicon semiconductor. This is the characteristic when a positive pole is formed, and the sixth
The figure shows drain voltage-current characteristics with gate voltage as a parameter in an embodiment of the TPT according to the present invention.
The gate voltage of conventional TPT, which is identical in shape to PT but uses an n+ layer to obtain an ohmic contact, is
It is a drain voltage-current characteristic at V. 1... Gate voltage, 2... Gate insulating film, 3...
Semiconductor layer of amorphous silicon, 4... Insulating film, 5...
Source/drain electrode, 5a... Electrode metal, 6...
n10 layers, 7... Channel region, 8... Channel portion, 9... Photoresist, 10... Insulating substrate.

Claims (3)

[Claims] (1) Gate electrode, gate insulating film,
An amorphous silicon semiconductor layer whose surface layer is subjected to reactive ion etching where source/drain electrodes are to be formed; a pair of source/drain electrodes; - A thin film transistor characterized by consisting of an insulating film formed between drain electrodes. (2) A claim characterized in that the amorphous silicon semiconductor layer is an amorphous silicon layer doped with at least one impurity selected from the group consisting of boron, germanium, carbon, nitrogen, and oxygen. Item 1. The thin film transistor according to item 1. (3) A step of forming a gate electrode on an insulating substrate, a step of forming a gate insulating film to cover the gate electrode, and a step of forming a semiconductor layer of amorphous silicon on the gate insulating film. , the process of removing the insulating film in the part where the source/drain electrode will be formed by covering the part other than the part where the source/drain electrode will be formed with photoresist and performing reactive ion etching using CF_4 gas; A method for manufacturing a thin film transistor, comprising the step of forming a pair of source/drain electrodes sandwiching the left and right insulating films.