JPH0334337A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH0334337A
JPH0334337A JP2148061A JP14806190A JPH0334337A JP H0334337 A JPH0334337 A JP H0334337A JP 2148061 A JP2148061 A JP 2148061A JP 14806190 A JP14806190 A JP 14806190A JP H0334337 A JPH0334337 A JP H0334337A
Authority
JP
Japan
Prior art keywords
circuit
semiconductor integrated
integrated circuit
pad
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2148061A
Other languages
Japanese (ja)
Inventor
Yoshinori Futami
二見　美紀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2148061A priority Critical patent/JPH0334337A/en
Publication of JPH0334337A publication Critical patent/JPH0334337A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06153—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry with a staggered arrangement, e.g. depopulated array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To make it possible to isolate two-dimensionally bonding wires from each other, to make possible the arrangement of a multitude of pads in the minimum area without reducing the yield of the manufacture of the title circuit and to cut down the cost of the circuit by a method wherein a plurality of columns of the pad parts are arranged zigzag near the outer periphery of the circuit. CONSTITUTION:Pad parts 2b arranged near the outer periphery of a semiconductor integrated circuit 1 are arranged being shifted zigzag to pad parts 2a. There is a connection 3 for connecting the pad part 2a with an internal circuit part (a). Lead frames 5 and 7 for connecting electrically the circuit 1 with an external circuit are integrally laminated through an electrical insulating material 6. There is a bonding wire 4a for connecting electrically each pad part 2 with the lead frame 5 and there is a bonding wire 4b for connecting electrically each pad part 2b with the lead frame 7.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路の外周回路との接続部構造に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure for connecting a semiconductor integrated circuit to an outer peripheral circuit.

〔発明の概要〕[Summary of the invention]

本発明は半導体集積回路のパッド部を外周付近に千鳥状
に複数列配列することにより、外部回路との接続用パッ
ドを多数必要とする高集積回路の小型化を実現するもの
である。The present invention realizes miniaturization of highly integrated circuits that require a large number of pads for connection with external circuits by arranging pad portions of semiconductor integrated circuits in multiple rows in a staggered manner near the outer periphery.

〔従来の技術〕[Conventional technology]

従来の半導体集積回路は、第６図の示す如くパッド部を
外周付近に一列配置する構造であった。A conventional semiconductor integrated circuit has a structure in which pad portions are arranged in a row near the outer periphery as shown in FIG.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

半導体集積回路の製造技術が向上し、小面積の中に多数
の回路を作成することが可能となってきているが、多数
の回路を外部回路と接続するためにパッド数も増加し、
従来の技術である外周付近に一列配置する方法では、外
周の総長さを延長しなければならず、小型化が困難であ
った。また、パッド部を単純に複数列にすることは、外
部回路との接続が難しく製造歩留りを低下させる恐れが
あった。As manufacturing technology for semiconductor integrated circuits improves, it has become possible to create a large number of circuits in a small area, but the number of pads has also increased in order to connect a large number of circuits to external circuits.
In the conventional technique of arranging them in a row near the outer periphery, the total length of the outer periphery had to be extended, making it difficult to downsize. Furthermore, simply arranging the pad portions in a plurality of rows may make it difficult to connect to an external circuit and may reduce manufacturing yield.

本発明はこのような問題を解決しようとするもので、そ
の目的とするところは多数パッド外周長を長くせずに配
列できるようにすることにより、回路に必要とする面積
が小さくかつ多数のパッドを必要とする集積回路を製造
歩留りを下げることなく実現することにある。The present invention attempts to solve such problems, and its purpose is to reduce the area required for the circuit and to reduce the area required for the circuit by arranging multiple pads without increasing the outer circumference length. The objective is to realize integrated circuits that require this without reducing manufacturing yield.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体集積回路は、パッド部が外周近辺に千鳥
状に２列以上配列することを特徴とする。The semiconductor integrated circuit of the present invention is characterized in that the pad portions are arranged in two or more rows in a staggered manner near the outer periphery.

さらに、外部回路とパッドを電気的に結合するためのリ
ードフレームを積層化したことを特徴とする。Furthermore, a feature is that a lead frame for electrically coupling an external circuit and a pad is laminated.

〔作　用〕[For production]

本発明の上記の構成によれば、半導体集積回路の面積を
パッド部のために必要以上に拡張せずにすみ、パッドと
内部回路との結線及び外部回路の結線がパッドが複数列
あるにもかかわらず交叉したり干渉することを防止でき
る。According to the above configuration of the present invention, the area of the semiconductor integrated circuit does not need to be expanded more than necessary due to the pad portion, and the connection between the pads and the internal circuit and the connection between the external circuit can be made even if there are multiple rows of pads. Cross-over and interference can be prevented regardless of the situation.

［実施例］ 第１図は本発明の実施例における半導体集積回路のパッ
ド部を示す平面図で、１は半導体集積回路、２ａは半導
体集積回路ｌの外周近辺に配列されたバンド部、２ｂは
前記パツド部２ａと千鳥状にずらして配列されたパッド
部である。３はパツド部２ａと内部回路部を接続する結
線である。[Embodiment] FIG. 1 is a plan view showing a pad portion of a semiconductor integrated circuit in an embodiment of the present invention, in which 1 is a semiconductor integrated circuit, 2a is a band portion arranged near the outer periphery of the semiconductor integrated circuit l, and 2b is a pad portion of a semiconductor integrated circuit l. These pad portions are arranged in a staggered manner with respect to the pad portion 2a. 3 is a connection for connecting the pad portion 2a and the internal circuit portion.

第２図は本発明の部分断面図で５．６は半導体集積回路
と外部回路を電気的に接続するためのリードフレームで
、電気絶縁材７を介して５と６を一体化に積層しである
。４ａはパツド部２ａとリードフレーム５を電気的に接
続するボンディングワイヤー、４ｂはパツド部２ｂとリ
ードフレーム６を電気的に接続するボンディングワイヤ
ーである。FIG. 2 is a partial cross-sectional view of the present invention, and 5.6 is a lead frame for electrically connecting the semiconductor integrated circuit and an external circuit. be. 4a is a bonding wire that electrically connects the pad portion 2a and the lead frame 5, and 4b is a bonding wire that electrically connects the pad portion 2b and the lead frame 6.

第３図は本発明の部分平面図でパッド部とリードフレー
ム部のワイヤーボンドによる接続状態を示す。FIG. 3 is a partial plan view of the present invention, showing a state in which the pad portion and the lead frame portion are connected by wire bonding.

第４図は本発明の部分断面図、第５図はリードフレーム
の一部の斜視図である。リードフレーム５と６は、それ
ぞれ平面状を形成後、カシメ等により積層的に一体化す
る。８縁材７はリードフレーム５の形状形成前に塗布又
は貼付等により一体化しておく、リードフレームは半導
体集積回路と一部モールド後、外部回路との接続部を第
４図、第５図に示す如く、リードフレーム５を５ａ及び
５ｂで曲げ戻すことにより分離することができる。FIG. 4 is a partial sectional view of the present invention, and FIG. 5 is a perspective view of a portion of the lead frame. The lead frames 5 and 6 are each formed into a planar shape and then integrated in a laminated manner by caulking or the like. 8 The edge material 7 is integrated by coating or pasting before forming the shape of the lead frame 5. After the lead frame is partially molded with the semiconductor integrated circuit, the connection part with the external circuit is shown in FIGS. 4 and 5. As shown, the lead frame 5 can be separated by bending back at 5a and 5b.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、パッド部を半導体集
積回路の外周近辺に複数列千鳥状に配列することにより
、ボンディングワイヤーを平面的に分離でき製造上の歩
留りを低下させることなく多数パッドを最少面積で配置
でき、コストを下げることを可能にするものである。又
、パッドを複数列にすることによる外部回路との接続の
問題もリードフレームの積層化により解決するものであ
る。As described above, according to the present invention, by arranging the pad portions in multiple rows in a staggered manner near the outer periphery of a semiconductor integrated circuit, bonding wires can be separated in a plane, and a large number of pads can be padded without reducing manufacturing yield. can be arranged in a minimum area, which makes it possible to reduce costs. Furthermore, the problem of connection with external circuits due to multiple rows of pads can be solved by stacking the lead frame.

特にリードフレームのピッチ微細化への対応として第４
図、第５図に示すように積層リードフレームの一部を分
離することは、半導体集積回路を用いるシステムの小型
化及びコストダウンに効果がある。In particular, in response to the finer pitch of lead frames, the fourth
Separating a part of the stacked lead frame as shown in FIGS. 5 and 5 is effective in reducing the size and cost of a system using semiconductor integrated circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例のパッド部平面図。 第２図は本発明の一実施例の部分断面図。 第３図は本発明の一実施例のパッド部とリードフレーム
部の接続方法を示す部分平面図。 第４図は本発明の一実施例を示す部分断面図。 第５図は本発明の一実施例のリードフレームの部分斜視
図。 第６図は従来の半導体集積回路を示すバンド部平面図。 ２　ａ　％　　２　ｂ・・・・・・パッド部３・・・・
・・・・・・・・・・・・・・内部回路接続線４ａ、４
ｂ・・・・・・ボンディングワイヤ５．６・・・・・・
・・・・・・リードフレーム７・・・・・・・・・・・
・・・・・・・電気絶縁体以上FIG. 1 is a plan view of a pad portion according to an embodiment of the present invention. FIG. 2 is a partial sectional view of one embodiment of the present invention. FIG. 3 is a partial plan view showing a method of connecting a pad section and a lead frame section according to an embodiment of the present invention. FIG. 4 is a partial sectional view showing one embodiment of the present invention. FIG. 5 is a partial perspective view of a lead frame according to an embodiment of the present invention. FIG. 6 is a plan view of a band portion showing a conventional semiconductor integrated circuit. 2 a % 2 b...Pad part 3...
・・・・・・・・・・・・Internal circuit connection wires 4a, 4
b...Bonding wire 5.6...
・・・・・・Lead frame 7・・・・・・・・・・・・
・・・・・・More than electrical insulator

Claims (2)

【特許請求の範囲】[Claims] （１）トランジスタ、抵抗、コンデンサ等からなる電子
回路を一体化した半導体集積回路に於いて、外部回路と
回路接続を行なうパッド部を、該半導体集積回路の外周
近辺に千鳥状に２列以上配列したことを特徴とする半導
体集積回路。(1) In a semiconductor integrated circuit that integrates electronic circuits consisting of transistors, resistors, capacitors, etc., pads for making circuit connections with external circuits are arranged in two or more rows in a staggered manner near the outer periphery of the semiconductor integrated circuit. A semiconductor integrated circuit characterized by: （２）複数枚のリードフレームを電気絶縁層に介して積
層化したリードフレームとパッド部を電気結線したこと
を特徴とする特許請求の範囲第１項記載の半導体集積回
路。(2) A semiconductor integrated circuit according to claim 1, characterized in that a lead frame formed by laminating a plurality of lead frames with an electrical insulating layer interposed therebetween and a pad portion are electrically connected.
JP2148061A 1990-06-06 1990-06-06 Semiconductor integrated circuit Pending JPH0334337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2148061A JPH0334337A (en) 1990-06-06 1990-06-06 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2148061A JPH0334337A (en) 1990-06-06 1990-06-06 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH0334337A true JPH0334337A (en) 1991-02-14

Family

ID=15444314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2148061A Pending JPH0334337A (en) 1990-06-06 1990-06-06 Semiconductor integrated circuit

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818114A (en) * 1995-05-26 1998-10-06 Hewlett-Packard Company Radially staggered bond pad arrangements for integrated circuit pad circuitry
US6037669A (en) * 1994-04-07 2000-03-14 Vlsi Technology, Inc. Staggered pad array
US6251768B1 (en) * 1999-03-08 2001-06-26 Silicon Integrated Systems Corp. Method of arranging the staggered shape bond pads layers for effectively reducing the size of a die

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57165272A (en) * 1981-04-03 1982-10-12 Toshiba Corp Connecting method for wire bonding
JPS5998543A (en) * 1982-11-26 1984-06-06 Hitachi Ltd Semiconductor device
JPS59107551A (en) * 1982-12-13 1984-06-21 Hitachi Ltd Semiconductor device
JPS59224152A (en) * 1983-06-03 1984-12-17 Nec Ic Microcomput Syst Ltd Integrated circuit device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57165272A (en) * 1981-04-03 1982-10-12 Toshiba Corp Connecting method for wire bonding
JPS5998543A (en) * 1982-11-26 1984-06-06 Hitachi Ltd Semiconductor device
JPS59107551A (en) * 1982-12-13 1984-06-21 Hitachi Ltd Semiconductor device
JPS59224152A (en) * 1983-06-03 1984-12-17 Nec Ic Microcomput Syst Ltd Integrated circuit device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6037669A (en) * 1994-04-07 2000-03-14 Vlsi Technology, Inc. Staggered pad array
US5818114A (en) * 1995-05-26 1998-10-06 Hewlett-Packard Company Radially staggered bond pad arrangements for integrated circuit pad circuitry
US6251768B1 (en) * 1999-03-08 2001-06-26 Silicon Integrated Systems Corp. Method of arranging the staggered shape bond pads layers for effectively reducing the size of a die

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