JP2002076244A - Multi-chip semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multifunction semiconductor device in which inter-chip alignment is facilitated, effective wiring length between functional chips is shortened, working frequency range is widened, and a plurality of semiconductor chips constitute a single semiconductor device. SOLUTION: A plurality of semiconductor chips, each having a circuit formed therein, are assembled three-dimensionally where a second semiconductor chip 21 is disposed substantially perpendicular to a first semiconductor chip 11, and the first and second semiconductor chips 11 and 21 are connected electrically at a plurality of contacts.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip semiconductor device, and more particularly, to a multi-chip semiconductor device formed of a plurality of semiconductor chips in a three-dimensional manner.

[0002]

2. Description of the Related Art As one measure for improving the functions of a system LSI, there is a combination of a plurality of functions. For example, DR
AM (Dynamic Random Access Memory) and logic L
Directionality such as mixed mounting of SI and mixed mounting of digital LSI and analog LSI is shown. Also, the number of functions to be mixed is not limited to two, and three or more functions are expected to be mixed and discussed.

However, since the LSI manufacturing process flow is different for each function, the total number of processes is significantly increased. Although this is not a simple addition of the number of LSI manufacturing steps having individual functions, the manufacturing cost is significantly increased accordingly. Also,
Due to the increase in the number of processes, it is necessary to consider the influence on the manufacturing yield, and there are many difficult problems in realizing a high-performance system LSI.

However, in order to increase the added value of functions of a so-called system LSI, it has been desired to develop a manufacturing process technology for realizing the above-described system LSI with a plurality of functions. Several solutions have been suggested for such needs.

[0005] For example, as shown in FIG. 13, there is a system LSI 101 having a configuration in which another chip 112 or 113 is planarly attached to a chip 111 serving as a base.

[0006]

However, in the above-mentioned laminated or superposed structure, it is difficult to align the chips to be combined. Alternatively, it is necessary to develop a correction technique or the like when misalignment occurs. This problem has not been solved and is not practical at this stage. Also, considering the performance of the finished product, problems such as the fact that the effective wiring distance between each functional chip is not necessarily shortened, and that the contact resistance adversely affects the signal delay and the desired performance cannot be obtained. Have. After all, there is a problem that the effective wiring length cannot be shortened, and the demand for a bandwidth for use in a wide frequency range cannot be met, and there is a problem in application to a high-performance system LSI in the future. Was. This is disclosed in SSDM (1999) p588-589. At the same time, as one solution, a connection hole 212 penetrating through the first chip 211 is opened as shown in FIG. A technology for connecting the chips 221 via the electrodes 213 has been disclosed. Further, it is difficult to efficiently radiate heat generated from the semiconductor chip in a structure in which semiconductor chips are stacked, particularly in a structure in which semiconductor chips are stacked.

[0007]

SUMMARY OF THE INVENTION The present invention is a multi-chip semiconductor device for solving the above-mentioned problems.

A multi-chip semiconductor device according to the present invention is obtained by three-dimensionally assembling a plurality of semiconductor chips on which circuits are formed, and at least one set of the plurality of semiconductor chips is electrically connected by a plurality of contacts. What is connected.

That is, a first multi-chip semiconductor device comprises: a first semiconductor chip on which a circuit is formed;
A second semiconductor chip provided with a circuit substantially perpendicular to the semiconductor chip and having a circuit formed therein,
And the second semiconductor chip are electrically connected by a plurality of contacts.

A second multi-chip semiconductor device comprises a first semiconductor chip on which a circuit is formed and a plurality of second semiconductor chips provided substantially perpendicular to the first semiconductor chip and on which a circuit is formed. And at least one of the first semiconductor chip and the second semiconductor chip is electrically connected by a plurality of contacts.

A third multi-chip semiconductor device comprises a first semiconductor chip on which a circuit is formed, and a plurality of second semiconductor chips provided substantially perpendicular to the first semiconductor chip and on which a circuit is formed. And a third semiconductor chip provided with a circuit and provided on the second semiconductor chip, wherein at least one of the first semiconductor chip and each of the second semiconductor chips is provided. One semiconductor chip is electrically connected with a plurality of contacts, and at least one of the second semiconductor chips and the third semiconductor chip are electrically connected with a plurality of contacts. Is what it is.

A fourth multi-chip semiconductor device is provided with a first semiconductor chip on which a circuit is formed and a first semiconductor chip on which a circuit is formed substantially perpendicular to the front surface side of the first semiconductor chip. A second semiconductor chip, and a third semiconductor chip provided with a circuit substantially perpendicular to the back surface side of the first semiconductor chip and having a circuit formed therein. The second semiconductor chip is electrically connected to the second semiconductor chip by a plurality of contacts, and the second semiconductor chip and the third semiconductor chip are electrically connected to each other by a plurality of contacts.

In each of the above multi-chip semiconductor devices, one semiconductor device is formed by incorporating a plurality of semiconductor chips. Therefore, by incorporating a plurality of types of semiconductor chips having different functions, a semiconductor having a multi-function is provided. The device is realized as one semiconductor device.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment according to a first multi-chip semiconductor device of the present invention is shown in a schematic perspective view of FIG. 1 (1) and a partial sectional perspective view of FIG. 1 (2). It will be explained by. FIG. 1 shows a multichip semiconductor device in which two semiconductor chips are combined as an example.

As shown in FIG. 1A, the multi-chip semiconductor device 1 includes a first semiconductor chip 11 on which circuits are formed. This first semiconductor chip 11
In contrast, a second semiconductor chip 21 on which a circuit is formed is provided substantially vertically.

For example, as shown in FIG.
A groove 12 is formed on the surface of the semiconductor chip 11 described above, and a part of the second semiconductor chip 21 is incorporated in the groove 12. Then, the first and second semiconductor chips 1
For example, bonding between the two is based on bonding using an adhesive, bonding using a reaction such as a silicide reaction, bonding using a eutectic reaction, bonding using an intermolecular force, bonding by alloying,
The semiconductor chips are fixed by various bonding methods such as bonding by sintering.

As described above, the two semiconductor chips can be easily assembled by incorporating and bonding them in the grooves, so that the alignment becomes easier than the conventional multi-chip structure by bonding. Further, since the semiconductor chips can be assembled three-dimensionally, the cooling effect of the semiconductor chips is enhanced as compared with the conventional multi-chip structure by bonding.

Next, the first and second semiconductor chips 1
An example of an electrical connection state between the terminals 21 and 21 will be described with reference to FIG. FIG. 2A is a perspective view, and FIG. 2B is a cross-sectional view.

As shown in (1) and (2) of FIG.
A plurality of electrodes (or wires) 13 are formed on the surface of the semiconductor chip 11. Also, the first semiconductor chip 1
A plurality of electrodes (or wiring) 23 are also formed on the surface of the second semiconductor chip inserted into the groove 12 formed in the first semiconductor chip. The electrodes 13 and 23 are formed at intervals at which they can come into contact with each other. Then, each electrode 23 of the second semiconductor chip 21 is inserted into the groove 12 together with the second semiconductor chip 21, and the surface 23S of the electrode 23 contacts the side surface 13S of the electrode 13 to form a contact. Through these contacts, conduction between the first semiconductor chip 11 and the second semiconductor chip 21 is established. Although not shown, the electrode 13 formed on the first semiconductor chip 11 may be formed to extend inside the groove 12.

In the multi-chip semiconductor device 1, for example, either the second semiconductor chip 21 to be inserted or the first semiconductor chip 11 to be inserted is DRA.
If it is M, it becomes a DRAM embedded system LSI. In such a DRAM-embedded system LSI, the portion contributing to the electrical connection is only one side of the second semiconductor chip 21 to be inserted.
Needs to be determined.

Next, the first and second semiconductor chips 1
FIG. 3 shows another example of the electrical connection state between the devices 1 and 21.
This will be described with reference to FIG. 3A is a perspective view, and FIGS. 3B and 4 are cross-sectional views.

As shown in (1) and (2) of FIG.
A plurality of electrodes (or wirings) 13 are formed on the surface of the semiconductor chip 11 so as to reach the side end of the groove 12. Also, a plurality of electrodes (or wiring) 23 are formed on the surface of the second semiconductor chip inserted into the groove 12 formed in the first semiconductor chip 11. Hereinafter, the term “electrode” includes the wiring. The electrodes 13 and 23 are formed at intervals at which they can come into contact with each other. And the second
Each of the electrodes 23 of the semiconductor chip 21 is formed by inserting the second semiconductor chip 21 into the groove 12 and pressing or crimping the electrode 13 to form a contact. The conduction between the first semiconductor chip 11 and the second semiconductor chip 21 is established via this contact.

As shown in FIG. 4A, the second semiconductor chip 21 may have an insulating film 25 formed on the surface thereof and electrodes 23 formed on the surface of the insulating film 25. Further, as shown in FIG. 4B, an insulating film 15 may be formed on the surface of the groove 12 of the first semiconductor chip 11.

Here, an example of a method of bonding semiconductor chips will be described with reference to FIG. As shown in FIG. 5, the electrode 1 is formed by the existing lithography technique and etching.
The groove 12 is formed in the first semiconductor chip 11 on which 3 is formed. The width of the groove 12 is, for example, 0.5 μm to 10 μm wider than the thickness of the second semiconductor chip depending on the thickness of the second semiconductor chip 21 incorporated in the groove 12, and the depth of the groove 12 is It is about 100 μm to 300 μm. Then, a precursor (not shown) of an insulator is formed inside the groove 12, and the second semiconductor chip 21 is inserted into the groove 12 and sintered, and the first semiconductor chip 11 is formed.
And the second semiconductor chip 21 are bonded and fixed. that time,
The second semiconductor chip 21 is pressed against the first semiconductor chip 11 so that the electrode 23 contacts the electrode 13. Then, the first semiconductor chip 11 and the second semiconductor chip 21
Is formed between the first semiconductor chip 11 and the second semiconductor chip 2 by the insulating film 28.
1 are bonded and fixed.

Next, first to fourth embodiments according to the second multi-chip semiconductor device of the present invention will be described with reference to FIG.
This will be described with reference to the perspective view of (2) and FIGS.

As shown in FIG. 6A, a plurality of second semiconductor chips 21 (21
a, 21b, 21c) can also be provided. First
Mounting method between first semiconductor chip 11 and each second semiconductor chip 21, and first and second semiconductor chips 11, 21
The method of bonding the electrodes (not shown) formed in the above is based on the method described above.

As shown in FIG. 6B, a plurality of second semiconductor chips 21 are formed on the first semiconductor chip 11.
(21a, 21b), the second semiconductor chip 21
It is also possible to provide a and 21b at a predetermined angle to each other (in the illustrated example, at a right angle). The method for attaching the first semiconductor chip 11 to each of the second semiconductor chips 21 and the method for bonding electrodes (not shown) formed on the first and second semiconductor chips 11 and 21 are the same as those described above. .

As shown in FIG. 7A, a plurality of second semiconductor chips 21 (21
a, 21b), the second semiconductor chips 21a, 21
It is also possible to provide b in a state of forming a predetermined angle with each other (in the illustrated example, at a right angle) and in a connected state. First semiconductor chip 11 and each second semiconductor chip 2
1, a method of attaching the second semiconductor chips 21 to each other, and a method of attaching the first and second semiconductor chips 11,
The method of bonding the electrodes (not shown) formed on 21 is based on the method described above.

Further, as shown in FIG.
It is also possible to provide a plurality of second semiconductor chips 21 (21a, 21b, 21c) having different heights on the semiconductor chip 11 of FIG. The method of attaching the first semiconductor chip 11 to each of the second semiconductor chips 21 and the method of bonding electrodes (not shown) formed on the first and second semiconductor chips 11 and 21 are the same as those described above.

When a plurality of semiconductor chips are incorporated as described above, the directions and heights of the semiconductor chips need not be uniform. Further, in the above embodiment, the second semiconductor chips 21 are arranged on the first semiconductor chip 11 so as to be, for example, perpendicular to each other or parallel to each other. It can be freely selected as long as the electrical connection with the first semiconductor chip 11 is not hindered. Also, the first semiconductor chip 11
The number of the second semiconductor chips 21 incorporated in the first semiconductor chip 11 may be any number as long as it can be incorporated on the first semiconductor chip 11. Further, the size of the second semiconductor chip 21 to be incorporated can be freely selected.

Next, an embodiment of the third multi-chip semiconductor device of the present invention will be described with reference to the perspective view of FIG.

As shown in FIG. 8, the multi-chip semiconductor device 6 includes a first semiconductor chip 11 on which circuits are formed. A second semiconductor chip 21 (21a, 21b, 21c) on which a circuit is formed and having the same height is provided substantially perpendicular to the first semiconductor chip 11. Further, a third semiconductor chip 31 is provided on each second semiconductor chip 21.

The first semiconductor chip 11 and the second
The semiconductor chips 21 and the second semiconductor chip 11 and the third semiconductor chip 31 are assembled by the same configuration as that described with reference to FIGS. The electrical connection between the first semiconductor chip 11 and each second semiconductor chip 21 and the electrical connection between each second semiconductor chip 11 and the third semiconductor chip 31 are shown in FIGS. The configuration is similar to that described.

Next, an embodiment of the fourth multi-chip semiconductor device of the present invention will be described with reference to the perspective view of FIG.

As shown in FIG. 9, the multi-chip semiconductor device 7 includes a first semiconductor chip 11 on which circuits are formed. On the front side of the first semiconductor chip 11, a second semiconductor chip 21 on which a circuit is formed is provided substantially vertically. Further, the first semiconductor chip 11
A third semiconductor chip 41 is provided substantially vertically on the back side of the semiconductor chip. In the drawing, the second semiconductor chip 21 and the third
Is provided at a position opposing the first semiconductor chip 11 with the first semiconductor chip 11 interposed therebetween, but the second semiconductor chip 21 and the third semiconductor chip 41 may not be disposed at positions opposing each other. Good.

The first semiconductor chip 11 and the second semiconductor chip 21 and the first semiconductor chip 11 and the third semiconductor chip 41 are the same as those described with reference to FIGS. They are assembled by a similar configuration. The electrical connection between the first semiconductor chip 11 and the second semiconductor chip 21 and the electrical connection between the first semiconductor chip 11 and the third semiconductor chip 41 have been described with reference to FIGS. The configuration is the same as described above.

Next, an embodiment of a multi-chip semiconductor device having a configuration in which the third multi-chip semiconductor device and the fourth multi-chip semiconductor device of the present invention are combined will be described with reference to a perspective view of FIG.

As shown in FIG. 10, a multi-chip semiconductor device 8 has a first semiconductor chip 11 on which a circuit is formed.
Is provided. A second semiconductor chip 21 (21a, 21b, 21c) on which a circuit is formed and having the same height is provided substantially perpendicular to the first semiconductor chip 11. Further, the third semiconductor chip 31 is provided on each of the second semiconductor chips 21 so that the back surface of the third semiconductor chip 31 is connected. further,
A fourth semiconductor chip 51 is provided on the front side of the third semiconductor chip 31.

The first semiconductor chip 11 and the second
Between the semiconductor chips 21, the second semiconductor chip 11 and the third semiconductor chip 31, and between the third semiconductor chip 31 and the fourth semiconductor chip 51.
The two are assembled by the same configuration as that described with reference to FIGS. Further, the first semiconductor chip 11 and the second semiconductor chips 21 are electrically connected to each other, the second semiconductor chip 11 and the third semiconductor chips 31 are electrically connected to each other, and the third semiconductor chip 3
The electrical connection between the first and fourth semiconductor chips 51 has the same configuration as that described with reference to FIGS.

Next, another embodiment of a multi-chip semiconductor device having a configuration in which the third multi-chip semiconductor device and the fourth multi-chip semiconductor device of the present invention are combined will be described with reference to the perspective view of FIG. I do.

As shown in FIG. 11, a multi-chip semiconductor device 8 has a first semiconductor chip 11 on which a circuit is formed.
Is provided. Further, the first semiconductor chip 1
1, a second semiconductor chip 21 (21a, 21b, 21c) on which a circuit is formed and having the same height is, for example, parallel to each other, and is substantially parallel to the first semiconductor chip. It is provided vertically.

The third semiconductor chip 31 is provided on each of the second semiconductor chips 21 so that the back side of the third semiconductor chip 31 is connected. Further, on the front surface side of the third semiconductor chip 31, the plurality of fourth semiconductor chips 51 (51 a, 51 b) are, for example, parallel to each other and perpendicular to the third semiconductor chip 31. It is provided in.

The fifth semiconductor chip 61 is provided on each of the fourth semiconductor chips 51 so that the back surface of the fifth semiconductor chip 61 is connected. Further, on the front side of the fifth semiconductor chip 61, a plurality of sixth semiconductor chips 71 (71a, 71b, 71c) are, for example, parallel to each other and perpendicular to the fifth semiconductor chip 61. It is provided so that it becomes.

The first semiconductor chip 11 and the second
Between the second semiconductor chips 11 and the third semiconductor chips 31, between the third semiconductor chips 31 and the fourth semiconductor chips 51, and between the fourth semiconductor chips 51. And the fifth semiconductor chips 61 and the respective fifth semiconductor chips 6
1 and the sixth semiconductor chip 71 are the same as those in FIGS.
It is assembled by a configuration similar to that described with reference to FIG. Also, the electrical connection between the first semiconductor chip 11 and each second semiconductor chip 21, the electrical connection between each second semiconductor chip 11 and the third semiconductor chip 31, and the electrical connection between the third semiconductor chip 31 and each Fourth semiconductor chip 5
Electrical connection between each other, electrical connection between each fourth semiconductor chip 51 and fifth semiconductor chip 61, and fifth electrical connection.
The electrical connection between the semiconductor chip 61 and each of the sixth semiconductor chips 71 has the same configuration as that described with reference to FIGS.

In the example shown in FIG. 11, the semiconductor chips are assembled in three stages, but it is also possible to assemble the semiconductor chips in more stages.

In each of the above-described embodiments, the connection between the semiconductor chips is made by connecting the side walls 1 of the step 17 formed on one side of the first semiconductor chip 11 as shown in FIG.
A second semiconductor chip 21 may be provided so as to adhere to 7S and bottom 17B. In this case, the method of bonding the first semiconductor chip 11 and the second semiconductor chip 21 is the same as described above. The method of electrically connecting the first semiconductor chip 11 and the second semiconductor chip 21 is the same as described above.

According to the configuration of the embodiment as described above, in order to incorporate the semiconductor chip into the semiconductor chip serving as a base, alignment of forming a groove in the first semiconductor chip serving as a base and second integration to be incorporated are performed. There is an advantage that it is determined by cutting the semiconductor chip and does not require an alignment control mechanism at the time of insertion. Therefore, the problem of the alignment disclosed in the conventional lamination technique by superposition is solved.

For example, in the manufacture of a system in which a memory chip is incorporated (inserted), a groove is formed in the first semiconductor chip serving as a base and a memory chip is formed in the groove as described in the above embodiment. The second
When the method of incorporating a semiconductor chip is used, since the memory capacity of the second semiconductor chip to be incorporated can be freely selected, a plurality of types of performance can be provided on a single type of mother substrate (first semiconductor chip). And a multi-chip semiconductor device having the same.

As described above, a plurality of semiconductor chips may be incorporated, but further incorporated and connected between the chips may be in contact with or separated from each other. If the electrical connection is made, a higher performance system LSI device can be obtained.

[0050]

As described above, according to the multi-chip semiconductor device of the present invention, since one semiconductor device is formed by incorporating a plurality of semiconductor chips, a plurality of types of semiconductor chips having different functions are provided. , A semiconductor device having multiple functions can be realized as one semiconductor device. Therefore, it is possible to provide a new solution to the multi-function mixed technology in the system LSI, and it is possible to significantly improve the manufacturing cost and the yield of the high-performance system LSI.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a first multi-chip semiconductor device of the present invention, wherein (1) is a schematic perspective view and (2) is a partial cross-sectional perspective view.

FIG. 2 is a diagram showing an example of an electrical connection state between first and second semiconductor chips, where (1) is a perspective view and (2)
Is a sectional view.

FIG. 3 is a diagram showing another example of an electrical connection state between the first and second semiconductor chips, (1) is a perspective view,
(2) is a sectional view.

FIG. 4 is a diagram showing another example of an electrical connection state between the first and second semiconductor chips, (1) is a perspective view,
(2) is a sectional view.

FIG. 5 is a cross-sectional view illustrating an example of a method of bonding semiconductor chips.

FIG. 6 is a diagram showing first and second embodiments of the second multi-chip semiconductor device of the present invention, wherein (1),
(2) is a perspective view.

FIGS. 7A and 7B are diagrams showing third and fourth embodiments according to the second multi-chip semiconductor device of the present invention, wherein FIGS.
(2) is a perspective view.

FIG. 8 is a perspective view showing an embodiment according to a third multi-chip semiconductor device of the present invention.

FIG. 9 is a perspective view showing an embodiment according to a third multi-chip semiconductor device of the present invention.

FIG. 10 is a perspective view showing an embodiment of a multichip semiconductor device having a configuration in which a third multichip semiconductor device and a fourth multichip semiconductor device of the present invention are combined.

FIG. 11 is a perspective view showing another embodiment of a multi-chip semiconductor device having a configuration in which a third multi-chip semiconductor device and a fourth multi-chip semiconductor device of the present invention are combined.

FIG. 12 is a perspective view showing another example of a connection structure between semiconductor chips in each embodiment.

FIG. 13 is a perspective view showing a conventional multi-chip semiconductor device.

FIG. 14 is a perspective view showing a conventional multi-chip semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Multi chip semiconductor device, 11 ... 1st semiconductor chip, 21 ... 2nd semiconductor chip

Claims (11)

[Claims] 1. A semiconductor device comprising: a plurality of semiconductor chips on which circuits are formed; wherein the plurality of semiconductor chips are three-dimensionally assembled; and at least one set of the plurality of semiconductor chips is electrically connected by a plurality of contacts. A multi-chip semiconductor device characterized by being performed. 2. A semiconductor device comprising: a first semiconductor chip having a circuit formed thereon; and a second semiconductor chip having a circuit formed substantially perpendicular to the first semiconductor chip and having a circuit formed therein. A multi-chip semiconductor device, wherein one semiconductor chip and the second semiconductor chip are electrically connected by a plurality of contacts. 3. The multi-chip semiconductor device according to claim 2, wherein a part of said second semiconductor chip is incorporated in a groove formed in said first semiconductor chip. 4. The semiconductor device according to claim 1, wherein an electrical contact between said first semiconductor chip and said second semiconductor chip is provided inside a groove formed in said first semiconductor chip. 4. The multi-chip semiconductor device according to 3. 5. The multi-chip semiconductor according to claim 2, wherein an electrical contact between said first semiconductor chip and said second semiconductor chip is provided on a surface of said first semiconductor chip. apparatus. 6. The multi-chip semiconductor according to claim 3, wherein an electrical contact between said first semiconductor chip and said second semiconductor chip is provided on a surface of said first semiconductor chip. apparatus. 7. A semiconductor chip comprising: a first semiconductor chip on which a circuit is formed; and a plurality of second semiconductor chips provided substantially perpendicular to the first semiconductor chip and having a circuit formed thereon, A multi-chip semiconductor device, wherein at least one of the first semiconductor chip and the second semiconductor chip is electrically connected by a plurality of contacts. 8. At least one set of second semiconductor chips among the second semiconductor chips is connected, and the connected sets of second semiconductor chips are electrically connected to each other through a plurality of contacts. The multi-chip semiconductor device according to claim 7, wherein: 9. A groove is formed in one of the connected second semiconductor chips, and the other second semiconductor chip is assembled by being inserted into the groove. The multi-chip semiconductor device according to claim 7, wherein: 10. A first semiconductor chip on which a circuit is formed, a plurality of second semiconductor chips provided substantially perpendicular to the first semiconductor chip and having a circuit formed thereon, A third semiconductor chip formed on the second semiconductor chip, wherein at least one of the first semiconductor chip and the second semiconductor chip has a plurality of semiconductor chips. And at least one of the second semiconductor chips and the third semiconductor chip are electrically connected by a plurality of contacts. Multi-chip semiconductor device. 11. A first semiconductor chip on which a circuit is formed, a second semiconductor chip on which a circuit is formed substantially perpendicular to a surface side of the first semiconductor chip, and A third semiconductor chip provided with a circuit substantially perpendicular to the upper surface of the back surface of the first semiconductor chip and having a circuit formed therein, wherein the first semiconductor chip and the second semiconductor chip are provided in plural; Wherein the second semiconductor chip and the third semiconductor chip are electrically connected by a plurality of contacts.