JPS5895860A - Semiconductor device having multiple layer structure - Google Patents
Semiconductor device having multiple layer structureInfo
- Publication number
- JPS5895860A JPS5895860A JP56194708A JP19470881A JPS5895860A JP S5895860 A JPS5895860 A JP S5895860A JP 56194708 A JP56194708 A JP 56194708A JP 19470881 A JP19470881 A JP 19470881A JP S5895860 A JPS5895860 A JP S5895860A
- Authority
- JP
- Japan
- Prior art keywords
- active
- semiconductor device
- layers
- active layer
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000004020 conductor Substances 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims abstract 11
- 239000011229 interlayer Substances 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract 1
- DSSYKIVIOFKYAU-XCBNKYQSSA-N (R)-camphor Chemical compound C1C[C@@]2(C)C(=O)C[C@@H]1C2(C)C DSSYKIVIOFKYAU-XCBNKYQSSA-N 0.000 description 1
- 241000723346 Cinnamomum camphora Species 0.000 description 1
- 229960000846 camphor Drugs 0.000 description 1
- 229930008380 camphor Natural products 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、半導体能動素子および受動素子が多数形成
されている活性層が多数積層した構造を持つ多層構造半
導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer structure semiconductor device having a structure in which a large number of active layers in which a large number of semiconductor active elements and passive elements are formed are laminated.
半導体装置の高速動作化、爾密度化のため、半導体能＃
素子が多数形成された活性層を多数に積層した構造を持
つ多層構造半導体装置がある。In order to increase the speed and density of semiconductor devices, semiconductor performance #
There is a multilayer structure semiconductor device that has a structure in which a large number of active layers in which a large number of elements are formed are laminated.
従来のこの樟の半導体装置の断面図を第１図に示す。図
において（１）は基板、（２）は半導体素子を作成する
活性層、（３） Ｉ／′ｉ絶縁層、（４）は各活性層を
結ぶコンタクトホールである。また上層部の活性層の面
積は下層部の活性層の面積より小さくなっている。A cross-sectional view of this conventional camphor semiconductor device is shown in FIG. In the figure, (1) is a substrate, (2) is an active layer for forming a semiconductor element, (3) is an I/'i insulating layer, and (4) is a contact hole connecting each active layer. Further, the area of the active layer in the upper layer is smaller than the area of the active layer in the lower layer.
次に従来の活性層が多数積層された構造を持つ半導体装
置の作用について説明する。基板（１）け半導体装置全
体を支える。活性層（２）は半萼体能＃素層（２）をｉ
ＩＥ気的に絶縁するために設けられている。Next, the operation of a conventional semiconductor device having a structure in which a large number of active layers are stacked will be explained. The substrate (1) supports the entire semiconductor device. The active layer (2) is semicalyx #elementary layer (2) i
It is provided for electrical insulation.
またコンタクトホール（４）は各活性層の半導体能動素
子を動作させるのに必要な電気的エネルギーを供給した
り、情報信号を往復させるために各絶縁層にあけられた
穴である。Further, contact holes (4) are holes made in each insulating layer for supplying electrical energy necessary to operate the semiconductor active elements in each active layer and for reciprocating information signals.
ところが従来の第１図のような多層構造半導体装置では
、各活性層間のコンタクトを、コンタクトホールによっ
ているため、絶縁層に穴をあけなければならず、作成し
にくいという欠点があった。However, in the conventional multilayer structure semiconductor device as shown in FIG. 1, the contact between the active layers is made by contact holes, which requires holes to be made in the insulating layer, which is difficult to fabricate.
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、階段上になっている各活性層の周
辺部にコンタクト部を集め、各層間配線のために、上下
活性層のコンタクト部を密着した導体で配線することに
よって、多層構造半導体装置を作成し易くすることを目
的としている。This invention was made in order to eliminate the above-mentioned drawbacks of the conventional method.Contact parts are gathered around the periphery of each active layer on a staircase, and the upper and lower active layers are connected for interconnection between layers. The purpose of this invention is to facilitate the production of a multilayer semiconductor device by wiring contact portions with conductors that are in close contact with each other.
以丁、この発明の一実施例を図について説明する。第２
図にこの発明による多層構造半導体装置の４而図を示す
。（１）は基板、（２）は半導体素子を作成する活性層
、（３）は絶縁層、（５）は密着した配線用導体である
。この配線用導体（５） ｄ図に示すように各活性層の
周辺部において、各活性層とコンタクトをとるようにし
て形成されている。An embodiment of the present invention will now be described with reference to the drawings. Second
The figure shows four diagrams of a multilayer structure semiconductor device according to the present invention. (1) is a substrate, (2) is an active layer for forming a semiconductor element, (3) is an insulating layer, and (5) is a closely-attached wiring conductor. The wiring conductor (5) is formed at the periphery of each active layer so as to make contact with each active layer, as shown in Figure d.
ここで、基板（１） ｆ′１半導体装置全体を支える。Here, the substrate (1) f'1 supports the entire semiconductor device.
活性層（２）には多数の半導体能動素子および受動素子
が作られている。絶縁層（３）は各活性層を電気的にる
のに必要な電気的エネルギーを供給したり、情報信号を
往復させるために各層間に接続されている。A large number of semiconductor active and passive elements are fabricated in the active layer (2). An insulating layer (3) is connected between each layer to supply the electrical energy necessary to electrically activate each active layer and to reciprocate information signals.
なお上記実施例では、すべての配線を、密着した導体に
よって配線する例を示したが、コンタクトホールによる
接続を並用してもよい。または。In the above embodiment, an example is shown in which all the wiring is wired using closely-contact conductors, but connections using contact holes may also be used. or.
ワイヤボンディングを使用してもよい。Wire bonding may also be used.
′１走、図では活性層が５層の場合を示したが、活性層
は何層あってもよい。Although the figure shows a case where there are five active layers, there may be any number of active layers.
以上のように、この発明によれば、各活性層の接続に密
着した導体によって配線を行ったので、層間の接続が６
易になるという効果がある。As described above, according to the present invention, wiring is performed using a conductor that is in close contact with the connection of each active layer, so that the connection between the layers is 6.
This has the effect of making it easier.
第１図は従来の多層構造半導体装置を説明するための断
面図、第２図はこの発明の一実施例である多層構造半導
体装置を説明するだめの断面図である。
図において、（１）は基板、（２）は活性層、（３）は
絶縁層、（４）はコンタクトホール、（５）は配線用の
密着した導体である。
なお、図中岡−符号はそれぞれ同一または相当部分を−
示す。FIG. 1 is a sectional view for explaining a conventional multilayer structure semiconductor device, and FIG. 2 is a sectional view for explaining a multilayer structure semiconductor device according to an embodiment of the present invention. In the figure, (1) is a substrate, (2) is an active layer, (3) is an insulating layer, (4) is a contact hole, and (5) is a closely-contact conductor for wiring. In addition, the numbers in the figure Nakaoka indicate the same or corresponding parts.
show.
Claims (1)
動素子および受動素子が多数形成されている活性層を、
上の活性層の面積が下の活性層の面積より小さくなるよ
うに積層した多層構造を持つ半導体装置において、階段
状になっている各活性層の周辺部にコンタクト部を集め
、各層間配線を のためこれを、密着した導体で上下同区配線することを
特徴とする多層構造半導体装置。[Claims] In order to increase the operating speed and density of semiconductor devices, an active layer in which a large number of semiconductor active elements and passive elements are formed,
In a semiconductor device that has a multilayer structure in which the area of the upper active layer is smaller than the area of the lower active layer, contacts are gathered around the periphery of each step-like active layer, and each interlayer wiring is connected. Therefore, this multilayer structure semiconductor device is characterized in that the upper and lower parts are interconnected in the same manner using closely-contact conductors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56194708A JPS5895860A (en) | 1981-11-30 | 1981-11-30 | Semiconductor device having multiple layer structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56194708A JPS5895860A (en) | 1981-11-30 | 1981-11-30 | Semiconductor device having multiple layer structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5895860A true JPS5895860A (en) | 1983-06-07 |
Family
ID=16328928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56194708A Pending JPS5895860A (en) | 1981-11-30 | 1981-11-30 | Semiconductor device having multiple layer structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5895860A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10090320B2 (en) | 2016-05-19 | 2018-10-02 | Toshiba Memory Corporation | Semiconductor device and method for manufacturing the same |
-
1981
- 1981-11-30 JP JP56194708A patent/JPS5895860A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10090320B2 (en) | 2016-05-19 | 2018-10-02 | Toshiba Memory Corporation | Semiconductor device and method for manufacturing the same |
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