JPH0333042Y2 - - Google Patents

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Publication number
JPH0333042Y2
JPH0333042Y2 JP1983112119U JP11211983U JPH0333042Y2 JP H0333042 Y2 JPH0333042 Y2 JP H0333042Y2 JP 1983112119 U JP1983112119 U JP 1983112119U JP 11211983 U JP11211983 U JP 11211983U JP H0333042 Y2 JPH0333042 Y2 JP H0333042Y2
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JP
Japan
Prior art keywords
electrodes
electrode
insulating
protective film
insulating substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1983112119U
Other languages
Japanese (ja)
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JPS6020110U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Priority to JP11211983U priority Critical patent/JPS6020110U/en
Publication of JPS6020110U publication Critical patent/JPS6020110U/en
Application granted granted Critical
Publication of JPH0333042Y2 publication Critical patent/JPH0333042Y2/ja
Granted legal-status Critical Current

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Description

【考案の詳細な説明】 この考案は、チツプ抵抗器に係り、特に、共通
のセラミツク基板等の上に複数の抵抗素子を隣接
配置した所謂多連チツプ抵抗器に関する。
[Detailed Description of the Invention] The present invention relates to a chip resistor, and more particularly to a so-called multiple chip resistor in which a plurality of resistance elements are arranged adjacent to each other on a common ceramic substrate or the like.

第1図は、従来の多連チツプ抵抗器を示し、第
2図は第1図の−線断面を示す。長方形状に
形成されたセラミツク基板2には、その長手方向
に一定の絶縁間隔を置いてその表面及び側面部に
複数組の電極4A,4Bが形成されているととも
に、各電極4A,4B間には、第2図に示すよう
に、電極4Aに一端、電極4Bに他端が重ねられ
て電気的に接続される抵抗素子6が個別に形成さ
れている。そして、抵抗素子6及び電極4A,4
Bの一部の表面には、合成樹脂等の絶縁材料から
なる保護膜8が被覆されている 次に、第3図は、この種の抵抗器のフエイスボ
ンデイングによるプリント配線板上の実装状態を
示す。即ち、プリント配線板10の表面に形成さ
れた配線導体12A,12Bの間には、チツプ抵
抗器が保護膜8をプリント配線板10側にして半
田14により接続されている。
FIG. 1 shows a conventional multiple chip resistor, and FIG. 2 shows a cross section taken along the line -- in FIG. A ceramic substrate 2 formed in a rectangular shape has a plurality of electrodes 4A, 4B formed on its surface and side surfaces at a constant insulating interval in the longitudinal direction, and a plurality of electrodes 4A, 4B are formed between each electrode 4A, 4B. As shown in FIG. 2, a resistor element 6 is individually formed, one end of which is overlapped with the electrode 4A and the other end of which is electrically connected to the electrode 4B. Then, the resistance element 6 and the electrodes 4A, 4
A part of the surface of B is covered with a protective film 8 made of an insulating material such as synthetic resin. Next, FIG. 3 shows how this type of resistor is mounted on a printed wiring board by face bonding. show. That is, a chip resistor is connected by solder 14 between wiring conductors 12A and 12B formed on the surface of printed wiring board 10, with protective film 8 facing printed wiring board 10.

この種の抵抗器では、コンパクト化を目的とし
ているため、隣接する電極4A,4A間、電極4
B,4B間の間隔は狭く設定されている。このた
め、半田付けした場合には、その間隔内に半田が
入り込み、電極4A,4A間、電極4B,4B間
に半田14によつて短絡が生じ易く、しかも、隣
接する電極4A,4A間、電極4B,4B間の耐
電圧が低い。また、プリント配線板10上に実装
した場合、保護膜8の厚さによつて各電極4A,
4A間、電極4B,4B間の間隙部には、大きな
空間16が形成され、この空間16にフエイスボ
ンデイングの際の処理液、水分等の不純物が侵入
して残留し、これがチツプ抵抗器等の特性を劣化
させる原因になる。
This type of resistor aims to be compact, so between the adjacent electrodes 4A and 4A, the electrode 4
The interval between B and 4B is set narrowly. Therefore, when soldering is performed, the solder enters into the space between the electrodes 4A and 4A, and between the electrodes 4B and 4B, and short circuits are likely to occur due to the solder 14. The withstand voltage between the electrodes 4B and 4B is low. Moreover, when mounted on the printed wiring board 10, each electrode 4A,
A large space 16 is formed in the gap between the electrodes 4A and between the electrodes 4B and 4B, and impurities such as processing liquid and water during face bonding enter and remain in this space 16, and this impurities such as chip resistors etc. This may cause deterioration of characteristics.

そこで、この考案は、電極間の空間を除くこと
により、耐電圧を向上させるとともに、半田の侵
入による短絡や不純物等の侵入による特性の劣化
を防止したチツプ抵抗器の提供を目的とする。
Therefore, the object of this invention is to provide a chip resistor that improves the withstand voltage by eliminating the space between the electrodes, and prevents short circuits due to solder penetration and deterioration of characteristics due to impurity penetration.

即ち、この考案のチツプ抵抗器は、絶縁体基板
の表面に対向して配置されるとともに前記絶縁体
基板の側面側に延長された複数の電極と、前記絶
縁体基板の表面上の前記電極間に設置された複数
の抵抗素子と、各抵抗素子とともに前記電極の一
部を選択的に覆つて前記絶縁体基板上に設置さ
れ、前記絶縁体基板の表面側及び側面側に露出さ
せた前記電極の間に絶縁部材として延長し、且
つ、電極面より突出させた保護膜とを備えたもの
である。
That is, the chip resistor of this invention includes a plurality of electrodes arranged facing the surface of an insulating substrate and extending to the side surface of the insulating substrate, and a plurality of electrodes arranged on the surface of the insulating substrate. a plurality of resistance elements installed on the insulator substrate, and the electrode installed on the insulator substrate selectively covering a part of the electrode together with each resistance element, and exposed on the front and side surfaces of the insulator substrate. A protective film extends as an insulating member between the electrodes and protrudes from the electrode surface.

以下、この考案を図面に示した実施例を参照し
て詳細に説明する。
Hereinafter, this invention will be described in detail with reference to embodiments shown in the drawings.

第4図は、この考案のチツプ抵抗器の実施例を
示し、第1図に示す抵抗器と同一部分には同一符
号が付してある。
FIG. 4 shows an embodiment of the chip resistor of this invention, and the same parts as those of the resistor shown in FIG. 1 are given the same reference numerals.

このチツプ抵抗器には、絶縁体基板として例え
ばセラミツク基板2が用いられ、このセラミツク
基板2の表面には、一定の絶縁間隔を置いてその
表面に複数組の電極4A,4Bが対向して配置さ
れており、各電極4A,4Bはセラミツク基板2
の側面側に延長されている。そして、各電極4
A,4B間には、第2図に示すように、電極4A
に一端、電極4Bに他端が重ねられて電気的に接
続される抵抗素子6が個別に形成されている。
For example, a ceramic substrate 2 is used as an insulating substrate in this chip resistor, and a plurality of pairs of electrodes 4A and 4B are arranged facing each other on the surface of the ceramic substrate 2 with a constant insulating interval. Each electrode 4A, 4B is connected to a ceramic substrate 2.
is extended to the side. And each electrode 4
Between A and 4B, as shown in FIG.
A resistor element 6 is individually formed, one end of which is overlapped with the electrode 4B, and the other end of which is electrically connected to the electrode 4B.

また、セラミツク基板2の上面には、各抵抗素
子6とともに各電極4A,4Bの上面の一部を選
択的に覆う保護膜8が設置されている。この保護
膜8は合成樹脂等の絶縁材料によつて形成され、
その一部が電極4A,4A間、電極4B,4B間
のセラミツク基板2の表面及び側面側に延長さ
れ、セラミツク基板2の表面側で絶縁部18A,
18Bが形成されるとともに、セラミツク基板2
の側面側で絶縁部20A,20Bが形成されてい
る。また、保護膜8は、電極4A,4Bより厚く
形成され、電極4A,4A間及び電極4B,4B
間の絶縁部18A,18Bが各抵抗素子6の上面
側の保護膜8と平坦面を成し、しかも、絶縁部2
0A,20Bも電極4A,4Bより厚く形成され
ていることから、絶縁部18A,18B,20
A,20Bは、それぞれ電極4A,4Bの間から
その電極面を越えて厚み方向に突出している。
Further, on the upper surface of the ceramic substrate 2, a protective film 8 is provided which selectively covers a portion of the upper surface of each electrode 4A, 4B together with each resistor element 6. This protective film 8 is formed of an insulating material such as synthetic resin,
A part of it is extended to the surface and side surface of the ceramic substrate 2 between the electrodes 4A and 4A and between the electrodes 4B and 4B.
18B is formed, and the ceramic substrate 2
Insulating portions 20A and 20B are formed on the side surfaces of. Further, the protective film 8 is formed thicker than the electrodes 4A and 4B, and is formed between the electrodes 4A and 4A and between the electrodes 4B and 4B.
The insulating parts 18A and 18B between them form a flat surface with the protective film 8 on the upper surface side of each resistance element 6, and the insulating parts 2
Since 0A and 20B are also formed thicker than electrodes 4A and 4B, insulating parts 18A, 18B, 20
A and 20B protrude from between the electrodes 4A and 4B, respectively, beyond the electrode surfaces in the thickness direction.

このように隣接する電極4A,4A間、電極4
B,4B間に保護膜8の一部を選択的に延長させ
て絶縁部18A,18B,20A,20Bを形成
したので、第5図に示すように、プリント配線板
10上に実装した場合、第3図に示すように、隣
接する一方の電極4A,4A間の空間16は絶縁
部18Aで埋まるとともに、隣接する他方の電極
4B,4B間に生じていた空間16が絶縁部18
Bによつて埋まることになる。このため、電極4
A,4A間、電極4B,4B間の耐電圧を高くで
きるとともに、半田14の侵入による短絡を防止
でき、従来、空間部に生じていたフエイスボンデ
イングの処理液、水分、その他の不純物の侵入及
び残留が無くなるため、特性劣化が防止でき、安
定した電気的特性を長期に亘つて維持できる。
In this way, between the adjacent electrodes 4A, 4A, the electrode 4
Since the insulating parts 18A, 18B, 20A, and 20B are formed by selectively extending a part of the protective film 8 between B and 4B, when mounted on the printed wiring board 10 as shown in FIG. As shown in FIG. 3, the space 16 between the adjacent electrodes 4A, 4A is filled with the insulating part 18A, and the space 16 between the other adjacent electrodes 4B, 4B is filled with the insulating part 18A.
It will be filled by B. For this reason, electrode 4
It is possible to increase the withstand voltage between A and 4A and between electrodes 4B and 4B, and also prevent short circuits due to the intrusion of solder 14, and prevent the intrusion of face bonding treatment liquid, moisture, and other impurities that conventionally occur in the space. Since there is no residue, characteristic deterioration can be prevented and stable electrical characteristics can be maintained over a long period of time.

また、セラミツク基板2の側面側の一方の電極
4A,4A間には保護膜8の延長によつて絶縁部
20Aが設置され、また、他方の電極4B,4B
間には保護膜8の延長によつて絶縁部20Bが設
置され、しかも、各絶縁部20A,20Bは、各
電極4A,4Bの電極面より突出しているので、
絶縁部18A,18Bと相俟つて、隣接した電極
4A,4A間、電極4B,4B間の耐電圧を向上
させることができるとともに、半田による短絡が
防止できる。
Further, an insulating part 20A is installed between one electrode 4A and 4A on the side surface side of the ceramic substrate 2 by an extension of the protective film 8, and an insulating part 20A is installed between the other electrodes 4B and 4B.
An insulating part 20B is installed between them by an extension of the protective film 8, and each insulating part 20A, 20B protrudes from the electrode surface of each electrode 4A, 4B.
Together with the insulating parts 18A and 18B, the withstand voltage between the adjacent electrodes 4A and 4A and between the electrodes 4B and 4B can be improved, and short circuits due to solder can be prevented.

そして、各絶縁部18A,18B,20A,2
0Bは、抵抗素子6の上面に設置される保護膜8
の延長によつて形成できるので、抵抗素子6の保
護とともに、各電極4A,4A間、電極4B,4
B間の絶縁を特別な工程を要することなく、同一
工程で処理できる。
And each insulating part 18A, 18B, 20A, 2
0B is a protective film 8 installed on the upper surface of the resistor element 6.
Since it can be formed by extending the
The insulation between B can be processed in the same process without requiring a special process.

なお、絶縁部18A,18B,20A,20B
は、保護膜8とは別の絶縁部材で形成し、保護膜
8を延長させた形態としてもよく、同様の効果が
期待できる。
In addition, insulating parts 18A, 18B, 20A, 20B
may be formed of an insulating member different from the protective film 8, and the protective film 8 may be extended, and similar effects can be expected.

以上説明したように、この考案によれば、次の
ような効果が得られる。
As explained above, according to this invention, the following effects can be obtained.

(a) 抵抗素子とともに電極の表面の一部を選択的
に覆う保護膜を絶縁体基板の表面及び側面側に
露出する電極の間に絶縁部材として延長し、か
つ、電極面より突出させたので、従来、電極間
に生じていた空間が絶縁部材によつて除くこと
ができ、電極間の耐電圧を高めることができる
とともに、半田による短絡や不純物の侵入が防
止されるため、信頼性の向上とともに安定した
電気的な特性を維持できる。
(a) A protective film that selectively covers part of the surface of the electrode along with the resistive element is extended as an insulating member between the electrodes exposed on the surface and side surfaces of the insulating substrate, and is made to protrude from the electrode surface. , the space that conventionally occurred between electrodes can be removed by using an insulating member, increasing the withstand voltage between the electrodes, and preventing short circuits and impurity intrusion due to solder, improving reliability. At the same time, stable electrical characteristics can be maintained.

(b) また、電極間の絶縁部材は保護膜を延長して
形成したので、保護膜の形成と同時に電極間の
絶縁を行うことができ、特別な処理工程を要し
ないので、電極間の耐電圧が高くかつ信頼性の
高いチツプ抵抗器を安価に製造できる。
(b) In addition, since the insulating member between the electrodes is formed by extending the protective film, the insulation between the electrodes can be achieved at the same time as the formation of the protective film, and no special treatment process is required. Chip resistors with high voltage and high reliability can be manufactured at low cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は多連チツプ抵抗器を示す斜視図、第2
図は第1図に示した多連チツプ抵抗器の−線
断面図、第3図は第1図に示した多連チツプ抵抗
器の実装状態を示す斜視図、第4図はこの考案の
チツプ抵抗器の実施例を示す斜視図である。第5
図は第4図に示したチツプ抵抗器の実装状態を示
す斜視図である。 2……セラミツク基板(絶縁体基板)、4A,
4B……電極、6……抵抗素子、8……保護膜、
18A,18B,20A,20B……絶縁部(絶
縁部材)。
Figure 1 is a perspective view showing a multiple chip resistor, Figure 2
The figure is a sectional view taken along the line -- of the multiple chip resistor shown in Figure 1, Figure 3 is a perspective view showing the mounting state of the multiple chip resistor shown in Figure 1, and Figure 4 is a cross-sectional view of the multiple chip resistor shown in Figure 1. FIG. 2 is a perspective view showing an example of a resistor. Fifth
This figure is a perspective view showing the state in which the chip resistor shown in FIG. 4 is mounted. 2... Ceramic substrate (insulator substrate), 4A,
4B... Electrode, 6... Resistance element, 8... Protective film,
18A, 18B, 20A, 20B...Insulating section (insulating member).

Claims (1)

【実用新案登録請求の範囲】 絶縁体基板の表面に対向して配置されるととも
に前記絶縁体基板の側面側に延長された複数の電
極と、 前記絶縁体基板の表面上の前記電極間に設置さ
れた複数の抵抗素子と、 各抵抗素子とともに前記電極の一部を選択的に
覆つて前記絶縁体基板上に設置され、前記絶縁体
基板の表面側及び側面側に露出させた前記電極の
間に絶縁部材として延長し、且つ、電極面より突
出させた保護膜とを備えたことを特徴とするチツ
プ抵抗器。
[Claims for Utility Model Registration] A plurality of electrodes arranged opposite to the surface of an insulating substrate and extending to the side surface of the insulating substrate, and installed between the electrodes on the surface of the insulating substrate. between the plurality of resistive elements and the electrode, which is installed on the insulating substrate so as to selectively cover a part of the electrode together with each resistive element, and is exposed on the front and side surfaces of the insulating substrate. A chip resistor comprising a protective film extending as an insulating member and protruding from an electrode surface.
JP11211983U 1983-07-18 1983-07-18 chip resistor Granted JPS6020110U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11211983U JPS6020110U (en) 1983-07-18 1983-07-18 chip resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11211983U JPS6020110U (en) 1983-07-18 1983-07-18 chip resistor

Publications (2)

Publication Number Publication Date
JPS6020110U JPS6020110U (en) 1985-02-12
JPH0333042Y2 true JPH0333042Y2 (en) 1991-07-12

Family

ID=30260039

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11211983U Granted JPS6020110U (en) 1983-07-18 1983-07-18 chip resistor

Country Status (1)

Country Link
JP (1) JPS6020110U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5820559B2 (en) * 1977-01-17 1983-04-23 株式会社椿本チエイン Induction motor speed control device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5820559U (en) * 1981-07-31 1983-02-08 松下電工株式会社 Electronic components for mounting

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5820559B2 (en) * 1977-01-17 1983-04-23 株式会社椿本チエイン Induction motor speed control device

Also Published As

Publication number Publication date
JPS6020110U (en) 1985-02-12

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