JPH0332053A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0332053A JPH0332053A JP16821589A JP16821589A JPH0332053A JP H0332053 A JPH0332053 A JP H0332053A JP 16821589 A JP16821589 A JP 16821589A JP 16821589 A JP16821589 A JP 16821589A JP H0332053 A JPH0332053 A JP H0332053A
- Authority
- JP
- Japan
- Prior art keywords
- polysilicon
- capacitor
- electrode
- oxide film
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 239000003990 capacitor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000012212 insulator Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 239000008188 pellet Substances 0.000 abstract description 6
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Ceramic Capacitors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体基板上に形成され絶縁物を誘電体とし
て用いたコンデンサに関し、特に、絶縁1勿にノンドー
プポリシリコンを用いたコンデンサを有する半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a capacitor formed on a semiconductor substrate and using an insulator as a dielectric, and particularly to a semiconductor device having a capacitor using non-doped polysilicon as well as an insulator. Regarding.
従来の技術
従来、この種の半導体基板上に形成されるコンデンサは
、第3図に示すように、半導体基板11に不純物をイオ
ン注入または熱拡散によって導入することで形成された
拡散層12とアルミニウム(以下アルミと略記する)電
極15ではさまれた熱酸化またはCVDにより形成され
た酸化11113を誘電体として用いていた。2. Description of the Related Art Conventionally, a capacitor formed on a semiconductor substrate of this type has a diffusion layer 12 formed by introducing impurities into a semiconductor substrate 11 by ion implantation or thermal diffusion, and aluminum, as shown in FIG. Oxide 11113 formed by thermal oxidation or CVD and sandwiched between electrodes 15 (hereinafter abbreviated as aluminum) was used as a dielectric.
発明が解決しようとする課題
上述した従来の半導体基板上に形成されるコンデンサは
、誘電体として酸化膜を用いているので、誘電率が3.
9と小さい為に単位面積当たりのキャパシタンス(C)
は小さくなり、例えばl0PFのコンデンサを酸化膜厚
1000人で形成しようとした場合にはコンデンサの面
積は約30001m2となり、ベレットのかなり大きな
面積を占めていた。Problems to be Solved by the Invention The conventional capacitor formed on a semiconductor substrate as described above uses an oxide film as a dielectric material, and therefore has a dielectric constant of 3.
Since it is small at 9, the capacitance per unit area (C)
For example, if an attempt was made to form a 10PF capacitor with an oxide film thickness of 1000, the area of the capacitor would be approximately 30001 m2, which would occupy a fairly large area of the pellet.
本発明は従来の上記実情に鑑みてなされたものであり、
従って本発明の目的は、従来の技術に内在する上記欠点
を解消し、ベレットを小さくすることを可能とした新規
な半導体装置を提供することにある。The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel semiconductor device that eliminates the above-mentioned drawbacks inherent in the conventional technology and allows the pellet to be made smaller.
発明の従来技術に対する相違点
上述した従来の酸化膜を誘電体として用い半導体基板上
に形成された半導体集積回路の一要素であるコンデンサ
に対し、本発明は、誘電体としてノンドープポリシリコ
ンを使用したという相違点を有する。Differences between the invention and the prior art In contrast to the above-mentioned conventional capacitor, which is an element of a semiconductor integrated circuit formed on a semiconductor substrate using an oxide film as a dielectric, the present invention uses non-doped polysilicon as a dielectric. There is a difference.
課題を解決するための手段
前記目的を達成する為に、本発明に係る絶縁物を誘電体
として用い半導体基板上に形成された半導体集積回路の
一要素であるコンデンサは、絶縁物にノンドープポリシ
リコンを用いたことを特徴として有している。Means for Solving the Problems In order to achieve the above object, a capacitor, which is an element of a semiconductor integrated circuit formed on a semiconductor substrate using an insulator according to the present invention as a dielectric, has non-doped polysilicon as an insulator. It is characterized by the use of
実施例
次に、本発明をその好ましい各実施例について図面を参
照して具体的に説明する。Embodiments Next, preferred embodiments of the present invention will be specifically explained with reference to the drawings.
第1図は本発明による第1の実施例を示す縦断面図であ
る。FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention.
第1図を参照するに、n型半導体基板1にP型不純物を
イオン注入または熱拡散によって導入し、先ず一方の電
!(P型拡散層)を形成し、その後薄いフィールド酸化
JII3を形成した後にスパッタ法によってノンドープ
ポリシリコン4を堆積する0次にポリシリコン4の側面
酸化を行い、最後にアルミを極5を形成する。Referring to FIG. 1, P-type impurities are introduced into an n-type semiconductor substrate 1 by ion implantation or thermal diffusion. (P-type diffusion layer), then form a thin field oxide JII 3, and then deposit non-doped polysilicon 4 by sputtering. Next, perform side oxidation of the polysilicon 4, and finally form aluminum pole 5. .
第2図は本発明による第2の実施例を示す縦断面図であ
る。FIG. 2 is a longitudinal sectional view showing a second embodiment of the present invention.
第2図を参照するに、半導体基板1に形成されたフィー
ルド酸化H3上に、第1の電極としてポリシリコン電極
6を形成し、上記第1の実施例と同様に薄い酸化膜を形
成し、ノンドープポリシリコン4を堆積させ、側面酸化
の後にポリシリコン電極6を形成する。Referring to FIG. 2, a polysilicon electrode 6 is formed as a first electrode on a field oxide H3 formed on a semiconductor substrate 1, and a thin oxide film is formed as in the first embodiment. Non-doped polysilicon 4 is deposited, and after side oxidation, polysilicon electrode 6 is formed.
この第2の実施例では、拡散層を第1の成極として用い
ずに基板とは絶縁されたポリシリコン電極を用いている
為に、拡散層に他の素子を形成でき、−層ペレットの縮
小化に効果がある。In this second embodiment, since the diffusion layer is not used as the first polarization and a polysilicon electrode insulated from the substrate is used, other elements can be formed in the diffusion layer, and the - layer pellet can be formed. Effective in downsizing.
発明の詳細
な説明したように、本発明によれば、半導体基板上に形
成されたコンデンサの誘電体としてノンドープポリシリ
コンを用いることにより、ノンドープポリシリコンの誘
電率が約12である為に単位面積当たりのキャパシタン
ス(C)を酸化膜でコンデンサを形成した場合の約3倍
にすることができ、例えば10pFのコンデンサを膜厚
1000人のポリシリコンで形成しようとした場合にコ
ンデンサの面積は約940#+1”となり、酸化膜でコ
ンデンサを形成した場合の約1/3となり、ベレットを
縮小できる効果が得られる。As described in detail, according to the present invention, non-doped polysilicon is used as the dielectric of a capacitor formed on a semiconductor substrate, and since the dielectric constant of non-doped polysilicon is about 12, the unit area can be reduced. The capacitance (C) per unit can be approximately three times that of a capacitor formed using an oxide film.For example, if a 10 pF capacitor is formed using polysilicon with a film thickness of 1000 mm, the area of the capacitor will be approximately 940 mm. #+1'', which is about 1/3 of that in the case where the capacitor is formed with an oxide film, and it is possible to achieve the effect of reducing the size of the pellet.
第1図は本発明による第1の実施例を示す縦断面図、第
2図は本発明による第2の実施例を示す縦断面図、第3
図は従来におけるこの種のコンデンサを示す縦断面図で
ある。
1.11・・・n型半導体基板、2,12・・・P型拡
散層、3,13・・・フィールド酸化膜、4・・・ノン
ドープポリシリコン、5.15・・・アルミ電極、6・
・・ポリシリコン電極FIG. 1 is a longitudinal cross-sectional view showing a first embodiment of the present invention, FIG. 2 is a longitudinal cross-sectional view showing a second embodiment of the present invention, and FIG.
The figure is a longitudinal sectional view showing a conventional capacitor of this type. 1.11... N-type semiconductor substrate, 2, 12... P-type diffusion layer, 3, 13... Field oxide film, 4... Non-doped polysilicon, 5.15... Aluminum electrode, 6・
・Polysilicon electrode
Claims (1)
半導体集積回路の一要素であるコンデンサにおいて、絶
縁物にノンドープポリシリコンを用いたことを特徴とす
る半導体装置。1. A semiconductor device characterized in that, in a capacitor that is an element of a semiconductor integrated circuit formed on a semiconductor substrate using an insulator as a dielectric, non-doped polysilicon is used as the insulator.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16821589A JPH0332053A (en) | 1989-06-28 | 1989-06-28 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16821589A JPH0332053A (en) | 1989-06-28 | 1989-06-28 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0332053A true JPH0332053A (en) | 1991-02-12 |
Family
ID=15863923
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16821589A Pending JPH0332053A (en) | 1989-06-28 | 1989-06-28 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0332053A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7023038B2 (en) * | 2004-06-08 | 2006-04-04 | Fuh-Cheng Jong | Silicon barrier capacitor device structure |
-
1989
- 1989-06-28 JP JP16821589A patent/JPH0332053A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7023038B2 (en) * | 2004-06-08 | 2006-04-04 | Fuh-Cheng Jong | Silicon barrier capacitor device structure |
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