JPH0213465B2 - - Google Patents
Info
- Publication number
- JPH0213465B2 JPH0213465B2 JP55154861A JP15486180A JPH0213465B2 JP H0213465 B2 JPH0213465 B2 JP H0213465B2 JP 55154861 A JP55154861 A JP 55154861A JP 15486180 A JP15486180 A JP 15486180A JP H0213465 B2 JPH0213465 B2 JP H0213465B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- capacitance
- semiconductor substrate
- floating electrode
- variable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 24
- 238000009792 diffusion process Methods 0.000 claims description 23
- 239000003990 capacitor Substances 0.000 claims description 17
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 20
- 230000001590 oxidative effect Effects 0.000 description 6
- 238000009413 insulation Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/93—Variable capacitance diodes, e.g. varactors
Description
【発明の詳細な説明】
本発明は電子回路に用いられる半導体可変容量
素子の構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a semiconductor variable capacitance element used in an electronic circuit.
従来、水晶発振器等に用いられる可変容量（ト
リマーコンデンサ）としてはセラミツクトリマー
コンデンサが知られていたが、半導体を用いた実
用的な可変容量素子はなかつた。 Conventionally, ceramic trimmer capacitors have been known as variable capacitors (trimmer capacitors) used in crystal oscillators, etc., but there have been no practical variable capacitors using semiconductors.
本発明は、半導体を用いた実用的な可変容量素
子を実現するものである。 The present invention realizes a practical variable capacitance element using a semiconductor.
以下、本発明の実施例を図面を用いて詳細に説
明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
半導体基板上に絶縁膜で覆われ外部より絶縁さ
れた浮遊電極を有し、浮遊電極の電荷を蓄積する
ことによつて容量を可変する本発明の第１実施例
である半導体可変容量（容量電極４と７の間の容
量）素子が、第１図ａとｂに示される。第１図ａ
はその平面図、第１図ｂはその断面図である。こ
の構造では、浮遊電極３とｎ−導電型の半導体基
板１の表面間の容量を決定する部分の浮遊電極面
積S1と絶縁酸化膜３０の厚みtox１、および容量
電極４と浮遊電極３の間の容量を決定する部分の
容量電極面積S2と絶縁酸化膜３１の厚みtox２と
するとS1，S2，tox１，tox２の４つによつて容
量素子の容量（容量電極４と７の間の容量）の最
大値が決定される。なお、５はＰ−型拡散層、６
は浮遊電極３に電荷を注入したり、引き出したり
するためのｎ＋型拡散領域である容量可変電極で
あり、７はＰ−型拡散層で形成される第２の容量
電極である。 A semiconductor variable capacitor (capacitance electrode) is a semiconductor variable capacitor (a semiconductor variable capacitor), which is a first embodiment of the present invention, which has a floating electrode covered with an insulating film and insulated from the outside on a semiconductor substrate, and whose capacitance is varied by accumulating charge on the floating electrode. A capacitance between 4 and 7) elements are shown in FIGS. 1a and b. Figure 1a
1 is a plan view thereof, and FIG. 1b is a sectional view thereof. In this structure, the floating electrode area S 1 is the part that determines the capacitance between the floating electrode 3 and the surface of the n-conductivity type semiconductor substrate 1, the thickness tox1 of the insulating oxide film 30, and the space between the capacitive electrode 4 and the floating electrode 3. Assuming that the capacitive electrode area S 2 and the thickness tox2 of the insulating oxide film 31 determine the capacitance of the capacitive element, the capacitance of the capacitive element (between the capacitive electrodes 4 and 7) is determined by S 1 , S 2 , tox1, and tox2. The maximum value of capacity) is determined. Note that 5 is a P-type diffusion layer, and 6 is a P-type diffusion layer.
7 is a variable capacitance electrode which is an n+ type diffusion region for injecting and extracting charges into the floating electrode 3, and 7 is a second capacitance electrode formed of a P− type diffusion layer.
小型で、かつ、容量最大値を大きくするには絶
縁酸化膜３０，３１の厚みtox１，tox２を薄く
すれば良い。単結晶シリコンである半導体基板１
を熱酸化して得られる絶縁酸化膜３０の厚みtox
１は、50Å程度の薄い膜でも良好な絶縁特性を持
つている。しかし、ポリシリコンでできた浮遊電
極３を熱酸化して得る絶縁酸化膜３１の厚みtox
２は絶縁性がきわめて悪いので、浮遊電極３に蓄
積した電荷の消失を起さない実用的な絶縁性を得
るために、絶縁酸化膜３１の厚みtox２は2000Å
程度のかなり厚く形成される。 In order to reduce the size and increase the maximum capacitance, the thicknesses tox1 and tox2 of the insulating oxide films 30 and 31 may be reduced. Semiconductor substrate 1 made of single crystal silicon
The thickness of the insulating oxide film 30 obtained by thermally oxidizing
1 has good insulation properties even when the film is as thin as 50 Å. However, the thickness of the insulating oxide film 31 obtained by thermally oxidizing the floating electrode 3 made of polysilicon is
2 has extremely poor insulating properties, so in order to obtain practical insulating properties that do not cause the loss of charge accumulated in the floating electrode 3, the thickness tox2 of the insulating oxide film 31 is set to 2000 Å.
It is formed quite thickly.
したがつて、可変容量素子の容量最大値を大き
くするためには、容量電極面積S2を大きくしなけ
ればならず、大型にならざるを得ない。 Therefore, in order to increase the maximum capacitance value of the variable capacitance element, the capacitive electrode area S 2 must be increased, which necessitates an increase in size.
本発明の第２実施例はこの点を更に改善した、
小型で、かつ、容量最大値の大きな半導体可変容
量素子を提供するものである。 The second embodiment of the present invention further improves this point.
The present invention provides a semiconductor variable capacitance element that is small in size and has a large maximum capacitance.
第２図は、本発明の第２実施例を示す図であ
る。第２図ａはその平面図、第２図ｂはその断面
図である。以下、この第２実施例を具体的に説明
する。 FIG. 2 is a diagram showing a second embodiment of the present invention. FIG. 2a is a plan view thereof, and FIG. 2b is a sectional view thereof. This second embodiment will be explained in detail below.
ｎ−導電型の半導体基板８上に絶縁酸化膜９で
覆われ外部より絶縁された浮遊電極１０がある。
半導体基板８の表面には浮遊電極１０の一部と対
して、Ｐ−型拡散層１１が形成され、Ｐ−型拡散
層１１内に容量電極１２がｎ＋型拡散層で形成さ
れている。さらに、基板８の表面にはＰ−型拡散
層１３が形成され、その内部に容量可変端子のｎ
＋型拡散層１４が形成されている。 A floating electrode 10 is provided on an n-conductivity type semiconductor substrate 8 and is covered with an insulating oxide film 9 and insulated from the outside.
A P- type diffusion layer 11 is formed on the surface of the semiconductor substrate 8 for a part of the floating electrode 10, and a capacitor electrode 12 is formed as an n+ type diffusion layer within the P- type diffusion layer 11. Further, a P-type diffusion layer 13 is formed on the surface of the substrate 8, and a capacitance variable terminal n
A + type diffusion layer 14 is formed.
容量電極１２をＰ−型拡散層１１内にｎ＋型の
拡散層によつて形成することによつて、浮遊電極
１０と容量電極１２との間の絶縁酸化膜３３の厚
みtox２は半導体基板８である単結晶シリコンを
熱酸化することによつて得られる。単結晶シリコ
ンを熱酸化して得られる酸化膜性にすぐれ、50Å
程度の薄い膜でも充分な絶縁性が得られる。した
がつて、浮遊電極１０と容量電極１２との間の容
量は、酸化膜３３の厚みを薄くすることにより、
電極面積を小さくしても充分大きな値を得られ
る。なお、Ｐ−型拡散層１１は容量電極１２と半
導体基板８との間に生じる寄生容量を減らすため
の拡散層で、Ｐ−型拡散層１１によつて容量電極
１２と半導体基板８との間の寄生容量はほぼ無視
できる。 By forming the capacitor electrode 12 as an n+ type diffusion layer within the P- type diffusion layer 11, the thickness tox2 of the insulating oxide film 33 between the floating electrode 10 and the capacitor electrode 12 can be reduced by the semiconductor substrate 8. Obtained by thermally oxidizing certain single crystal silicon. Excellent oxide film properties obtained by thermally oxidizing single crystal silicon, 50 Å
Sufficient insulation can be obtained even with a relatively thin film. Therefore, the capacitance between the floating electrode 10 and the capacitive electrode 12 can be reduced by reducing the thickness of the oxide film 33.
A sufficiently large value can be obtained even if the electrode area is made small. Note that the P-type diffusion layer 11 is a diffusion layer for reducing parasitic capacitance generated between the capacitor electrode 12 and the semiconductor substrate 8. The parasitic capacitance of is almost negligible.
実際、最大容量を30pF程度にする場合、本発
明の第１実施例の構造では約0.5mm2の大きさとな
り、本発明の第２実施例の構造では絶縁酸化膜３
３の厚みtox２を200Åとして、約半分の大きさ
が実現できる。すなわち基板８の表面を酸化して
できる酸化膜３３の厚みは本発明の第１実施例よ
り非常に薄くなる。 In fact, when the maximum capacitance is about 30 pF, the structure of the first embodiment of the present invention has a size of about 0.5 mm2 , and the structure of the second embodiment of the present invention requires an insulating oxide film 3.
By setting the thickness tox2 of 3 to 200 Å, approximately half the size can be achieved. That is, the thickness of the oxide film 33 formed by oxidizing the surface of the substrate 8 is much thinner than in the first embodiment of the present invention.
また、本発明の第２実施例の構造では、浮遊電
極１０と容量電極１２との間の絶縁酸化膜３３の
厚みtox２と浮遊電極１０と半導体基板８の表面
との間の絶縁酸化膜３２の厚みtox１を同時に作
ることも可能で、製造プロセスも本発明の第１実
施例に較べて簡単になり、量産性にすぐれてい
る。 In the structure of the second embodiment of the present invention, the thickness tox2 of the insulating oxide film 33 between the floating electrode 10 and the capacitor electrode 12 and the thickness tox2 of the insulating oxide film 32 between the floating electrode 10 and the surface of the semiconductor substrate 8 are It is also possible to simultaneously manufacture the thickness tox1, and the manufacturing process is simpler than in the first embodiment of the present invention, resulting in excellent mass productivity.
第３図ａ，ｂは本発明の第３実施例を示す図で
ある。第３図ａはその平面図、第３図ｂはその断
面図である。 FIGS. 3a and 3b are diagrams showing a third embodiment of the present invention. FIG. 3a is a plan view thereof, and FIG. 3b is a sectional view thereof.
ｎ−型の半導体基板１５上に絶縁酸化膜１６で
覆われ外部より絶縁された浮遊電極１７がある。
半導体基板１５の表面には浮遊電極１７に蓄積し
た電荷によつて表面の状態が蓄積、空乏、反転す
るＰ−型拡散層のＰ−ウエル１８が形成されてい
る。また半導体基板１５の表面には浮遊電極１７
の一部と相対して、容量電極となるＰ＋型拡散層
１９が形成されている。さらに半導体基板１５の
Ｐ−ウエル１８、Ｐ＋型拡散層１９外の表面には
Ｐ−型拡散層２０が形成され、Ｐ−型拡散層２０
の中には、容量可変のために浮遊電極１７に電荷
を注入もしくは引き出すための容量可変のための
電極となるｎ＋型拡散層２１が形成されている。
すなわち可変電極２１（ｎ＋型拡散層）と浮遊電
極１７との間の電子のやりとりにより容量電極１
９とＰーウエル１８との間の容量を可変する。 A floating electrode 17 is provided on an n-type semiconductor substrate 15 and is covered with an insulating oxide film 16 and insulated from the outside.
A P-well 18 is formed on the surface of the semiconductor substrate 15, which is a P-type diffusion layer whose surface state is accumulated, depleted, or reversed by the charges accumulated in the floating electrode 17. Furthermore, a floating electrode 17 is provided on the surface of the semiconductor substrate 15.
A P+ type diffusion layer 19, which serves as a capacitor electrode, is formed opposite to a part of the capacitor. Furthermore, a P- type diffusion layer 20 is formed on the surface of the semiconductor substrate 15 outside the P-well 18 and the P+ type diffusion layer 19.
An n+ type diffusion layer 21 is formed therein to serve as a capacitance variable electrode for injecting or extracting charges into or out of the floating electrode 17 for capacitance variation.
That is, due to the exchange of electrons between the variable electrode 21 (n+ type diffusion layer) and the floating electrode 17, the capacitive electrode 1
9 and the P-well 18.
第３図に示した本発明の第３実施例も第２図に
示した本発明の第２実施例と同じく、容量電極１
９が半導体基板１５の表面の拡散層として形成さ
れていため、容量電極１９と浮遊電極１７との間
の絶縁酸化膜３４の厚みtox２は薄くしても充分
絶縁性にすぐれたものができ、小型で、かつ、最
大容量の大きな半導体可変容量素子が得られる。
すなわち容量電極１９が作られているシリコン半
導体基板１５の表面を酸化して成る絶縁酸化膜は
よい絶縁性を持つている。 The third embodiment of the present invention shown in FIG. 3 is similar to the second embodiment of the present invention shown in FIG.
Since 9 is formed as a diffusion layer on the surface of the semiconductor substrate 15, even if the thickness tox2 of the insulating oxide film 34 between the capacitive electrode 19 and the floating electrode 17 is made thin, a product with sufficient insulation properties can be achieved, resulting in a small size. Thus, a semiconductor variable capacitance element with a large maximum capacity can be obtained.
That is, the insulating oxide film formed by oxidizing the surface of the silicon semiconductor substrate 15 on which the capacitor electrode 19 is formed has good insulation properties.
なお、第３図の本発明の第３実施例では、利用
する容量は、容量電極１９とＰ−ウエル１８の間
の容量である。 In the third embodiment of the present invention shown in FIG. 3, the capacitance utilized is the capacitance between the capacitor electrode 19 and the P-well 18.
また、第２図の本発明の第２実施例、第３図の
本発明の第３実施例の双方とも、Ｐ型をｎ型、ｎ
型をＰ型におきかえても、同等であることは自明
である。 Furthermore, in both the second embodiment of the present invention shown in FIG. 2 and the third embodiment of the present invention shown in FIG.
It is obvious that they are equivalent even if the type is changed to P type.
以上の説明で明らかなように、本発明によれば
小型で、かつ、最大容量が大きく、量産性にすぐ
れた半導体可変容量素子が実現できる。 As is clear from the above description, according to the present invention, it is possible to realize a semiconductor variable capacitance element that is small in size, has a large maximum capacity, and is excellent in mass production.
第１図ａは本発明の第１実施例の半導体可変容
量素子の平面図であり、第１図ｂはその断面図で
ある。第２図ａは本発明の第２実施例の平面図で
あり、第２図ｂはその断面図である。第３図ａは
本発明の第３実施例の平面図であり、第３図ｂは
その断面図である。
１，８，１５……半導体基板、２，９……絶縁
酸化膜、３，１０，１７……浮遊電極、４，１
２，１９……容量電極、１１……Ｐ−型拡散層、
１４，２０……容量可変端子、１８……Ｐ−ウエ
ル。
FIG. 1a is a plan view of a semiconductor variable capacitance element according to a first embodiment of the present invention, and FIG. 1b is a sectional view thereof. FIG. 2a is a plan view of a second embodiment of the invention, and FIG. 2b is a sectional view thereof. FIG. 3a is a plan view of a third embodiment of the present invention, and FIG. 3b is a sectional view thereof. 1, 8, 15... Semiconductor substrate, 2, 9... Insulating oxide film, 3, 10, 17... Floating electrode, 4, 1
2, 19...capacitance electrode, 11...P-type diffusion layer,
14, 20... Capacitance variable terminal, 18... P-well.
Claims (1)
下の第１の導電型の半導体基板の表面部分に前記
半導体基板とは逆導電型の第１のウエルを形成す
ると共に前記第１のウエル内の表面部分に形成さ
れた前記半導体基板と同じ導電型の第１の拡散領
域からなつて前記浮遊電極と容量結合をなす容量
電極と、前記浮遊電極下の前記半導体基板の前記
容量電極外の表面部分に前記半導体基板とは逆導
電型の第２のウエルを形成すると共に前記第２の
ウエル内の表面部分に前記半導体基板と同じ導電
型の第２の拡散領域を形成して成る容量可変電極
とから成り、前記容量可変電極に正負の容量可変
電圧を印加することにより、前記浮遊電極に電荷
を注入するまたは引き出して前記浮遊電極下の前
記半導体基板の前記容量電極及び前記第１および
第２のウエル外の表面部分に形成される空乏層の
容量を増減させて前記容量電極と前記空乏層が形
成される領域との間から正負にアナログ的に変化
する種々の容量値を得る半導体可変容量素子。 ２ 前記浮遊電極と容量可変電極との間の前記絶
縁膜を流れるトンネル注入によつて前記浮遊電極
に電荷を注入または引き出す特許請求の範囲第１
項記載の半導体可変容量素子。[Claims] 1. A floating electrode surrounded by an insulating film, and a first well of a conductivity type opposite to that of the semiconductor substrate is formed in a surface portion of a semiconductor substrate of a first conductivity type below the floating electrode. and a capacitive electrode formed on a surface portion of the first well and formed of a first diffusion region of the same conductivity type as the semiconductor substrate and capacitively coupled to the floating electrode, and the semiconductor substrate below the floating electrode. A second well having a conductivity type opposite to that of the semiconductor substrate is formed in a surface portion outside the capacitor electrode, and a second diffusion region having the same conductivity type as the semiconductor substrate is formed in a surface portion inside the second well. By applying positive and negative capacitance variable voltages to the capacitance variable electrode, charges are injected into or drawn out from the floating electrode, and the capacitance electrode of the semiconductor substrate under the floating electrode is injected or extracted. and various types of capacitances that increase or decrease the capacitance of the depletion layer formed in the surface portion outside the first and second wells and change in positive or negative analog manner from between the capacitance electrode and the region where the depletion layer is formed. Semiconductor variable capacitance element that obtains capacitance value. 2. Charge is injected into or drawn out from the floating electrode by tunnel injection flowing through the insulating film between the floating electrode and the variable capacitance electrode.
The semiconductor variable capacitance element described in .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15486180A JPS5778181A (en) | 1980-11-04 | 1980-11-04 | Semiconductor variable capacity element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15486180A JPS5778181A (en) | 1980-11-04 | 1980-11-04 | Semiconductor variable capacity element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5778181A JPS5778181A (en) | 1982-05-15 |
| JPH0213465B2 true JPH0213465B2 (en) | 1990-04-04 |
Family
ID=15593511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15486180A Granted JPS5778181A (en) | 1980-11-04 | 1980-11-04 | Semiconductor variable capacity element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5778181A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01125987A (en) * | 1987-11-11 | 1989-05-18 | Seiko Instr & Electron Ltd | Semiconductor variable capacitance device |
| US5248891A (en) * | 1988-03-25 | 1993-09-28 | Hiroshi Takato | High integration semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53115185A (en) * | 1977-03-17 | 1978-10-07 | Sanyo Electric Co Ltd | Memory type variable capacitive device |
| JPS53135235A (en) * | 1977-04-30 | 1978-11-25 | Toshiba Corp | Nonvolatile memory array |
-
1980
- 1980-11-04 JP JP15486180A patent/JPS5778181A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53115185A (en) * | 1977-03-17 | 1978-10-07 | Sanyo Electric Co Ltd | Memory type variable capacitive device |
| JPS53135235A (en) * | 1977-04-30 | 1978-11-25 | Toshiba Corp | Nonvolatile memory array |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5778181A (en) | 1982-05-15 |
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