JPS59125654A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59125654A JPS59125654A JP58000345A JP34583A JPS59125654A JP S59125654 A JPS59125654 A JP S59125654A JP 58000345 A JP58000345 A JP 58000345A JP 34583 A JP34583 A JP 34583A JP S59125654 A JPS59125654 A JP S59125654A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductive layer
- unit
- charge
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
不発明は、半導体装置にかかシ、特に薄い絶縁膜をもつ
コンデンサーと電界効果トランジスタとを情報記憶単位
とする半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, particularly a semiconductor device in which a capacitor having a thin insulating film and a field effect transistor are used as information storage units.
1 (ffllのコンテンサーと1個のトランジスタよ
構成るいわゆる1トランジスタ型メモリーセルは大容量
メモリーの最も一般的な記憶単位として使用されている
が、大容量化、高集積化への技術進歩とともに、年々微
細化の一途をたどっておシ、コンデンツ″−1個あたシ
に必要とされる面招も減少を余儀なくされている。1 (The so-called one-transistor memory cell, which is composed of an FFLL capacitor and one transistor, is used as the most common storage unit for large-capacity memory, but as technology advances toward larger capacity and higher integration, With the progress of miniaturization year by year, the amount of space required for one piece of content has been forced to decrease.
しかしながら、情報蓄積に必要とされる十分々容量値は
確保しなければならず、必然的に容量の対極間の絶縁膜
はよシ薄く々ってゆかざるを得なくなって来ている。However, it is necessary to ensure a sufficient capacitance value required for information storage, and as a result, the insulating film between the opposite electrodes of the capacitor has to become thinner and thinner.
ところがよシ薄い絶縁膜では絶縁耐圧がよシ低くカシ、
コンテンサーーの一方の対極である導電層が半導体基板
から電気的に絶縁されている場合には、例等かのチャー
ジアップが起こって導電層上に電荷が誘起された場合、
一番弱い場所であるメモリーセルのコンテンサ一部で絶
縁破壊を起こし易くなる。絶縁破壊が起こって、半導体
基板とショートが起こってしまえは、それ以上チャージ
アップが起こることはなくなるのであるが、1箇所でも
絶縁破壊が起これば、他のメモリーセルが正常動作をし
ていても、その1ビツトの不良のために半導体装置とし
ての機能は損なわれることとなる。However, a thinner insulating film has a lower dielectric strength.
If the conductive layer, which is one opposite electrode of the capacitor, is electrically insulated from the semiconductor substrate, for example, if charge-up occurs and charges are induced on the conductive layer,
Dielectric breakdown is likely to occur in a part of the capacitor of the memory cell, which is the weakest point. Once dielectric breakdown occurs and a short circuit occurs with the semiconductor substrate, no further charge-up occurs, but if dielectric breakdown occurs even in one place, other memory cells may be operating normally. However, due to that one bit defect, the function as a semiconductor device will be impaired.
不発明は斯かる不都合を解決するものである。Non-invention is a solution to such inconveniences.
不発明の構成は半導体基板上に形成された電界効果トラ
ンジスタと一層または多層の絶縁層をもつ第1の容量部
を少くとも電荷蓄積の一部に用いるコンテンツ゛−とで
情報記憶単位を構成する半導体装置であって、該第1の
容量部の一方の対極を含む導電層の一部金一方の対極と
し、該穿1の容量部以外の領域で、該第1の容量部の絶
縁層よシ絶縁耐圧が低い絶縁層をもつM2の容量部を有
することを特徴とする半導体装置でおる。The uninvented structure is a semiconductor in which an information storage unit is composed of a field effect transistor formed on a semiconductor substrate and a content that uses a first capacitor section having one or more insulating layers for at least part of charge storage. In the apparatus, part of the conductive layer including one counter electrode of the first capacitive part is made of gold as one counter electrode, and the insulating layer and the silicon of the first capacitive part are formed in a region other than the capacitive part of the hole 1. This semiconductor device is characterized by having an M2 capacitor portion having an insulating layer with a low dielectric strength voltage.
次に図によって、不発明の詳細な説明を行9゜第4図は
不発明の一実施例を示したものである。Next, a detailed explanation of the invention will be given with reference to the drawings. FIG. 4 shows an embodiment of the invention.
第1図中、1は半導体基板、2は基板と逆導電型の不純
物を拡散し′た不純物拡散層、3は反転層、4は二酸化
珪素膜よ構成る絶縁層、5は不純物をドープした多結晶
シリコンよシなる1ffi目の導電層、6は同じく不純
物をドープした多結晶シリコンよシなる2層目の導電層
である。電界効果トランジスタは不純物拡散層2、反転
層3がソースドレインとして働き二酸化珪素膜のゲート
絶縁膜7を介した2層目の導電層6がゲートとして構成
される。第1の容量部は、反転層6と二酸化珪素膜の誘
電体膜8を介したIN目の導電層5とに構成され、図中
Iで示された領域である。そして図中■で示された領域
は■の領域より薄い二酸化珪素膜9を介して、2層目の
導電N6と反転層3′の間で構成された第2の容量部で
ある。第1図はウェハー処理工程途中の状態を示してい
るが、もし、この状態で1層目の導電層に電荷が誘起し
たとすると、絶縁耐圧がよシ弱い■の領域の第2の容量
部に絶縁破壊が起こる。その結果IN目の導を層の電荷
は半導体基板中に流れて、それ以上のチャージアップは
防止され、情報記憶部分として働く領域Iの第1の容量
部は保護されることとなる。In Figure 1, 1 is a semiconductor substrate, 2 is an impurity diffusion layer in which impurities of the opposite conductivity type to the substrate are diffused, 3 is an inversion layer, 4 is an insulating layer composed of a silicon dioxide film, and 5 is an impurity doped layer. The 1ffi conductive layer is made of polycrystalline silicon, and 6 is the second conductive layer made of polycrystalline silicon doped with impurities. In the field effect transistor, an impurity diffusion layer 2 and an inversion layer 3 function as a source/drain, and a second conductive layer 6 with a gate insulating film 7 of silicon dioxide film interposed therebetween serves as a gate. The first capacitor section is constituted by an inversion layer 6 and an IN-th conductive layer 5 with a dielectric film 8 of a silicon dioxide film interposed therebetween, and is a region indicated by I in the figure. In the figure, a region indicated by a square mark is a second capacitor section formed between the second conductive layer N6 and the inversion layer 3' via a silicon dioxide film 9 which is thinner than the region marked by a square mark. Figure 1 shows the state in the middle of the wafer processing process, but if charges were to be induced in the first conductive layer in this state, the second capacitive part in the region (■) where the dielectric strength voltage is weaker would be dielectric breakdown occurs. As a result, the charges in the IN-th conductive layer flow into the semiconductor substrate, and further charge-up is prevented, and the first capacitor section in region I, which functions as an information storage section, is protected.
ところでこの第2の容量部での絶縁破壊は弱い部分でピ
ンホール状に起こる事が知られており、絶縁破壊後に導
電層のチャージを基板側に流すには十分率さい抵抗では
あるが、半導体装置完成後に1層目の導電層5と半導体
基板間に半導体装置動作上必黴な電圧を印加した場合に
、両者間に流れる電流が規格を起えないよう十分大きい
抵抗となし得る。この第2の容量部は各単位セルごとに
設ける必要は力く1層目の導電層5の連続的な一平面に
対して少くとも1個この第2の容量部をもうければよい
ことは言うまでもない。By the way, it is known that dielectric breakdown in this second capacitor part occurs in the form of a pinhole at a weak point, and although the resistance is low enough to allow the charge in the conductive layer to flow to the substrate side after dielectric breakdown, the semiconductor When a voltage necessary for the operation of the semiconductor device is applied between the first conductive layer 5 and the semiconductor substrate after the device is completed, the resistance can be made sufficiently large so that the current flowing between the two does not exceed the standard. It is not necessary to provide this second capacitance section for each unit cell; it is sufficient to provide at least one second capacitance section for one continuous plane of the first conductive layer 5. Needless to say.
第1図は不発明の実施例の半導体装置の途中フ。
ロセスの構造を示している。
各部位はそれぞれ以下の通夛である。
1・・・・・・半導体基板、2・・・・・基板と逆導電
型の不純物拡散層、3・・・・・反転層、4・・・・・
・二酸化珪素膜よシなる絶縁層(フィールド絶縁層)、
5・・・・・・1層目の導電層、6・・・・2層目の導
電層、■・・・・・・第1の容量部、■・・・・・第2
の容量部、7・・・・・・ゲート絶縁膜、8・・・・・
・第1の容量部の誘電体膜、9・・・・・・第2の容量
部の誘電体膜。FIG. 1 is an intermediate view of a semiconductor device according to an embodiment of the present invention. It shows the structure of the process. Each part has the following conventions. 1... Semiconductor substrate, 2... Impurity diffusion layer of conductivity type opposite to that of the substrate, 3... Inversion layer, 4...
・Insulating layer (field insulating layer) such as silicon dioxide film,
5...First conductive layer, 6...Second conductive layer, ■...First capacitor section, ■...Second conductive layer
capacitive part, 7...gate insulating film, 8...
- Dielectric film of the first capacitive part, 9... Dielectric film of the second capacitive part.
Claims (1)
または多層の絶縁層をもつ第1の容量部を少くとも電荷
蓄積の一部に用いるコンデンサーとで情報記憶単位を構
成する半導体装置において、該第1の容量部の一方の対
極を含む導電層の一部を一方の対極とし、該第1の容量
部以外の領域で、該第1の容量部の絶縁層よシ絶縁耐圧
が低い絶縁層をもつ第2の容量部を有することを特徴と
する半導体装置。In a semiconductor device in which an information storage unit is constituted by a field effect transistor formed on a semiconductor substrate and a capacitor that uses a first capacitance section having one or multiple insulating layers for at least part of charge storage, the first A part of the conductive layer including one counter electrode of the capacitive part is used as one counter electrode, and an insulating layer having a lower dielectric strength voltage than the insulating layer of the first capacitive part is provided in a region other than the first capacitive part. A semiconductor device comprising a second capacitor section.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58000345A JPS59125654A (en) | 1983-01-05 | 1983-01-05 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58000345A JPS59125654A (en) | 1983-01-05 | 1983-01-05 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59125654A true JPS59125654A (en) | 1984-07-20 |
Family
ID=11471266
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58000345A Pending JPS59125654A (en) | 1983-01-05 | 1983-01-05 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59125654A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4924278A (en) * | 1987-06-19 | 1990-05-08 | Advanced Micro Devices, Inc. | EEPROM using a merged source and control gate |
JP2007194424A (en) * | 2006-01-19 | 2007-08-02 | Matsushita Electric Ind Co Ltd | Protection element and its manufacturing method |
US7851891B2 (en) | 2003-01-14 | 2010-12-14 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS509389A (en) * | 1973-05-22 | 1975-01-30 | ||
JPS56107390A (en) * | 1980-01-29 | 1981-08-26 | Nec Corp | Semiconductor memory device |
JPS5762564A (en) * | 1980-09-30 | 1982-04-15 | Seiko Epson Corp | Tunnel effect type protecting device |
-
1983
- 1983-01-05 JP JP58000345A patent/JPS59125654A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS509389A (en) * | 1973-05-22 | 1975-01-30 | ||
JPS56107390A (en) * | 1980-01-29 | 1981-08-26 | Nec Corp | Semiconductor memory device |
JPS5762564A (en) * | 1980-09-30 | 1982-04-15 | Seiko Epson Corp | Tunnel effect type protecting device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4924278A (en) * | 1987-06-19 | 1990-05-08 | Advanced Micro Devices, Inc. | EEPROM using a merged source and control gate |
US7851891B2 (en) | 2003-01-14 | 2010-12-14 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
JP2007194424A (en) * | 2006-01-19 | 2007-08-02 | Matsushita Electric Ind Co Ltd | Protection element and its manufacturing method |
US8026552B2 (en) | 2006-01-19 | 2011-09-27 | Panasonic Corporation | Protection element and fabrication method for the same |
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