JPH0331710A - Absolute encoder - Google Patents

Abstract

PURPOSE:To highly accurately detect a position by latching the input time of a control synchronizing signal. CONSTITUTION:A counter 11 counts up time longer than the period of a control synchronizing signal inputted from the external. A comparator 31 detects zero in an output signal ef0 whose phase is changed in accordance with a position obtained from a resolver 61 and sends a latch instruction to a latch circuit 41 at the detecting timing. The circuit 41 latches the counting position RDn of the counter 11 which indicates the detecting time and position based upon the latch instruction and sends the latched result to a latch circuit 42. The circuit 42 latches the counted value RDn based upon the control synchronizing signal SQ and sends the latched result to a computing element 51. A latch circuit 43 sends the precedently latched counted value RDn-1 to the computing element 51 based upon the signal SQ. A latch circuit 44 latches a counted value TDn indicating the input time of the signal SQ based upon the signal SQ and sends the latched result to the computing element 51. The computing element 51 outputs position data R0 for a current command from these counted values.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an absolute encoder that is used for position control, speed control, etc., and detects a position in synchronization with a control synchronization signal.

(Prior Art) A resolver is usually used to detect the position of each axis of a machine tool, etc.

FIG. 3 is a block diagram showing an example of an absolute encoder using a conventional resolver, and FIG. 4 is a timing chart showing an example of its operation.

The counter 12 counts the counter clock inside the counter up to a value PP of 2'''*l-s (m, a natural number), and synchronizes it with the count value CT to create a control equivalent signal SQ and output it to the outside. Output. Excitation 1 + i (
The circuit 21 uses the count value CT from the counter 12 to generate a two-phase excitation signal ef synchronized with the control synchronization signal No. 8 SQ,
, ef2 are generated and sent to the resolver 61. The resolver 61 receives two-phase excitation signals ef, , e from the excitation circuit 21.
Output signal ef whose phase changes depending on the position based on f2
o is sent to the comparator 31. The comparator 31 detects the output signal efo from the resolver 61 and issues a latch command to the latch circuit 45 at this detection timing.
41i respectively. The latch circuit 45 latches the count value PD of the counter 12 in response to a latch command from the comparator 31 and sends it to the arithmetic unit 52. This count value PD is composed of the count value CT and the excitation signal ef.
, and the control synchronization signal SQ are synchronized, so they represent the detection time and the detection position. However, since the detection time changes depending on the detection position, the detection position is not synchronized with the control synchronization signal SQ.

The latch circuit 46 receives the latch command from the comparator 31 and the latch circuit 45 latches the counter 12 last time.
The count value pan-+ is latched and sent to the arithmetic unit 52. The computing unit 52 substitutes the count value TF at the time of current command to the motor that drives the axis and the count values PDn, PD, l from the latch circuit 45.46 into the following equation (1) to synchronize with the control synchronization signal SQ. The position data PO at the time of the current command is determined and output to the outside.

Note that ΔP: distance traveled from PDo-1 to PD (problem to be solved by the invention) The conventional absolute encoder described above generates a control synchronization signal using its internal counter. Therefore, for example, when absolute encoders are attached to each of a plurality of axes to detect the position, the same excitation signal and count value as the absolute encoder generating the control synchronization signal must be used for the other absolute encoders. However, when each axis has a different purpose, it is necessary to change the frequency of the resolver's excitation signal and the counter's clock according to the purpose of each axis, and all absolute encoders attached to each axis have the same excitation signal and The drawback was that the count value could not be shared.

The present invention was made in view of the above-mentioned circumstances, and an object of the present invention is to provide a versatile absolute encoder that is independent as a unit.

(Means for Solving the Problems) The present invention relates to an absolute encoder that is used for position control, speed control, etc. and detects a position in synchronization with a control synchronization signal. a counting means for counting a time longer than a cycle of the control synchronization signal; a position detecting means for detecting a position; and a first storage means for storing the count value of the counting means at the detection timing of the position detecting means. , a second storage means for storing the count value of the counting means in response to a control synchronization signal from the outside, a speed detection means for determining a moving speed based on a position detection value from the position detection means, and a storage means of the 5iSx. , the count value from the second storage means, the position detection value from the position detection means, the speed detection value from the speed detection means, and the time up to the current command. This is achieved by comprising a calculation means for determining and outputting a position synchronized with the .

(Function) Since the absolute encoder of the present invention is designed to latch the input time of the control synchronization signal, position data at the time of the current command synchronized with the control synchronization signal can be obtained based on the human power time of the control synchronization signal. I can do it.

(Embodiment) FIG. 1 is a block diagram showing an example of the absolute encoder of the present invention corresponding to FIG. 3, and FIG. 2 is a timing chart showing an example of its operation.

The counter 11 counts the counter clock inside the counter up to a value of 2'''-1 (m: a natural number), and sends the count value CT to the excitation circuit 21 and the latch circuit 41.
44 respectively. The excitation circuit 21 uses the count value CT from the counter 11 to generate two-phase excitation signals ef, ef2 with a phase shift of 90' and sends them to the resolver 61. The resolver 61 sends an output signal efo whose phase changes depending on the position to the comparator 31 based on the two-phase excitation signals ef, ef2 from the excitation circuit 21. The comparator 31 outputs the output signal efo from the resolver 61.
A latch command is sent to the latch circuit 41 at this detection timing. The latch circuit 41 latches the count value +10n of the counter 11 representing the detection time and detection position in response to a latch command from the comparator 31 and sends it to the latch circuit 42 . The latch circuit 42 latches the count value RD of the counter 11 representing the detection time and detection position latched by the latch circuit 41 in response to a latch command of the control synchronization signal SQ from the outside, and
Send to 1.

The latch circuit 43 includes a count value RD of the counter 11 representing the detection time and detection position at which the latch circuit 42 last latched in response to a latch command of the control synchronization signal SQ from the outside;
l is latched and sent to the arithmetic unit 51.

The latch circuit 44 latches the count value ↑D of the counter 11 representing the manual labor time of the control synchronization signal sq by a latch command of the control synchronization signal SQ from the outside, and
Send to. The computing unit 51 calculates the time TF until the current command is issued to the motor that drives the axis and the latch circuits 42, 43, 44.
The count values nD, , RD, l, TDn from the following equation (2
) to find the position data RO at the time of the current command synchronized with the control synchronization signal SQ and output it to the outside.

Note that ΔP: RD, moving distance ΔT1 from -1 to RDn: elapsed time ΔT2 from RDn-1 to R[ln
=TF+ΔT.

Note that the latch circuits 41 to 44 and the arithmetic unit 51 in the above-described embodiments can also be realized using a microcomputer.

(Effects of the Invention) As described above, since the absolute encoder of the present invention is independent as a unit, when this absolute encoder is installed on each of a plurality of axes, it can be used for each axis without affecting each other. Combined position detection can be performed.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of the absolute encoder of the present invention, Fig. 2 is a time chart showing an example of its operation, Fig. 3 is a block diagram showing an example of a conventional absolute encoder, and Fig. 4 is an example of its operation. It is a time chart showing. II, 12... Counter, 21... Excitation circuit, 3
1... Comparator, 41, 42, 43, 44, 45
．． 46...Latch circuit, 51.52... Arithmetic unit, 6
1...Resolver.

Claims (1)

[Claims] 1. In an absolute encoder that detects a position in synchronization with a control synchronization signal, a counting means that counts a time longer than the cycle of the control synchronization signal from the outside, and a position detection means that detects the position. a first storage means for storing the count value of the counting means at the detection timing of the position detection means; a second storage means for storing the count value of the counting means in response to a control synchronization signal from the outside; a speed detection means for determining a moving speed based on a position detection value from the position detection means; a count value from the first storage means, a count value from the second storage means, and a position detection value from the position detection means; and calculation means for determining and outputting a position synchronized with the control synchronization signal based on the speed detection value from the speed detection means and the time up to the time of the current command. 2. The position detecting means includes an excitation means that generates a two-phase excitation signal using the count value from the counting means, and a signal whose phase changes depending on the position based on the two-phase excitation signal from the excitation means. 2. The absolute encoder according to claim 1, comprising: a resolver that outputs the output signal; and comparison means that detects zero in the output signal from the resolver and sends a storage command to the first storage means at the timing of this detection.