JPH033041A - Time-out monitoring circuit - Google Patents

Abstract

PURPOSE:To prevent the occurrence of intermittent time-out error by converting a comparing value into an initializing value at the time of detecting time-out in processing monitored by a timer, commanding the reexecution of the processing, and at the time of detecting time-out again, informing the occurrence of a fault. CONSTITUTION:A timer counting register 1 holds the count value or initializing value 100 of the timer and its value 101 is sent to a decision circuit 4. The circuit 4 decides whether the value 105 of a timer counting register 3 is equal to the value 101 or not and sends th decided result 106 to a timer control circuit 5. In response to a select signal 108 from the circuit 5, a selector 6 selects the initializing value 100 and commands the reexecution of the processing, and when time-out is detected during the period of the reexecution, the occurrence of a fault is informed. Consequently, the time-out monitoring circuit can be prevented the occurrence of intermittent time-out error caused because the value set up in the timer is smaller than the maximum time practically required for the processing whose time-out is to be monitored.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a timeout monitoring circuit, and more particularly to a timeout monitoring circuit used in an information processing device.

Prior Art Conventionally, timeout monitoring circuits have used timers to detect timeouts in processing between multiple processes within each processor, processing between multiple processors, and processing between each processor and the main storage device. The initial setting value of this timer was set to a default value by hardware or a microprogram.

In such conventional timeout monitoring circuits, the initial setting value of the timer is fixed, and the value is determined in advance by calculating the actual time required for the process that requires timeout monitoring. There is.

However, the actual time required for processing that requires timeout monitoring varies depending on various factors such as the system configuration of the device and the load status of each processor, so it is difficult to calculate it assuming all cases. It is.

Therefore, if the value set in the timer is smaller than the maximum time actually required for processing, a problem may occur in which timeouts occur intermittently.

Additionally, if a timeout occurs because the value set in the timer is close to the maximum time actually required for the process that requires timeout monitoring, it is difficult to determine the cause of the timeout. There is a problem.

Purpose of the Invention The present invention has been made to eliminate the problems of the conventional methods as described above. An object of the present invention is to provide a timeout monitoring circuit that can prevent intermittent timeout errors that occur because the value is smaller than the maximum time actually required for processing that requires timeout monitoring.

Configuration of the Invention A timeout monitoring circuit according to the present invention is a timeout monitoring circuit that detects a timeout indicating that a count value of a timer has exceeded a preset initial setting value, and comprises:
switching means for switching a comparison value to be compared with a count value of the timer to detect the timeout to one of the initial setting value and the processing time actually required in the processing monitored by the timer; re-execution instructing means for instructing re-execution of the processing after switching to the initial setting value by the switching means when the timeout is detected while the processing is being performed after switching to the processing time by the means; and a notification means for notifying the occurrence of a failure in the process when the timeout is detected while the process is being re-executed in response to an instruction from the re-execution instructing unit.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, it is assumed that the timeout monitoring circuit according to one embodiment of the present invention monitors the timeout of one process using one timer.

The timer counting register (ITR) 1 holds the J1 value of the timer or the initial setting value 100 (all "1"), and the value lot is sent to the determination circuit (ZDU) 4.

The adder 2 adds the addition value 103 "1" to the initial value 102 (all "0") of the timer or the value 105 of the timer count register (CTR) 3, and the addition result 104
is sent to timer count register 3.

Timer count register 3 is the addition result 104 of adder 2
, that is, it holds the value while the timer is counting (during addition by adder 2) or the value after counting (after addition), and the value 1
05 is sent to the determination circuit 4 and selector 6.7.

The determination circuit 4 determines whether the value I05 of the timer count register 3 is equal to the value lot of the timer count register 1, and sends the determination result 10B to the timer control circuit (TCU) 5.

The timer control circuit 5 receives the judgment result 10B from the judgment circuit 4 and the timeout monitoring start signal (TST) from the CPU 8.
(hereinafter referred to as the monitoring start signal) 111 and timeout monitoring stop signal (TSP) (hereinafter referred to as the monitoring stop signal) 1
12, a hold signal 107 is output to the timer count register 3, select signals 108 and 109 are output to the selectors 6 and 7, respectively, and an interrupt signal (INT) 110 is output to the CPU 8.

The selector 6 receives a select signal 10 from the timer control circuit 5.
8, the initial setting value of the timer is set to 100 (all “1”).
) and the value 105 of the timer count register 3 (timer count value), and store that value in the timer count register 1.

Selector 7 receives select signal 10 from timer control circuit 5
9, one of the timer initial value 102 (all "0") and the timer count register 3 value 105 (timer count value) is selected, and the selected value is sent to the adder 2.

FIG. 2 is a block diagram showing the system configuration of an embodiment of the present invention. In the figure, a main memory unit (MMU) 10,
Arithmetic processing unit (EPU) 11, human output control unit (IOP)
) 12 and 13 are connected to each other by a system bus ZOO.

A plurality of timers (not shown) are provided in each device except the main storage device 10 for monitoring timeouts of various processes.

For example, when the arithmetic processing unit 11 accesses the main storage device 10, a timer in the arithmetic processing unit 11 performs timeout monitoring to determine whether the access ends within a certain period of time, or When the device 11 instructs the input/output control device 12 to execute an input/output command, another timer within the arithmetic processing device 11 monitors the timeout of the completion of the input/output command.

In the above-described system configuration, timeout monitoring for one process using a timeout monitoring circuit according to an embodiment of the present invention will be described.

The timer control circuit 5 receives the monitoring start signal tti from the CPU 8.
When started by human power, a select signal l port 8 is output to the selector 6, and the initial setting value 1 of the timer is set by the selector 6.
00 (all "1") is selected and stored in timer count register 1.

Further, the timer control circuit 5 outputs the select signal H)9 to the selector 7, and the selector 7 outputs the initial 1ii110 of the timer.
2 (all "0") is selected and input to the adder 2 as the augend.

The value to which 1'' has been added by the adder 2 is stored in the timer count register 3, and then selected by the selector 7 via the timer count register 3 by the select signal 109 from the timer control circuit 5, and is applied to the adder 2. Inputted as an addition number.

Thereafter, the adder 2 performs sequential addition until the timeout monitoring process ends or the addition result 104 of the adder 2 becomes equal to the value lot of the timer count register 1 and a timeout is detected. executed.

When the timeout monitoring process is completed, a monitoring stop signal 112 is input from the CPU 8 to the timer control circuit 5, thereby stopping the timeout monitoring operation.

At this time, the timer control circuit 5 outputs a hold signal 107 to the timer count register 3, and the adder 2
The addition result 104 is held in the timer count register 3 as the time actually required for the timeout monitoring process.

Next, when the same process that performed the above-mentioned timeout monitoring is executed again, in order to perform timeout monitoring, the timer control circuit 5 changes the timer count register 1 to the timer count register 3 in the previous timeout monitoring operation.
A select signal 10B is output to the selector 6 so that the value held in is stored.

As a result, the time actually required for the process for which timeout monitoring was previously performed is set in the timer count register 1, and timeout monitoring is executed in the same manner as described above.

Generally, when the same process is executed several times within a system, the time required for the process is not constant due to various environmental changes. Therefore, even if the above-mentioned timeout monitoring of the same process is performed based on the time actually required for the process for which timeout monitoring was performed last time, there is a possibility that a timeout will occur in the current timeout monitoring.

Here, when timeout monitoring for the same process is performed based on the time actually required for the process for which timeout monitoring was previously performed, the value 105 of the timer count register 3 changes to the value 105 of the timer count register 1 before the process ends. becomes equal to the value 101, the determination circuit 4 detects a timeout of the process and reports it to the timer control circuit 5.

The timer control circuit 5 changes the value 105 of the timer count register 3 to the timer count register 1 based on the report from the determination circuit 4.
When it is detected that the process has become equal to the value lO1, the timeout of the process is reported to the CPU 8 by an interrupt signal 110.

When the CPU 8 is informed that the process has timed out based on the time actually required last time, the CPU 8 instructs each device to re-execute the process, and again sends the monitoring start signal 11.
1 to the timer control circuit 5 and restarts. Note that the determination and execution of re-execution of the process and restart of the timer control circuit 5 are performed by a control program executed by the CPU 8.

The restarted timer control circuit 5 outputs a select signal 10g to the selector 6, and causes the timer count register 1 to store the timer initial setting value 100 (all "1") again, thereby executing timeout monitoring.

If the process ends normally with this timeout monitoring,
At this time, the value held in timer count register 3 is
It is used when monitoring the next timeout for the process.

In other words, when the process ends normally in this timeout monitoring, the value held in the timer count register 3 in this timeout monitoring is longer than the time actually required for the process for which timeout monitoring was performed last time. It is found that the timeout has occurred, and from now on, the value held in the timer count register 3 will be used as the time actually required for the process.

In addition, in this timeout monitoring, if a timeout occurs before the processing ends, the timeout is reported to the CPU 8 by the interrupt signal 110, and the CPU
8 to each device.

As a result, each device executes failure processing for the process as a re-execution failure of the process.

In this way, by performing timeout monitoring by switching between the initial setting value 100 of the timer in each device and the time actually required for the timeout monitoring process,
Monitoring time, which is difficult to predict at the time of design, can be set for each process, and system-specific monitoring time can be set.

In addition, timeout monitoring is performed by switching the timer's initial setting value of 100 to the time actually required by the process for which timeout monitoring is being performed, so that the process currently performing timeout monitoring is the same as the process for which timeout monitoring was previously performed. Even if it takes longer than the specified time, the timer count register 1
Since it is possible to set the time actually required by the process currently performing timeout monitoring, the process will not result in a timeout error, and the value set in the timer will indicate the actual time required for the process to perform timeout monitoring. Intermittent timeout errors that occur because the time is less than the maximum value can be prevented.

Furthermore, even if a timeout error occurs, by referring to the actual time required for the process, it can be determined that the timeout error occurred because the timer settings used for timeout monitoring were inappropriate. It is possible to investigate the cause by excluding it.

In one embodiment of the present invention, a case has been described in which one timer monitors the timeout of one process, but it is obvious that the present invention can also be applied to a case where multiple timers monitor the timeout of a plurality of processes.

Further, in the determination circuit 4, a timeout is detected when the value 105 of the timer count register 3 matches the value 101 of the timer count register 1. A timeout may be detected when the time exceeds lO1, but the present invention is not limited to this.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a comparison value that is compared with a timer count value to detect a timeout indicating that the timer count value has exceeded a preset initial setting value is provided. If a timeout is detected while the initial setting value is being switched to the processing time actually required in the processing monitored by the timer, the comparison value is switched to the initial setting value and then the processing time is changed to the actual processing time. By instructing the re-execution of the process, and if a timeout is detected while the process is being re-executed, it will notify you of the occurrence of a failure in the process, which is difficult to predict at the time of design. The time can be set system-specifically to prevent intermittent timeout errors that occur because the value set on the timer is less than the maximum amount of time that the process that needs to be monitored for timeout actually takes. It has the effect of being able to.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, and Fig. 2 is a system configuration of an embodiment of the present invention. Device 3... Timer count register 4...
Judgment circuit 5...Timer control circuit 7...Selector 8...CPU

Claims (1)

[Claims] (1) A timeout monitoring circuit that detects a timeout indicating that the count value of a timer has exceeded a preset initial setting value, the circuit being compared with the count value of the timer to detect the timeout. a switching means for switching a value between the initial setting value and a processing time actually required in the processing monitored by the timer; When the timeout is detected, a re-execution instruction means for instructing re-execution of the process after switching to the initial setting value by the switching means; and a re-execution of the process according to an instruction from the re-execution instruction means. 1. A timeout monitoring circuit comprising: a notification means for notifying the occurrence of a failure in the processing when the timeout is detected during the processing.