JPH05189258A - Microcomputer - Google Patents

Abstract

PURPOSE:To prevent runaway, and simultaneously, to improve the reliability of a system by automatically re-executing an instruction from starting before the generation of an error in the case the error is caused in a microcomputer because of an external noise, etc. CONSTITUTION:At the same time as the microcomputer 1 executes the instruction by an internal register 3 and an arithmetic logical part 6, an auxiliary register 4 and an auxiliary arithmetic logical part 7 emulate the instruction, and both results are compared with each other by a comparison circuit 9. Then, in the case that the error is caused, an interruption signal is generated through an interruption control circuit 10, and the contents of the register 3 just before the generation of the error copied beforehand in a monitor memory 5 are restored to the register 3 by this interruption signal. As the result, the instruction is re-executed while starting from the instruction just before the generation of the error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer for preventing runaway caused by external noise.

[0002]

2. Description of the Related Art The structure of a conventional general microcomputer is shown in FIG. In the figure, a microcomputer unit 1 showing the inside of the microcomputer includes an instruction decoder 16, an internal register 3, an arithmetic logic unit 6, and a control circuit 1.
It is composed of 7 etc. Here, the instruction decoder 16
Receives and decodes an encoded instruction from the external memory and I / O unit 15 via the address bus and the data bus 2, and the decoded instruction is executed by the arithmetic logic unit 6 via the internal register 3. It The control circuit 17 controls the external memory and the I / O unit 15 by the control bus 8. Further, the internal register 3 includes an accumulator having an accumulation function, a program counter indicating a memory address in which a program is stored, a general-purpose register used for temporarily saving operation data, and the like. As described above, the microcomputer unit 1 inputs data from the external memory 15 via the address bus and the data bus 2, decodes the instruction by the built-in instruction decoder 16, and decodes the decoded instruction in the internal register 3 And the arithmetic logic unit 6 and the like.

[0003]

In such a microcomputer, when noise or the like arrives, malfunction is prevented by taking measures such as software using interrupts or resetting by hardware. Therefore, there is a drawback that the processing that has been performed up to that point is interrupted.

[0004]

In order to solve such a problem, the present invention enables an instruction to be pseudo-executed (emulated) independently at the time of executing an instruction of a microcomputer, and the result is actually executed. The operation status is monitored by collating with the result of (1), and when an abnormality is detected, the instruction immediately before the abnormality is re-executed.

[0005]

The contents of the internal register of the microcomputer are copied to the auxiliary register of the present invention, and
The auxiliary arithmetic logic unit emulates the operation of the microcomputer internal bus, and the comparison circuit compares the instruction execution result of the internal register with the emulation result. If these results do not match, an interrupt signal is generated from the interrupt control circuit, and the interrupt signal restores the instruction already saved in the monitor memory to the internal register. As a result, if an abnormality occurs and the results of the respective instructions do not match, the instruction immediately before the abnormality occurs is re-executed immediately.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a microcomputer according to the present invention. In the figure, 1 is a microcomputer unit showing the inside of this microcomputer, 2 is an address bus and data bus, 3 is an internal register, 4 is an auxiliary register for assisting the internal register 3, 5
Is a monitor memory for storing the contents of the internal register 3, 6 is an arithmetic logic unit for executing instructions, 7 is an auxiliary arithmetic logic unit for assisting the arithmetic logic unit, 9 is an arithmetic logic unit 6 and an auxiliary arithmetic logic unit 7. A comparison circuit 10 for comparing the operation results is an interrupt control circuit for generating an interrupt according to the comparison result of the comparison circuit 9. The control bus 8 is for transmitting the interrupt generation signal to the monitor memory 5.

Next, the operation of the microcomputer configured as described above will be described. First, the microcomputer copies the contents of the internal register 3 to the auxiliary register 4 and the monitor memory 5 before executing the instruction using the arithmetic processing unit 6. Here, the auxiliary register 4 is
The change in the content of the internal register 3 which changes due to the execution of the instruction is emulated (simulated execution) as the change in the content of the auxiliary register 4 using the auxiliary arithmetic logic unit 7. After executing the command,
The comparison circuit 9 is used to compare the contents of the internal register 3 and the contents of the auxiliary register 4 to check whether the contents of the two are equal. If the contents of both are different, the internal register 3 or the auxiliary register 4 is for some reason.
It is determined that an error has occurred in any of the above, and the interrupt control circuit 10 issues a hardware interrupt to restore the contents of the internal register 3 copied in the monitor memory 5 immediately before the error occurs to the internal register 3. As a result, the instruction is re-executed from the state immediately before the error occurred.

Next, FIG. 2 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 2, a counter 11 for counting the number of abnormality occurrences, a comparator circuit 9 and an interrupt control circuit 12 are provided. It is provided between and. Then, the counter 11 counts the errors that have occurred during the execution of a certain time or a certain number of instructions, and when the count value exceeds a preset value, the interrupt control circuit 12 is instructed as described above. Generates a hardware interrupt signal that is separate from the hardware interrupt signal. That is,
When such an error occurs frequently, the interrupt control circuit 12 generates a hardware interrupt different from the above, interrupts the processing being executed, and shifts to the exception processing routine.

Next, FIG. 3 is a block diagram showing a third embodiment of the microcomputer, which is a count value setting for setting the value to the counter 11 shown in the second embodiment. A circuit 13 is provided and a count value monitor circuit 14 capable of monitoring the value set in the counter 11 is provided. By adding these circuits, the counter value to the counter 11 can be changed according to the purpose of the user, and the set count value can be monitored at any time. In this way, even if noise comes and the value of the internal register fluctuates and the microcomputer runs out of control, this can be completely suppressed and it is easy to determine whether the fluctuation of the register value is an accidental one. It can also be determined.

[0010]

As described above, according to the present invention,
The instruction can be pseudo-executed independently at the time of executing the instruction of the microcomputer, and the operation status is monitored by comparing the result with the result of the actual instruction execution.
When an abnormality is detected, the instruction immediately before the abnormality occurs is re-executed. Therefore, even if the abnormality occurs due to the arrival of noise or the like, the processing can be immediately restarted.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a microcomputer according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the microcomputer.

FIG. 3 is a block diagram showing a third embodiment of the microcomputer.

FIG. 4 is a block diagram of a conventional microcomputer.

[Explanation of symbols]

 1 microcomputer part 2 address bus and data bus 3 internal register 4 auxiliary register 5 monitor memory 6 arithmetic logic unit 7 auxiliary arithmetic logic unit 8 control bus 9 comparison circuit 10, 12 interrupt control circuit 11 counter 13 count value setting circuit 14 count value Monitor circuit

Claims (3)

[Claims] 1. An auxiliary register and an auxiliary logical operation unit, which are provided corresponding to a register for executing an instruction and a logical operation unit, and execute the instruction by simulation, and an instruction execution result of the instruction by the auxiliary register and the auxiliary logical operation unit. A comparison circuit that compares the execution result of the instruction by the register and the logical operation unit, an interrupt control circuit that generates an interrupt signal according to the comparison result of the comparison circuit, and a state immediately before the execution of the instruction by the interrupt signal A microcomputer provided with a monitor memory for controlling. 2. An auxiliary register and an auxiliary logical operation unit, which are provided corresponding to a register for executing an instruction and a logical operation unit, and execute the instruction by simulation, and a simulated execution result of the instruction by the auxiliary register and the auxiliary logical operation unit. A comparison circuit that compares the execution results of the instructions by the register and the logical operation unit and generates an error signal when they do not match, and counts the number of times the error signal is output, and the count value passes a fixed time or a fixed number. A counter for generating an output signal when a predetermined value is reached during execution of the instruction, and an interrupt control circuit for generating an interrupt signal for executing exception processing based on the output signal of the counter. Microcomputer characterized by. 3. The microcomputer according to claim 2, further comprising a setting circuit that arbitrarily sets a count value of the counter that shifts to the exception processing, and a monitor circuit that can refer to the count value. And a microcomputer.