JP2020071492A - Information processing system - Google Patents

Abstract

To provide an information processing system which learns a determination reference by itself, and in which modification of a monitor circuit is unnecessary even if the determination reference is changed.SOLUTION: A monitor circuit 30 of an information processing system monitors whether or not an active system host unit 1 is normally operated via a common bus 10. A learning circuit 40 stores address and data which the active system host unit accesses when executing an application, in a storage unit, and learns the address and data accessed while executing normally. The learning circuit determines that the operation is abnormal, when the active system host unit accesses abnormal address and data, and outputs a switch request signal 20 to a switch circuit 31. The switch circuit outputs a switch request signal 21 instructing to be a standby system host to the active system host unit, and at the same time outputs a switch request signal 22 instructing to be an active system host to a standby system host unit 2, and the standby system host unit transfers from a standby mode to an active system.SELECTED DRAWING: Figure 1

Description

The present invention relates to an information processing system, and more particularly to an information processing system capable of automatically switching a CPU system when a failure occurs.

When a host unit equipped with a processor (hereinafter referred to as CPU) has a redundant configuration, when a hardware failure occurs in the operating host unit (hereinafter referred to as the active host unit), or a forced reset is performed. When it is executed, the switch signal notifies the host unit in the standby state (hereinafter, the standby system host unit) that the operating system host unit cannot operate, and the standby system host in the standby state A system switching operation for transitioning the active system to the unit is executed (for example, refer to Patent Document 1).

JP, 2006-260393, A

However, in order to monitor whether or not a hardware failure or the like has occurred, conventionally, it has been necessary for a user to determine in advance a judgment criterion such as a normal response time. Then, there is a problem that the judgment standard must be reflected in the monitoring circuit.
Further, when the judgment standard is changed due to the modification or addition of the application to be used, there is a problem that the monitoring circuit must be modified to reflect the content of the modification.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an information processing system that does not require modification of a supervisory circuit even when the criteria are learned and the criteria are changed. And

An information processing system according to the present invention includes a plurality of host units connected by a common bus, a monitoring circuit connected to the common bus and monitoring whether the operation of the host unit is normal or abnormal, And a switching circuit that outputs a switching signal that switches the host unit in the operating state to the host unit in the standby state when the switching request signal is received from the monitoring circuit, and switches the host unit in the standby state to the host unit in the operating state. The monitoring circuit includes a learning circuit having a learning function, and the learning circuit learns a normal address accessed by the host unit in the operating state when executing an application, and the host unit in the operating state accesses an address that is not a normal address. , The operation of the operating host unit is abnormal To determine.

According to the information processing system of the present invention, since it is not necessary to modify the monitoring circuit even when the judgment criterion is changed, the operation management of the information processing system becomes easy.

It is a figure which shows the structure of the information processing system which concerns on Embodiment 1 of this invention. It is a figure which shows the structural example of the information processing system which applied PPMC to the host unit of the information processing system which concerns on Embodiment 1 of this invention. It is a figure explaining the state transition of the system by the switching control device of the information processing system which concerns on this invention.

Embodiment 1.
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same reference numerals denote the same or corresponding parts.

FIG. 1 is a system configuration diagram of an information processing system 100 according to the present embodiment.
The information processing system 100 includes an active system host unit 1, a standby system host unit 2, a monitoring circuit 30, and a switching circuit 31, and the monitoring circuit 30 further includes a learning circuit 40.

The active host unit 1 and the standby host unit 2 are connected to the common bus 10.
The operational host unit 1 inputs the switching signal 21 and the reset signal 23 from the switching circuit 31. Similarly, the standby system host unit 2 inputs the switching signal 22 and the reset signal 23 from the switching circuit 31.
The monitoring circuit 30 is connected to the common bus 10 and outputs the switching request signal 20 to the switching circuit 31.
Upon receiving the switching request signal 20 from the monitoring circuit 30, the switching circuit 31 outputs the switching signals 21 and 22 and the reset signal 23 to each of the active host unit 1 and the standby host unit 2.
The learning circuit 40 is mounted inside the monitoring circuit 30, and AI (artificial intelligence) technology that realizes intelligence on a computer is applied to the learning circuit 40.

In the information processing system 100, one of the host units is the active host by the switching signal 21 output from the switching circuit 31 to the host unit 1 and the switching signal 22 output from the switching circuit 31 to the host unit 2 as well. Yes, indicating that the other host unit is a standby host.
As an example, the switching circuit 31 outputs a switching signal 21 instructing the host unit 1 that it is an active host, and outputs a switching signal 22 instructing the host unit 2 that it is a standby host. Output at timing. As a result, the host unit 1 operates as an active host and the host unit 2 operates as a standby host.

The monitoring circuit 30 monitors whether the active host unit 1 is operating normally via the common bus 10.

Monitoring of whether or not the active host unit 1 is operating normally is performed as follows, for example.
The learning circuit 40 included in the monitoring circuit 30 stores in the storage unit (not shown) the address and data that the active host unit 1 accesses when executing the application.
In this way, the active host unit 1 learns the address and data to be accessed during the normal execution of the application.
Based on the learning result, the learning circuit 40 determines that the operation of the active host unit 1 is abnormal when the active host unit 1 accesses an abnormal address or data during application execution.

In the above example, the learning circuit 40 uses the learning result to determine whether the host unit is normal or abnormal based on the address or data that the active host unit has accessed, but the present invention is not limited to this.
For example, the learning circuit 40 learns the response time when the active host unit 1 normally executes the interrupt handler for the interrupt factor, and the interrupt handler is not executed even if the response time exceeds the predetermined time. Based on this, the abnormality of the host unit may be determined.

Alternatively, the watchdog timer and the register are mounted in the monitoring circuit 30, and the learning circuit 40 learns the frequency and the access interval at which the active host unit 1 normally accesses the watchdog timer and the register, and the access frequency is learned. Abnormality of the host unit may be determined based on the fact that the range exceeds the specified range or the access interval exceeds the learned predetermined time.

The learning period of the learning circuit 40 is such that a learning target event such as access to a common bus, access to a watchdog timer or a register, or execution of an interrupt handler is learned until a predetermined number of times occur after system startup. You may do so.

The period in which the learning circuit 40 learns is an example, and the learning circuit 40 may perform learning within a predetermined period from system startup.

Further, the learning start period of the learning circuit 40 may be learned not only when the system is started up but also periodically or irregularly during the system operation for an arbitrary period or an arbitrary number of times.
Further, the learning circuit 40 may learn during debugging before operating the system.

Further, the learning circuit 40 may continue learning from the previous learning result when iteratively learning, or may initialize the previous learning result and restart learning from the beginning.

Next, when the learning circuit 40 determines that the operating system host unit 1 is abnormal, the monitoring circuit 30 outputs the switching request signal 20 to the switching circuit 31.

Upon receiving the switching request signal 20, the switching circuit 31 outputs the switching signal 21 instructing the active host unit 1 to be the standby host, and at the same time, is the active host to the standby host unit 2. A switching signal 22 instructing that is output.

Next, the switching circuit 31 outputs a reset signal 23 to each of the active host unit 1 and the standby host unit 2 to reset the system.
When the system is reset, the operating system host unit 1 starts the standby operation as the standby system because the switching signal 21 is instructed to the standby system.
On the other hand, since the switching signal 22 is instructed as the active system, the standby system host unit 2 shifts from the conventional standby mode to the active system and starts the operational operation.

Since the host unit 1 that has become the standby system and the host unit 2 that has become the active system both start operation upon system reset, the configuration information of the entire bus system and management of interrupt input / output are reconfigured. Since this operation is the same as the operation when the power is turned on, the host unit 1 and the host unit 2 do not need to perform special processing.

As described above, the information processing system according to the present embodiment includes the learning circuit 40, and the learning circuit 40 performs learning so that the operation host unit can be monitored. As an example of monitoring, a method in which the learning circuit 40 stores addresses and data to be accessed when various applications are operating normally and monitors for abnormal access, access to a watchdog timer or a register within a certain period The method of observing whether it is possible and the method of observing whether the interrupt handler can be executed within a certain period for the input of the interrupt factor are mentioned. This eliminates the need to repair the monitoring circuit even when the judgment criterion is changed, and thus has the effect of facilitating the operational management of the information processing system. Further, the learning circuit 40 learns the period in which the host unit determines that the watchdog timer and the register are normally accessed and the period in which the interrupt handler is determined to be normally executed, thereby improving the reliability and the switching of the abnormality detection. The speed can be improved.

Embodiment 2.
The second embodiment shows an example in which PPMC is used as the host unit.
The PPMC is a CPU board that can be mounted on the PMC connector of the carrier board specified by IEEE 1386.1 PMC and ANSI / VITA 32-2003 (R2009) Processor PMC. A plurality of PPMCs can be mounted on the carrier board.

FIG. 2 is a system configuration diagram of the information processing system according to the second embodiment.
In FIG. 2, a carrier board 200 corresponding to the information processing system 100 according to the first embodiment has a PPMC 101 corresponding to the active host unit 1, a PPMC 102 corresponding to the standby host unit 2, a monitoring circuit 130, a switching circuit 131, The learning circuit 140 is implemented.

The PPMC 101 and the PPMC 102 are connected to the PCI bus 110 corresponding to the common bus 10, and correspond to the MONARCH # signals 121 and 122 corresponding to the switching signals 21 and 22 in the first embodiment and the reset signal 23 similarly to the first embodiment. The RST # signal 123 is input.
The monitoring circuit 130 is connected to the PCI bus 110 and outputs the switching request signal 120. The switching circuit 131 receives the switching request signal 120 from the monitoring circuit 130, and outputs the MONARCH # signals 121 and 122 and the RST # signal 123.
The RST # signal 123 is a signal whose logic L conforming to the PCI standard is significant.

The PPMC has two operation modes, a monarch mode and a non-monarch mode, depending on the standard. The MONARCH # signal is a signal for instructing the monarch mode or the non-monarch mode. When the MONARCH # signal is logic L, the monarch mode is instructed, and when it is logic H, the non-monarch mode is instructed.
Since it is desired to have a host function in the PPMC that is the active system, the monarch mode is positioned as the active system and the non-monarch mode is positioned as the standby system. By doing so, the MONARCH # signals 121 and 122 can be utilized as signals for instructing whether the PPMCs 101 and 102 are the active system or the standby system.

FIG. 3 is a diagram for explaining system state transition by the switching circuit of the carrier board 200 according to the present embodiment.
The signal waveforms of the switching request signal 120, the MONARCH # signal 121, the MONARCH # signal 122, and the RST # signal 123 are shown with the horizontal axis as the time axis. In FIG. 3, the switching signal 120 uses the logic L as a significant signal, but the logic H may be a significant signal.

3, in the initial state, the MONARCH # signal 121 outputs to the PPMC 101 a logical L signal indicating that it is in the active system, that is, the monarch mode, and the MONARCH # signal 122 is in the standby system, that is, nonmonarch to the PPMC 102. Is output as a logic H signal. As a result, the PPMC 101 operates as an active system and the PPMC 102 operates as a standby host.

The monitoring circuit 130 learns the observation status by the learning circuit 140 by observing the PCI bus 110, and monitors whether the PPMC 101 of the active system is operating normally. When the monitoring circuit 130 determines that the PPMC 101 in the active system is abnormal, it outputs the switching signal 120 of logic L to the switching circuit 31.

The switching circuit 131 switches the PPMC 101 from the active system to the standby system and switches the PPMC 102 from the standby system to the active system when the logical L switching request signal 120 is input from the monitoring circuit 130.
The MONARCH # signal 121 changes the output from the logic L to the logic H to instruct the PPMC 101 to be the standby system, and the MONARCH # signal 122 changes from the logic H to the logic L to instruct the PPMC 102 to be the active system. Change the output.

The switching circuit 131 outputs a logic L RST # signal 123 to the PPMCs 101 and 102 to reset the system. The system reset causes the PPMC 101 to start operating as a standby system because the MONARCH # signal 121 is instructed to be logic H. Since the MONARCH # signal 122 is instructed to be logic L, the PPMC 102 starts operating as an active system.

Since both the standby PPMC 101 and the active PPMC 102 start their operations by resetting, the configuration information of the entire bus system and the management of interrupt input / output are reconfigured. Since this operation is the same as the operation when the power is turned on, the PPMC 101 and PPMC 102 do not require special processing.

The learning circuit 140 according to the present embodiment observes the PCI bus 110 and learns the observation result, similarly to the learning circuit 40 according to the first embodiment, and then, the learning circuit 140 of the active PPMC (either of the PPMCs 101 and 102 in the operating state). Judge abnormalities.
The learning circuit 140 provided in the monitoring circuit 130 accumulates in the storage unit (not shown) the address and data that the active PPMC 101 accesses when executing the application. In this way, the active PPMC 101 learns the address and data to be accessed during the normal execution of the application. Based on the learning result, the learning circuit 140 determines that the operation of the active PPMC 101 is abnormal when the active PPMC 101 accesses an abnormal address or data during application execution.

In the above example, the learning circuit 140 uses the learning result to determine whether the host unit is normal or abnormal based on the address and data that the active PPMC 101 accelerates, but the present invention is not limited to this. ..
For example, the learning circuit 140 learns the response time when the active PPMC 101 normally executes the interrupt handler for the interrupt factor, and the interrupt handler is not executed even if the response time exceeds the predetermined time. Based on this, the abnormality of the PPMC 101 may be determined.

Further, the watchdog timer and the register are mounted in the monitoring circuit 130, and the learning circuit 140 learns the frequency and the access interval at which the working PPMC 101 normally accesses the watchdog timer and the register, and the access frequency is The abnormality of the active PPMC 101 may be determined based on the learned range being exceeded or the access interval having exceeded the learned predetermined time.

The learning period of the learning circuit 140 is such that a learning target event, for example, access to a common bus, access to a watchdog timer or a register, execution of an interrupt handler, or the like is performed until a predetermined number of times from system startup. You may do so.

The period in which the learning circuit 140 learns is an example, and the learning circuit 140 may perform learning within a predetermined period from system startup.

Further, the learning start period of the learning circuit 140 may be learned not only when the system is started up but also periodically or irregularly during system operation for an arbitrary period or an arbitrary number of times.
Further, the learning circuit 140 may learn at the time of debugging before operating the system.

Further, the learning circuit 140 may continue learning from the previous learning result when repeatedly learning, or may initialize the previous learning result and restart learning from the beginning.

As described above, in the information processing system according to the present embodiment, by implementing the switching control function independently of the PPMC, it is possible to realize the switching function while maintaining compatibility without making a special change to the existing PPMC. The development cost can be reduced.
Further, by making the switching control function independent of the PPMC, even when the PPMC fails, the failure can be detected and switched. In particular, even in the case of being configured according to the existing standard such as PPMC, the existing PPMC can be used as it is to realize the switching function.

Note that the learning circuit 140 may be instructed by the user at least during the initial period to determine whether or not the PPMC 101 or PPMC 102 is operating normally during learning. For example, when an abnormality occurs, the user may perform an operation to send an alarm signal to notify the learning circuit 140 of the abnormality of the active PPMC. Alternatively, when the PPMC itself determines an abnormality, a signal notifying the abnormality may be output to the learning circuit 140. By doing so, the learning circuit 140 can store and learn as an abnormal address or data an address or data accessed by the active PPMC that is initially judged to be abnormal by the user.

1 working host unit, 2 standby host unit, 10 common bus, 20 switching request signal, 21 switching signal, 22 switching signal, 23 reset signal, 30, 130 monitoring circuit, 31, 131 switching circuit, 40, 140 learning circuit , 100 information processing system, 110 PCI bus, 101 active PPMC, 102 standby PPMC, 121 MONARCH # signal, 122 MONARCH # signal, 123 RST # signal, 200 carrier board

Claims (3)

Multiple host units connected by a common bus,
A monitoring circuit connected to the common bus to monitor whether the operation of the host unit is normal or abnormal;
A switching circuit that outputs a switching signal that switches the host unit in the operating state to the host unit in the standby state when the switching request signal is received from the monitoring circuit, and switches the host unit in the standby state to the host unit in the operating state;
The monitoring circuit includes a learning circuit having a learning function, the learning circuit learns a normal address accessed by the host unit in the operating state when an application is executed, and the host unit in the operating state accesses an address that is not a normal address. Then, the information processing system is characterized in that the operation of the host unit in the operating state is determined to be abnormal. The learning circuit learns a period in which the host unit in the operating state normally executes interrupt handling for an interrupt factor, and if the interrupt handling is not executed within the period, the operation of the host unit in the operating state is abnormal. The information processing system according to claim 1, wherein the information processing system determines that The learning circuit learns a load condition of the system to set an access period, and determines that the operation of the host unit in the operating state is abnormal when there is no access within the access period. 1. The information processing system according to 1.

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