JPH03293767A - Semiconductor device - Google Patents

Abstract

PURPOSE:To allow a semiconductor device to make high-speed operations by making a channel completely depleted with a polycrystalline-silicon gate electrode of the same conductivity type as that of the channel and a high- concentration area immediately below the channel. CONSTITUTION:A storage capacitance is formed of an n<+> polysilicon film 13'', thin oxide film 13, and electrode 32 of A, etc. A gate electrode 14' is provided with p<+> polysilicon on a gate oxide film and Pt on the polysilicon so as to lower the resistance of a word line. In addition, the electrode 14' is provided with a p<+> area formed below and adjacently to an n<+> area 13 in order to improve the holding characteristics and storage capacitance. Then a channel area is formed to a layer which is almost completely depleted under a condition where no gate voltage is applied and a potential barrier which controls a main current is formed near a source area, and then, the clearance between a source and drain is set shorter than 1mum. Therefore, a normally-off MOS transistor which can make high-speed operations and a semiconductor device which is an integrated circuit using the transistor can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device including an improved normally-off insulated gate transistor capable of high density and good memory retention. In order to achieve higher density changes and higher speeds, the gate length (channel length) inevitably becomes shorter, which has the disadvantage of making it difficult to create normally-off characteristics. In order to achieve normally-off, it was necessary to increase the impurity density of the channel, but increasing the impurity density reduces mobility, which is disadvantageous for high-speed operation.

Progress in increasing the density of semiconductor memories, particularly dynamic random access memories (hereinafter referred to as d-RAMs), has been extremely remarkable. As 64-bit d-RAMs begin to be used in the market, 256-bit d-RAMs are also actively being developed. 1
The high density of the d-RAM, which has reached the ultimate circuit format, such as the one-transistor-capacitor format, is achieved primarily by miniaturizing each component. Therefore, the main electrode, that is, the distance between the source and drain (hereinafter referred to as channel length) of an insulated gate type (hereinafter referred to as MOS type) transistor is becoming shorter. Even if the voltage is set to zero, a current flows between the source and drain, and normally-off characteristics cannot be obtained, and the stored contents disappear within a short time, so that the memory no longer functions as a memory.

Currently, under normal LSI (Large Scale Integrated Circuit) Si processes, the component MO8 field effect transistor (hereinafter referred to as MO8FET) is often constructed as shown in Figure 1. To realize this, an n-channel structure as shown in Fig. 1 is usually used.The p region 11 is the substrate, and the two main electrodes are formed symmetrically in Fig. 1, so for convenience, the n region 12 is used as the source and the n" A region 13 is a drain. 14 is a gate which is a control electrode and is made of n-1 polysilicon in a normal process. 15 is a gate oxide film, 16 is a field oxide film, and 17 is a PSG film.

Reference numerals 12' and 13 are source and drain electrodes of AQ, etc. 18 is a p region, with a field oxide film and a p substrate 1
This is a channel stopper area to prevent channels that are likely to form between 10 and 10 cm. Of course, the gate oxide film 15 and the like may partially include a thin Si3N4 film.

Further, a passivation film is usually provided on the surface shown in FIG.

A structure in which an insulating film is provided on one main electrode region of a MOS FET configured as shown in Fig. 1, for example, an insulating film is provided on the drain region without directly providing an electrode, or an electrode is provided through the insulating film, or the drain region is The structure in which an electrode is provided in the region using n-polysilicon and the electrode is provided on an oxide film formed by lightly oxidizing the polysilicon surface becomes a 1-transistor-1-capacitor type d-RAM cell as it is.

Two types of substrates and two experimental samples with the same parameters except the channel length L (mask level) were used.
The results of prototyping with various gate oxide film thicknesses T0° and examining the memory content retention 11fl characteristics are shown below. The source region and drain region are provided by AS ion implantation, and their depth XJ is approximately 0.5 μm. The accelerating voltage at that time is 100 kV. Channel doping is performed by boron (B) ion implantation. Gate width is 100μm 1 Gate oxide film pressure TOX is 500A and 10
00A, P substrate resistivity ρSub is about 7Ωcm and 200
It is about CIIl.

The retention time characteristics were evaluated using a circuit configuration as shown in FIG. 2 in which one end of the storage capacitor ICa of this d-RAM was grounded. In FIG. 2, 21 and 22 are word lines and bit lines, respectively, and 23 and 24 are MOS FETs, respectively.
(T,) and storage capacity! (C3). During writing, a write voltage VW is applied to the bit line 22 and vG is applied to the word line 21. If the MOS FET T is an n-channel, both V and VG are positive voltages.

When a positive voltage ■ is applied to the lead wire and T1 becomes conductive, since a positive voltage vvv is applied to the bit line, current flows into the storage capacitor OS, and C3 becomes approximately Vw.
It is charged to Vth. Vi is the threshold voltage of the MOS FET. In this state, electrons flow out from the n+ drain region 13, and the n+ region 13 lacks electrons and is positively charged. After the word line pulse is returned to zero, writing is completed by removing the bit line voltage. In the memory holding state, there is no need to apply an external voltage to any terminal of the memory cell configured as shown in FIG. In this holding state, n
Since the + region 13 is positively charged due to a lack of electrons and is in a reverse bias state with respect to the P substrate 11, the stored contents will be preserved for a long time. In Figure 2, MOS FET (
Although the substrate bias of T, is not mentioned, if the channel length of T becomes short and the memory contents are erased or affected by subthreshold current, apply a substrate bias (in this example, a negative voltage). The memory content is better retained.

The retention time characteristics measured in this way are shown in FIGS. 3, 4, and 5 for three types of materials. These data were also measured under room temperature operating conditions. VG=
5 V, Vw = 5 V. The retention time is
It is defined as the time when the voltage stored in C3 becomes approximately 1/2. The retention time is the effective channel L eF
Plotted against F. L c4F is approximately 0.5 μm shorter than the channel length determined by the mask. In the figure, ■, ■, ■, ■ indicate the P board 11.
Substrate bias ■8 values to be added to 0v11V, -2V,
This corresponds to the case of -4V.

Figure 3 is T. Sample of X=1000A, ρ5ub=7ΩCR1, Fig. 4 is T. x=50OA, ρ5ub=7ΩCl
Sample l1, Figure 5 is T. x=500A, ρ, last=20
These are the results for each sample of ΩCIm. While L eFF is long, the retention time is long at around 100 seconds, but L
As the eFF becomes shorter, the retention time becomes shorter rapidly. Fifth
In the sample shown in the figure, when Laf+=2°5 μm, even if vS is added, it only lasts about 100 μsec. In the sample shown in Fig. 5, d-RA must be larger than L0 = 3.5 μm.
It does not work as M. On the other hand, in the sample shown in Figure 3, VB
-4v and n4. f, 'elf = 1, 5 μm
, 1: T-ha has sufficient memory retention. However, the sample shown in Fig. 3 is still solid. When it becomes clear = 0.5μ, it is already d
It cannot be used for RAM. In the sample shown in Figure 4, VB--4
Even as V, LaFf = 1.59m 1. : Then, the retention time begins to decrease.

As we aim for higher density and shorten the channel length,
When L=approximately 1 μm (Lau=approximately 0.5 μm), the retention time rapidly decreases and it no longer functions as a dRAM.

In order to lengthen the retention time in a short channel, normally-off characteristics are usually obtained by increasing the amount of doping in channel doping ion implantation. Alternatively, the impurity density of the channel is increased.
When L+jf=about 0.5 μm, the impurity density of the channel is about 100I11. Such a high impurity density results in a new disadvantage of low electron mobility and inability to operate at high speed.

An object of the present invention is to provide a semiconductor device including an insulated gate transistor that sufficiently retains memory contents and operates at high speed even with an extremely short channel length. Instead, it is an object of the present invention to provide a normally-off MO3 transistor that has a very low channel impurity density, has high mobility, and can operate at high speed, and a semiconductor device that is an integrated circuit using the same.

Another object of the present invention is to provide a semiconductor device with a novel structure in which the potential distribution within the channel and the size of the potential barrier can be easily determined and the design of a normally-off MOS transistor is easy.

First, let us discuss the reason why the stored contents suddenly disappear when the channel becomes short, as shown in FIGS. 3 to 5.

As the channel length becomes shorter, the potential barrier that previously prevented electrons from flowing between the source and drain appears to be lowered by the influence of the source and drain regions. In long channel samples, the potential barrier height in the channel region is usually controlled only by the gate potential and substrate voltage, but in short channel samples it is also controlled by the source and drain potentials. It becomes like this. In other words, the electrostatic induction effect seen in static induction transistors (SIT) appears, and current begins to flow between the source and drain even if no gate voltage is applied.
So-called bunch-through occurs. Here, this current is called an SIT current or a subthreshold current. FIG. 6 shows the relationship between the drain current 1d and the drain voltage vd of the sample shown in FIG. 3, where the mask channel length L=1 μlI (effective channel length Laf+=05 μl1).

The vertical axis is I.

, the horizontal axis is ■. The sixth point is that current flows between the source and drain even though the gate voltage vQ=o.
The figure shows. As a matter of course, when the substrate bias VB is increased to a negative value, Id becomes smaller. That is, even in case 6-0, current will flow if a certain amount of voltage is applied between the source and drain.

In the d-RAM, when the voltage VITl is written and held in the storage capacitor C3, the voltage Vm is applied between the source and drain. Therefore, naturally the sixth
A current as shown in the figure flows, and the accumulated voltage is attenuated. The process by which the accumulated voltage decreases due to the current flowing between the source and drain can be easily analyzed. Since the circuit is as shown in Figure 7, the voltage stored in CS is transferred to the MOS FET.
It is attenuated by the current flowing through T.

Letting the voltage of Cs be V, the equation describing the voltage attenuation process is as follows. t is time. As can be seen from FIG. 6, the SIT current 1 changes exponentially. That is, I
, = I. It can be expressed as e′ゞ. ro and a change depending on the substrate bias VB. Initial condition'(0) =V m
The solution to the original equation (1) is . V(t) becomes 1/γ of the write voltage. Figure 8 shows the calculated values and actual measured values assuming γ=4. In FIG. 8, retention time is plotted against substrate bias VB. The O mark is the actual value,
The 10 marks are calculated values, and it can be seen that they are in close agreement.

That is, the attenuation of the accumulated voltage when the channel becomes short is due to the SIT current between the source and drain. Next, when comparing FIG. 3 and FIG. 4, the retention characteristic when the channel becomes short is worse in FIG. 4.

That is, the gate oxide film pressure T. The thinner X becomes, the worse the retention characteristics become. Let me briefly discuss this matter.

As shown in FIG. 1, the gate of an n-channel MO3FET is typically formed of n-polysilicon. FIG. 9 shows a one-dimensional cross-sectional structure from the gate toward the substrate.

The thickness of the P substrate 11 is assumed to be d. The dielectric constants of the gate oxide film and the P substrate are ε2 and ε1, respectively. The equation describing the potential distribution when a reverse bias VQ (including the diffusion potential V1) is applied between the substrate and the n gate electrode is V, -V. 10V, ... (4) ... (5) is given. Vo and V8 are voltages applied to the oxide film and the PI board, respectively. N8 is the effective acceptor concentration of the P substrate. q is unit charge. From equations (4) and (5), the depletion layer width W and V of the P region.

becomes. Also, the electric field strength E in the gate oxide film and the P region
0, ES is. However, 2εIVQ'=(NA,>2, and the width of the depletion layer when all the voltages ■) are applied to the P substrate.

FIG. 10 shows the potential distribution within the P substrate when the voltage is changed. This is the result when the gate potential is kept at the same potential as the source. The vertical axis is the potential and the horizontal axis is the coordinates. This is a state in which only the diffusion potential Vbi is applied with the substrate bias VB-O. However, vbi is the diffusion potential of the np junction. The circle on the vertical axis is the source potential. Tox
When = 0, the curve is represented by ■, and the potential of the p region at the interface is the same as the potential of the source. As TOX becomes thicker, the potential at the interface with the oxide film increases. TOX-■
, that is, when the oxide film is sufficiently thick, it becomes a constant dotted line. That is, as TOX becomes thinner, the potential at the interface approaches the potential at the source region. This means that electrons from the source or drain easily enter this region where the potential has decreased, causing current to flow.

In order to shorten the channel, the gate oxide film must necessarily be made thinner. Therefore, the effect of lowering the surface potential and making it easier for current to flow becomes more and more pronounced.

In this way, when the channel is shortened, the source-drain current does not become so large unless a low-potential portion is created on the surface.

The reason why the above-mentioned phenomenon occurs is that in an n-channel doped FET, the gate electrode is formed of n-polysilicon. To overcome this difficulty, the gate electrode may be formed of p-polysilicon. FIG. 11 shows the potential distribution directly under the gate oxide film when a p+ polysilicon gate electrode is used. Potential O indicates the potential of the source region. (2) is the diffusion potential of the n+ source region and the p+ polysilicon region, which is about 1.0 to 1.1 V at room temperature. P
If the substrate impurity density is about 1 x 10 cm, vl
>i vbi is approximately O25. In the case of a p-polysilicon gate, the limit where TOX is thinner is curve 2, and as TOX becomes thicker, the curve becomes curve 2.

In other words, the thinner the Tox, the S! The potential at the Oz-PS interface becomes high and electrons flow. The sample of FIG. 3, namely T. x=1000A, ρ,. The retention time when the channel was doped with -7 ΩCm and the gate was made of p+ polysilicon was measured under the same conditions as in FIGS. 3 to 5, and the retention time is shown in curve (2) in FIG. Retention time is plotted against substrate bias. The channel length is 1 μm (effective channel length, 0.5 μm).
m), the retention time in FIG. 3 was extremely short. If V is set to -4v, L-1tlm, Len-0
, 5 μM, a retention time of about 100 seconds can be obtained.

Under the same conditions, the retention time of the n+ polysilicon gate is 6m5ec. The tendency for the retention time to be improved by the p+ polysilicon gate becomes more pronounced as the Tox becomes thinner. It's an extremely significant improvement. Curve 2 in FIG. 12 is the result when platinum (Pt) is used for the gate electrode.

By using platinum, the retention time characteristics have also been sufficiently improved. As gate resistance becomes higher as channels become shorter, it makes sense to make the gate a metal. By using platinum, retention time characteristics have been sufficiently improved.

FIG. 13 shows a cross-sectional structure of a p-polysilicon gate d-RAM cell according to the present invention. The numbers are written to correspond to those in Figure 1. The numbers different from those in FIG. 1 will be explained. 14
' is p-polysilicon. 13'' is n+ polysilicon.

31 is a thin oxide film, and 32 is an electrode such as A-view. In this structure, a storage capacitor is formed by 13''-31-32. In FIG. If the density increases, the resistance of the word line becomes too large, causing problems, so P is placed on the gate oxide film.
It is necessary to provide polysilicon and PT on top of it to reduce the resistance of the word line. Further M on top of Pt
It is also good to provide a high melting point metal such as O or W. In any case, any metal with a high melting point, such as Pt, that will not be damaged by subsequent high-temperature processes will suffice. Although not shown in FIG. 13, in order to improve retention characteristics and increase storage capacity, the n+ region 13 is placed adjacent to the n+ region 13.
It is necessary to provide a p1 region below the p1 region. The impurity density of the p+ region adjacent to the n+ region 13 may be set such that a breakdown phenomenon does not occur when a write voltage is accumulated. It is often made to have a density on the order of 10 cm.

The results shown in FIG. 12 were measured using the circuit configuration shown in FIG. 2, that is, the configuration in which one end of the storage capacitor, ie, 32, is grounded.

This is the result regarding the so-called depletion type operation in which electrons flow out from the n-region 13 and the maximum shortage of electrons is memorized. The cell of FIG. 13 is operated by applying a positive voltage Vss to 32, as is normally done. Naturally, it is operated in a so-called accumulation type operation, that is, an operation in which excessive electrons are accumulated in the n+ region 13. At high temperatures, storage-type operation has a shorter retention time than depletion-type operation.

In the p-polysilicon gate n-channel MOS transistor of the present invention, the potential v at the 5t02-PSi interface
The a-wall is a conventional n+ polysilicon gate n-channel M
As the channel becomes shorter, the depth x j of the n region 12. Subthreshold current (S
IT current) flows and deteriorates the retention time characteristics. In order to suppress this, it is effective to provide a p+ region inside as well. For example, by ion implantation, the p1 region is moved along the channel to about the same depth as the n region 12.13.
If it is provided inside the substrate, the internal potential barrier will be reduced, and the subthreshold current (SIT current) will be -layer smaller. An example of its structure is shown in FIG. FIG. 14 <a> shows an example in which the p+ region 33 reaches below the n region [13, but even though the p+ region impurity density along the p+ region channel below 13 is the same, , the area along the channel may also be made higher. The p+ region 33 may be provided only along the channel, as shown in FIG. 14(b). It is desirable that the n+ region 12 and the p+ region 33 be separated from each other. This is to prevent the bit line capacitance from increasing. Of course, the p+ region 33 is n+
It may even reach completely below area 12. In that case, the n+ region 12 may be made sufficiently shallow and a metal electrode may be removed to form a bit line. (Figure 14(C)).

A similar effect can also be achieved with the structure shown in FIG. 15 in which two layers 11' are provided on the p+ substrate 11''.
Of course, it may be directly adjacent to the substrate 114. At write voltage, n+ region 13, n+ region 12 and ρ+ substrate 1 powder.

1 or breakdown state and no current flows. Consideration must also be given to substrate bias. In order to reduce the bit line capacitance, it is preferable that the n+ region 12 not be directly adjacent to the p+ substrate 11''.If the n+ region 12 is made sufficiently shallow, the bit line capacitance will be reduced.

The cut-off state of the MOS transistor as shown in FIGS. 14 and 15 will be explained below.

To facilitate analysis, the MO3)-transistor is
Approximate as shown in Figure 6 (a). It is approximated by a rectangular structure. A p 2 polysilicon gate is provided on the thin 5izzle with n 2 source and drain regions on either side. The lower p region corresponds to the buried region. This is the channel depth D from the source-drain spacing surface to the p+ buried region. This is the impurity density NA of the channel region. The potential in the channel is determined when the potential of the source region is ov, and the potentials of ``Sub'' and ``2'' are applied to the p1 gate, V 6 V b; For simplicity, it is assumed that the oxide film thickness is sufficiently thin and that the inside of the channel is a complete depletion layer. The potential in the channel becomes φ(χ>)・.

L-Bottom It is.

Here, )-chiχh-'l/rt-1... (11)L''
D The potential distribution within the channel can be easily determined using equation (10).

for ease Vb is set to -1V.

FIG. 17 shows the height Vb of the potential fil generated in the channel.
shows the dependence of on the normalized channel length L7. The parameter is the drain voltage vp. The gate voltage ■, is OV, and the substrate bias V6ub'''4V.The voltage V, corresponds to the voltage Vrn stored in the storage region.The value of 17 to give the same VB increases as VD increases. It has become.

FIG. 18 shows the relationship between VB and Lh. The parameter is the substrate bias V Sub. V(,=O,
There is no NC when VD = 3V (7). Naturally, as the substrate bias v sub becomes smaller, the value of L that gives the same value of VB becomes larger.

FIG. 19 shows how the normalized channel length increases with drain voltage V9 when the same potential barrier ΔV is applied. VB=0.7V is given, and the value of is, for example, about 0.96 when VD=2V, vD=3Vr4t1.05, ■.

= 1.14 at 5V.

FIG. 20 shows the relationship between LrL and v sub for multiple values of △3□ when VD=3V. Naturally, the same △! LrX giving l/rrl is v5. Jb
becomes smaller as the value increases. V, Ub-OV, that is, even in a state where no substrate bias is applied, with this structure,
=1.8, it is possible to give AYn-, =0.7.

If it is about -0.7V, the retention time as a d-RAM is sufficient, and it operates as a normally-off transistor in which the drain current increases before an exponential function with respect to the drain voltage, so these results hold true. . is 0
．． This shows that a sufficient retention time can be obtained with a channel depth of about 9 to 2.0 μm.If the channel depth D is 0.1 μm, the effective channel length can sufficiently operate as a dynamic RAM even if it is from 0.09 μm to 0.2 μm. This means that MOS transistors can be realized.

FIG. 21 shows the drain current IcL and drain voltage V when the channel width W is 100 μm.

shows the relationship between - The dashed line is sample 1 (L, ■=0.5
This is an experimental value of μl11). L7 is 0.9.1.0.1
By setting ゜1.1.2.1.3, the drain current (subthreshold current) decreases drastically, but Id-V
The d characteristic is pre-exponential.

Up to now, the impurity density in the channel region has been discussed while being kept at a constant value, and FIG. 22 shows the influence of the impurity density in the channel region on the potential barrier.

Two cases are shown. Naturally, if you increase N8. becomes larger. However, below a certain NA, V is almost constant. (2) The value of N7 at which the value becomes approximately a constant value increases as the channel length becomes shorter. As long as the necessary V is compensated, it is desirable that N be as small as possible. The space charge resistance is reduced, the electric field distribution within the channel is made more uniform, the electric field strength is weakened, and the hot electron effect is reduced.

Dynamic RA with the structure shown in FIGS. 14 and 15
The effective channel length of the M cell is shortened to about 0.1 μm. When the effective channel length is shortened to this extent, the hot electron effect that shifts the threshold voltage becomes extremely small in the short channel MOS transistor. This is because the time for electrons to flow through the channel becomes shorter and they reach the electrode region before becoming hot electrons.If a p+ region is provided along the channel as shown in Figures 14 and 15, ,
The response of the potential distribution within the channel to the word line voltage becomes faster, and the operating speed is improved. Of course, it is important to take care not to increase the bit line capacitance.

Furthermore, when MOS transistors are made to have shorter channels and storage capacitance is reduced, a new problem arises in which carriers generated by α particle irradiation flow into the floating storage region and erase memory. α particles have an energy of several MeV, and depending on the energy in Sl, 1
It is thought that the thickness is about 0 to 25 μm. In 3i, the most electron-hole pairs are generated near where the α particles stop.

Therefore, if the p region 33 is provided below the channel region and the accumulation n region 13 as shown in FIG. It no longer flows into the region 13, and malfunctions due to α particle irradiation are drastically reduced.

FIG. 23 shows an example in which exactly the same thing can be applied to a two-layer polysilicon d-RAM cell.

41 is a P substrate, n region 42 is a bit line region, 43 is a low resistance polysilicon, 44 is a p+ polysilicon gate, 4
5 is a gate oxide film, 46 is a field oxide film, and 47 is an oxide film. 48 is a p+ region for channel stopper. The storage capacitor C3 is composed of 43-45-41. 41' is a substrate electrode. A signal is accumulated depending on the amount of electrons accumulated in the depletion layer formed under 43. It is also called an inversion layer. Here, for simplicity, this region will also be called a drain region.

It is equally effective to provide a p+ region or a p'' substrate as shown in FIGS. 14 and 15. For example, as shown in FIG. 24, a p+ region 49 is provided.

Up to now, in the structural example of the d-RAM cell, an example has been shown in which the substrate electrode is provided on the entire surface, but it is not necessary to provide it on the entire surface. Further, the surface may be further coated with a passivation group.

So far, we have described an example in which bit lines and storage capacitors are provided on the same plane, but the exact same thing happens with VMO8 and UMO8, which have notches.
Naturally, the d-RAM of the present invention having an O8 structure or a UMO8 structure can also be constructed.

Although only the n-channel has been described, a similar structure is also effective for an n-channel whose conductivity type is completely reversed. That is, a structure in which a high impurity density region of the same conductivity type as the channel is provided in direct contact with the gate insulating film is sufficient. Of course, high melting point metals such as W, MO, and PT are also effective. The thinner the gate insulating film is, the more
The voltage applied to the gate is efficiently applied to the channel region. Therefore, in order to increase the conversion conductance, it is desirable that the gate insulating film be as thin as possible due to breakdown voltage, manufacturing technology, etc.

If the portion of the gate electrode directly adjacent to the gate insulating film is composed of a high impurity density layer of the same conductivity type as the source and drain regions, the potential of the channel adjacent to the gate insulating film decreases, causing the source region potential to decrease. approach. Therefore, even if the gate voltage is reduced to zero, the channel cannot be blocked sufficiently, and current flows between the source and drain. Moreover, this effect becomes more noticeable as the channel length is shortened to achieve higher density. The structure of the present invention is such that the SIT current between the source and drain is suppressed to a sufficiently low level even in a short channel structure to realize normally-off characteristics, and the SIT current flows when conductive. Since it is in the d-RAM structure that the so-called leakage current between the source and drain in the zero gate voltage state is most severe, the application of the MoS transistor of the present invention has been described so far only to the d-RAM. Although only the structure of one cell is shown in the figure, these cells are provided at the intersections of a matrix formed by bit lines and word lines, with the word line connected to the decoder and the bit line connected to the sense amplifier. That's why there is. The short channel structure increases the conversion conductance and promotes high-speed logic circuits. The influence of leakage current when interrupting elements used in logic circuits is d
- Not as large as in RAM. However, if the leakage current becomes too large, it tends to become difficult to distinguish between high and low output levels. Therefore, an MO with an effective channel length of about 1 μm or less
In the logic circuit of an S transistor, it is necessary to configure the gate in a region of the same conductivity type as the channel, even though the process is complicated, and to reduce the gate resistance by forming a high-melting point metal on top of the gate. Moreover, the potential barrier in the channel must be reduced.

An example is shown in Figures 25, 26, and 27.

FIG. 25 shows an inverter whose load is an M○S transistor T3 whose gate is directly connected to its source. T2 is a MOS transistor of the present invention. Since T3 is in a conductive state with the gate and source directly connected, a Mo8 l-transistor with a conventional structure is more suitable. T2
can be sufficiently blocked, so high levels are almost completely blocked by VD.
Close to D.

In FIG. 26, a part of the potential V c5 (which may be directly connected to the drain of T3 depending on the case) is applied to the gate of T5. T4 is a MOS transistor of the present invention. T may be used as a transistor of the present invention.

FIG. 27 shows a complementary inverter. Both T6 and air are Mo8 l-transistors of the present invention. This 0MO
The third configuration is an ideal circuit configuration in which current flows only when switching is performed and no current flows during steady state. However, if this 0MO8 configuration is configured with a conventional Mo8 FET to make a short channel, a large leakage current causes a current to flow even in a steady state, increasing power consumption. However, in the Mo8 l-transistor of the present invention, the leakage current is suppressed to a sufficiently low level, so that the advantages of the 0MO3 configuration can be utilized even in short-channel, high-density integrated circuits. Furthermore, when the dovetail channel is formed, the gate capacitance becomes smaller and the response of the channel potential to the gate voltage becomes faster, so the switching speed becomes faster, and the advantages of the 0MO8 configuration become even more pronounced. 0M using the MOS transistor of the present invention
The O3 configuration has excellent high-speed power consumption characteristics. Multi-input NOR and NAND gates can be easily configured based on the configurations shown in FIGS. 25, 26, and 27, and static RAMs can also be configured in the same way.

The structure of the present invention is not limited to that described here. The conductivity type may be completely reversed. In short, it is sufficient that a high impurity density region of a conductivity type opposite to that of the source region is provided as at least a portion of the gate electrode in direct contact with the gate insulating film. At the same time, a high impurity density region may be provided inside the substrate along the channel.

Also, when the depth from the substrate surface to the p+ region 33 is W, and the effective channel length is C+r, L ef'f is due to the substrate bias,
'w+i,o~1.2 is enough to operate as a dynamic memory. That is, W-015μm, p
f = 0.15-0.18 μlR.

The insulated gate transistor of the present invention can sufficiently suppress leakage current during cut-off even in a short channel structure with an effective channel length of 1 μIll or less, and has a low gate resistance, so it is particularly effective when configuring a d-RAM. is significant, and the effective channel length is between 0.1 and 0.
Even with a thickness of 5 μm, sufficient memory can be retained. Also, 0M
When the O8 configuration is used, low power consumption and high speed are particularly emphasized with the short channel structure. As described above, the insulated gate transistor of the present invention and the integrated circuit using the same have extremely high industrial value.

The insulated gate transistor of the present invention and the memory and logic circuit using the same can be manufactured by conventionally known crystal technology, phosphorography technology, oxidation technology, diffusion technology, CV[) technology, vapor deposition technology, wiring technology, etc.

According to the present invention, a normally-off type (enhancement type) is realized by completely depleting the channel with a polycrystalline silicon gate electrode of the same conductivity type as the channel and a high concentration region directly under the channel.戊〜
Even extremely high resistance layers of 1013cIl-3 can be used as channels. Therefore, the mobility is high (and the junction capacitance of the source and drain regions is small, so high-speed operation is possible).

According to the present invention, switching is performed by actively utilizing the bunch-through phenomenon that was a problem with conventional short channel MO8FETs, so it is easy to shorten the channel, reduce the cell area, and increase the degree of integration. .

According to the present invention, since the channel is completely depleted, electrons drift and travel at extremely high speeds.

According to the present invention, since the potential distribution within the channel can be easily calculated using equation (10), it is extremely easy to design a normally-off type MOS transistor.

[Brief explanation of drawings]

Figure 1 shows the cross-sectional structure of the MOS FET, Figure 2 shows the d-R
AM cell circuit configuration, Figures 3 to 5 show channel length dependence of retention time, Figure 6 shows Id-Vp characteristics, Figure 7 shows retention characteristic analysis circuit, and Figure 8 shows substrate bias of retention time. Figure 9 shows the cross-sectional structure, Figure 10 shows the potential distribution in the P substrate just below the gate oxide film, Figure 11 shows the potential distribution just below the gate oxide film when using a p+ polysilicon gate electrode, and Figure 12 shows the potential distribution in the P substrate just below the gate oxide film. An example of the retention time in the structure of the present invention, FIGS. 13 to 15 are examples of the cross-sectional structure of the d-RAM cell of the present invention, and FIGS. 16(a) and 16(b) are model devices for potential distribution analysis. Figures 17 and 18 show the relationship between Vb and 17, and Figure 19 shows the potential R wall △yff.
The relationship between D and Figure 20 shows the relationship between L7 and V which gives the potential barrier Δy.
Figure 21 is the relationship between drain current and drain voltage when V = 0, Figure 22 is the impurity density dependence of the potential barrier ■, Figure 23 is the cross section of the d-RAM cell of the present invention. Structure example, FIG. 24 shows an embodiment of the present invention, FIGS. 25 and 26 show an inverter using the insulated gate transistor of the present invention, and FIG. 27 shows a complementary inverter using the insulated gate transistor of the present invention. It is a circuit. Diagram Zetsu no Zukan 7 Diagram 10 Diagram 0 -/ 2 Zu 4 5 Difference Hias Vi (V) ρ // // 11/'J Diagram 1/ Is//71 - Diagram ρ // ( Cn*711 figure (θ) θ / 2 3 4 F[I>1rso Up (V) and Ureshino 9 figure M2D figure ρ 4/ s23 figure ρ 4/ Iris L/- figure?-/ Hall 25 ■ Connection 2 and illustration 27 1991 January and half a day

Claims (6)

[Claims] (1) near the surface of the semiconductor substrate, a source region and a drain region of a first conductivity type, a second conductivity type located between the source region and the drain region, and a second conductivity type opposite to the first conductivity type;
In a semiconductor device including a normally-off insulated gate transistor in which a channel region of a conductive type and high resistance, a gate insulating film, and a gate electrode are sequentially formed on the surface of the channel region, at least the gate electrode is made of polycrystalline silicon of a second conductive type. A high-melting-point metal is formed on this material, and a region of a second conductivity type and high impurity density is provided in at least a part of the inside of the semiconductor substrate adjacent to the high-resistance channel region, and a gate voltage is applied to the semiconductor substrate. A depletion layer is formed almost completely in the channel region when no voltage is applied, a potential barrier for controlling the main current is formed near the source region, and the distance between the source and drain is 1 μm or less. Semiconductor equipment. (2) near the surface of the semiconductor substrate, a source region and a drain region of a first conductivity type, a second conductivity type located between the source region and the drain region, and a second conductivity type opposite to the first conductivity type;
In a semiconductor device including a normally-off insulated gate transistor in which a channel region of a conductivity type and high resistance, a gate insulating film, and a gate electrode are sequentially formed on the surface of the channel region, the semiconductor substrate has a high impurity density of a second conductivity type. Further, the semiconductor device includes a region of a second conductivity type and an impurity density lower than that of the semiconductor substrate, and the source, drain, and high resistance channel regions are formed in the region of the low impurity density. , a depletion layer is almost completely formed in the channel region when no gate voltage is applied, and a potential barrier for controlling the main current is formed near the source region, and the gate electrode is made of a second conductivity type polycrystalline material. A semiconductor device characterized in that the semiconductor device is made of a material made of silicon and a high melting point metal formed thereon, and the source-drain distance is 1 μm or less. (3) near the surface of the semiconductor substrate, a source region and a drain region of a first conductivity type, a second conductivity type located between the source region and the drain region, and a second conductivity type opposite to the first conductivity type;
A semiconductor device comprising a conductive type and high resistance channel region, an insulated gate transistor in which a gate insulating film and a gate electrode are sequentially formed on the surface of the channel region, and a storage capacitor directly connected to the insulated gate transistor. The gate electrode is made of a material made of polycrystalline silicon of a second conductivity type and a high melting point metal formed thereon, and at least a portion of the inside of the semiconductor substrate adjacent to the channel region is made of a material of a second conductivity type and high impurity. A dense region is provided so that a depletion layer is almost completely formed in the channel region when no gate voltage is applied, and a potential barrier for controlling the main current is formed near the source region, and the source-drain interval is 1. A semiconductor device characterized in that the diameter is 1 μm or less. (4) near the surface of the semiconductor substrate, a source region and a drain region of a first conductivity type, a second conductivity type located between the source region and the drain region, and a second conductivity type opposite to the first conductivity type;
A semiconductor device including a conductive type and high resistance channel region, an insulated gate transistor in which a gate insulating film and a gate electrode are sequentially formed on the surface of the channel region, and a storage capacitor directly connected to the insulated gate transistor,
The semiconductor substrate has a high impurity density of a second conductivity type,
Further, the semiconductor device includes a region of a second conductivity type and an impurity density lower than the impurity density of the semiconductor substrate,
The source, drain, and channel regions are formed in the low impurity density region, a depletion layer is almost completely formed in the channel region when no gate voltage is applied, and a main current is controlled in the vicinity of the source region. A potential barrier is formed, and the gate electrode is made of a material consisting of second conductivity type polycrystalline silicon and a high melting point metal formed thereon;
A semiconductor device characterized in that an interval between the source and drain regions is 1 μm or less. (5) In the semiconductor device according to claim 3 or 4, the drain region of the insulated gate transistor is constituted by an inversion layer, and the effective channel length of the distance between the source region and the inversion layer is 1 μm. A semiconductor device characterized by the following: (6) a source region and a drain region of a first conductivity type located near the surface of the semiconductor substrate, a second conductivity type located between the source region and the drain region, and a second conductivity type opposite to the first conductivity type; A high resistance channel region, a first normally-off insulated gate transistor in which a gate insulating film and a gate electrode are sequentially formed on the surface of the channel region, a second conductivity type low resistance source and drain region, the source region and the drain region a second normally-off insulated gate transistor located between the first conductivity type and high resistance channel region, a gate insulating film, and a gate electrode sequentially formed on the surface of the channel region; In a semiconductor device in which a gate region and a drain region of a gate type transistor are electrically connected, the gate electrodes of the first and second normally-off insulated gate transistors are made of polycrystalline silicon of a second conductivity type and a high-temperature layer formed thereon. It is a material consisting of a melting point metal, and in the first insulated gate transistor, the second conductivity type, and in the second insulated gate transistor, the first conductivity type and high impurity density region is formed in at least one part of the inside of the semiconductor adjacent to the channel region. a depletion layer is formed almost completely in the channel region when no gate voltage is applied, and a potential barrier for controlling the main current is formed near the source region, and the distance between the source and drain regions is A semiconductor device characterized by having a diameter of 1 μm or less.