JPH03293747A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03293747A JPH03293747A JP2075117A JP7511790A JPH03293747A JP H03293747 A JPH03293747 A JP H03293747A JP 2075117 A JP2075117 A JP 2075117A JP 7511790 A JP7511790 A JP 7511790A JP H03293747 A JPH03293747 A JP H03293747A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- grooves
- glass plate
- substrate
- chipping
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000000034 method Methods 0.000 abstract description 36
- 239000000758 substrate Substances 0.000 abstract description 31
- 239000011521 glass Substances 0.000 abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 8
- 238000001312 dry etching Methods 0.000 abstract description 6
- 238000000059 patterning Methods 0.000 abstract description 3
- 239000004642 Polyimide Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 239000007767 bonding agent Substances 0.000 abstract 2
- 239000000853 adhesive Substances 0.000 description 12
- 230000001070 adhesive effect Effects 0.000 description 11
- 238000005530 etching Methods 0.000 description 9
- 238000001039 wet etching Methods 0.000 description 4
- 238000003776 cleavage reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000007017 scission Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
Landscapes
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の製造方法に係り、特にVia−
)1o1eを有する半導体装置のチップ分割方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device.
) 1o1e relates to a chip dividing method for a semiconductor device.
(従来の技術〕
第3図および第4図は従来のV:a−Holeを有する
半導体装置のチップ分割方法を示す断面図で、図におい
て、1は半導体素子が表面に形成された半導体基板、2
はガラス板、3は半導体基板1とガラス板2とを接着す
る接着剤、4は半導体基板1を貫通しているVia−H
ole、5はP HS (PlatedHeat 5i
nk)である。(Prior Art) FIGS. 3 and 4 are cross-sectional views showing a conventional chip dividing method for a semiconductor device having a V:a-Hole. In the figures, 1 indicates a semiconductor substrate on which a semiconductor element is formed; 2
3 is a glass plate, 3 is an adhesive for bonding semiconductor substrate 1 and glass plate 2, and 4 is a Via-H that penetrates semiconductor substrate 1.
ole, 5 is PHS (PlatedHeat 5i
nk).
次にチップ分割方法について説明する。まず第3図(A
)に示すように、半導体素子か表面に形成された半導体
基板1か接着剤3を介してガラス板2に接着される。こ
の時、半導体基板1の表面か接着される側である。ここ
て、接着剤3は半導体基板1表面に形成されている半導
体素子を保護するフォトレジストとカラス板2への貼付
けを行なうワックスとから成る。Next, a chip dividing method will be explained. First, Figure 3 (A
), a semiconductor substrate 1 formed on the surface of a semiconductor element is bonded to a glass plate 2 via an adhesive 3. At this time, the surface of the semiconductor substrate 1 is the side to be bonded. Here, the adhesive 3 consists of a photoresist that protects the semiconductor elements formed on the surface of the semiconductor substrate 1 and wax that is attached to the glass plate 2.
次に第3図(B)のように、写真製版技術、ウェットエ
ッチンク技術を用いて半導体基板1の所望の場所にVi
a−Holeか形成される。ウェットゴッチンクによる
Via−Hole形成は等方性エッチンクの為サイトエ
ッチンクか多く図示するように表側、裏側で開口寸法か
異なる。Next, as shown in FIG. 3(B), Vi is applied to a desired location on the semiconductor substrate 1 using photolithography and wet etching technology.
An a-Hole is formed. Via-hole formation by wet etching is isotropic etching, so it is often site etching, and as shown in the figure, the opening size is different on the front side and the back side.
次いで第3図(C)のように、めっき技術によりPH5
5か形成され、Via−tlole4を通してPH55
は半導体基板1表面の半導体素子の電極と接続される。Next, as shown in Figure 3 (C), the pH is 5% by plating technology.
5 is formed and PH55 is passed through Via-tole4.
is connected to the electrode of the semiconductor element on the surface of the semiconductor substrate 1.
続いて第3図の(D)のように、PH55をマスクに半
導体基板1をウェットエッチンクし半導体装置個々(チ
ップ)に分割する。Subsequently, as shown in FIG. 3(D), the semiconductor substrate 1 is wet-etched using PH55 as a mask to divide it into individual semiconductor devices (chips).
この時もウェットエツチングの為にサイドエツチングが
多くPH55内側までエツチングが進んでしまう。この
後、接着剤3を除去すれば第3図(E)のようにチップ
分割が完了する。Also at this time, due to wet etching, there is a lot of side etching and the etching progresses to the inside of PH55. Thereafter, by removing the adhesive 3, the chip division is completed as shown in FIG. 3(E).
また、第4図は従来の他のチップ分割方法で、第3図(
C)までと同様の工程を終えた後、−旦接着剤3を除去
し第4図(A)に示すように、半導体基板1表面を出し
て再度ガラス板2に貼付ける。In addition, Fig. 4 shows another conventional chip division method, and Fig. 3 (
After completing the same steps up to C), the adhesive 3 is removed and the semiconductor substrate 1 is attached to the glass plate 2 again with the surface exposed, as shown in FIG. 4(A).
次いで第4図(B)のように、半導体基板1の所望の場
所をダイヤモンドカッターで切り込み、結晶のへき開性
を利用し分割するスクライブ方法や回転プレートで切削
して分割するダイシング方法等によりチップ分割する。Next, as shown in FIG. 4(B), the semiconductor substrate 1 is cut at a desired location with a diamond cutter, and the chips are divided by a scribing method in which the semiconductor substrate 1 is divided using the cleavage property of the crystal, or a dicing method in which the semiconductor substrate 1 is cut and divided by cutting with a rotating plate. do.
接着剤3を除去すれば第4図(C)のように個々に分割
された半導体装置が得られる。By removing the adhesive 3, individually divided semiconductor devices can be obtained as shown in FIG. 4(C).
従来の半導体装置のチップ分割方法は以上のように構成
されていたので、ウェットエツチングによる分割の場合
エツチングの均一性や再現性が良くない問題点があり、
またスクライブ方法の場合ではガラス板の貼り代え工程
がある事、半導体基板への切り込みが少ないとうまくへ
き開できず分割端面が欠ける、あるいは全く分割できな
い等の問題点がある。そしてダイシング方法も貼り代え
工程があり、回転ブレードで基板を切削する時切削端面
が欠ける(チッピング)という問題点があった。Conventional chip dividing methods for semiconductor devices are configured as described above, but when dividing by wet etching, there is a problem that the uniformity and reproducibility of etching is not good.
In addition, in the case of the scribing method, there are problems such as the step of replacing the glass plate, and if the number of cuts into the semiconductor substrate is small, the cleavage cannot be done well, resulting in chipping of the dividing end face, or the inability to divide the semiconductor substrate at all. The dicing method also involves a re-adhesive process, and there is a problem in that when cutting the substrate with a rotating blade, the cut end surface is chipped (chipping).
この発明は上記のような問題点を解消するためになされ
たもので、分割の均一性、再現性が良く分割端面の欠け
やチッピング等を防止できかつ、ガラス板の貼り代え等
の工程も削除できるチップ分割方法を得ることを目的と
する。This invention was made to solve the above-mentioned problems, and it has good division uniformity and reproducibility, prevents chipping and chipping of the divided end faces, and eliminates steps such as replacing glass plates. The purpose of this study is to obtain a chip dividing method that is possible.
この発明に係る半導体装置の製造方法は、Via−Ho
le形成をドライエツチング法で形成する際同時に分割
用の溝を形成するようにしたものである。The method for manufacturing a semiconductor device according to the present invention includes
When the le is formed by a dry etching method, dividing grooves are formed at the same time.
この発明における半導体装置の製造方法は、分割用の溝
をトライエツチング法により形成するため、均一性・再
現性か良くなり、またスクライブやダイシングのように
分割端面に欠けやチッピング等か生しることも無くなり
、またスクライブ方法等におけるガラス板貼り代え等の
工程も削除できる。In the semiconductor device manufacturing method of the present invention, the dividing grooves are formed by the tri-etching method, which improves uniformity and reproducibility, and also prevents chipping or chipping from occurring on the dividing end surface, unlike scribing or dicing. In addition, steps such as replacing the glass plate in the scribing method can also be eliminated.
以下、この発明の〜実施例を図について説明する。第1
図において、符号1〜5は前記従来のものと同一である
。図において、6はフォトレジスト、7は半導体基板1
に形成された分割用溝である。Embodiments of the present invention will be described below with reference to the drawings. 1st
In the figure, numerals 1 to 5 are the same as those of the conventional device. In the figure, 6 is a photoresist, 7 is a semiconductor substrate 1
This is a dividing groove formed in the .
次にチップ分割方法について説明する。Next, a chip dividing method will be explained.
第1図(A)において、半導体素子か表面に形成された
半導体基板1か接着剤3を介しガラス板2に接着され、
フォトレジスト6を半導体基板1裏面全面に塗有Jした
後、Via−Hole4形成用の形成−ニンクを行なう
と同時に、分割用溝7形成用のバターニンクを行なう。In FIG. 1(A), a semiconductor substrate 1 formed on the surface of a semiconductor element is bonded to a glass plate 2 via an adhesive 3,
After coating the entire back surface of the semiconductor substrate 1 with photoresist 6, formation-nicking for forming Via-Hole 4 is performed, and at the same time, butter-nicking for forming dividing groove 7 is performed.
次に第1図(B)において、トライエツチング法(反応
性イオンエツチング、RIEなど)により、半導体基板
1をエツチングしVia−Hole4及び分割用溝7を
同時に形成する。ここで、分割用溝7の形成にはドライ
エツチング法を用いるため、エツチングの均一性・再現
性が良くなる。又、スクライブ方法やダイシング方法の
様な分割端面の欠け、チッピングの問題点も無くなる。Next, in FIG. 1B, the semiconductor substrate 1 is etched by a tri-etching method (reactive ion etching, RIE, etc.) to form the via-hole 4 and the dividing groove 7 at the same time. Here, since the dry etching method is used to form the dividing grooves 7, the uniformity and reproducibility of etching is improved. Furthermore, the problems of chipping and chipping of the divided end faces, which are caused by the scribing method and the dicing method, are also eliminated.
次いて、後工程への影響か無いように分割用溝7をフォ
トレジストやポリイミド、絶縁膜(SiO,SiN )
なとて埋め込んだ後、第1図(C)のようにPH35か
形成され、接着剤3と分割用溝7に埋め込まれたものを
除去し第1図(D)のように各チップに分割される。Next, the dividing groove 7 is formed using photoresist, polyimide, or an insulating film (SiO, SiN) so as not to affect the subsequent process.
After embedding, PH35 is formed as shown in Fig. 1(C), and the adhesive 3 and the material embedded in the dividing groove 7 are removed and divided into each chip as shown in Fig. 1(D). be done.
なお、上記実施例ては半導体基板1裏側からVia−H
ole4及び分割用溝7を形成する場合について説明し
たか、第2図に示すように半導体基板1表面から形成し
てもよい。Note that in the above embodiment, Via-H is connected from the back side of the semiconductor substrate 1.
Although the case where the ole 4 and the dividing groove 7 are formed has been described, they may be formed from the surface of the semiconductor substrate 1 as shown in FIG.
以下、第2図について説明する。符号1から7は上記実
施例と同一である。図において、8は表面電極である。Below, FIG. 2 will be explained. Reference numerals 1 to 7 are the same as in the above embodiment. In the figure, 8 is a surface electrode.
次にチップ分割方法について説明する。第2図(A)に
おいて、半導体基板1にフォトレジスト6が塗布され、
Via−Hole4形成用及形成剤用溝7形成用のバタ
ーニングが行なわれる。次に第2図(B)において、ド
ライエツチング法により半導体基板1を所望の深さまで
エツチングし、Via−Hole4及び分割用溝7を同
時に形成する。Next, a chip dividing method will be explained. In FIG. 2(A), a photoresist 6 is applied to the semiconductor substrate 1,
Patterning for forming the via-hole 4 and forming agent groove 7 is performed. Next, in FIG. 2(B), the semiconductor substrate 1 is etched to a desired depth using a dry etching method to form the via-hole 4 and the dividing groove 7 at the same time.
次いで第2図(C)のように、分割用溝7は埋め込んで
置き、Via−Hole4には表面電極8が形成される
。この後、半導体基板1を接着剤3を介しガラス板2に
装着し、半導体基板1裏面を研削し第2図(D)のよう
に、Via−Hole4及び分割用溝7を露出させる。Next, as shown in FIG. 2(C), the dividing groove 7 is buried and a surface electrode 8 is formed in the via-hole 4. Thereafter, the semiconductor substrate 1 is attached to the glass plate 2 via the adhesive 3, and the back surface of the semiconductor substrate 1 is ground to expose the via-hole 4 and the dividing groove 7 as shown in FIG. 2(D).
以下、第2図(E)のようにPH35を形成し、接着剤
3を除去することで第2図(F)のように各チップに分
割される。Thereafter, a PH 35 is formed as shown in FIG. 2(E), and the adhesive 3 is removed to divide into chips as shown in FIG. 2(F).
以上のようにこの発明によれば、ドライエツチング法に
よりVia−Holeを形成すると同時に分割用溝を形
成するようにしたので、エツチングの均性・再現性か良
くなり、分割端面の欠け、チッピング等も無くなり、ま
た従来のスクライブ方法等にガラス板の貼り代え等の工
程も削除でき工程短縮も図れる。As described above, according to the present invention, since the dividing groove is formed at the same time as the via-hole is formed by the dry etching method, the uniformity and reproducibility of etching are improved, and chipping and chipping of the divided end face can be prevented. In addition, steps such as replacing the glass plate with the conventional scribing method can be eliminated, and the process can be shortened.
第1図はこの発明の一実施例による半導体装置の製造方
法を示す工程断面図、第2図はこの発明の他の実施例を
示す工程断面図、第3図及び第4図は従来の半導体装置
の製造方法を示す工程断面図である。
図において、1は半導体基板、2はガラス板、3は接着
剤、4はVia−Hole、5はPH3,6はフォトレ
ジスト、7は分割用溝、8は表面電極を示す。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a process sectional view showing another embodiment of the invention, and FIGS. FIG. 3 is a process cross-sectional view showing a method for manufacturing the device. In the figure, 1 is a semiconductor substrate, 2 is a glass plate, 3 is an adhesive, 4 is a via-hole, 5 is a PH3, 6 is a photoresist, 7 is a dividing groove, and 8 is a surface electrode. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
おいて、Via−Hole形成を行なうと同時にチップ
分割用溝を形成したことを特徴とする半導体装置の製造
方法。1. A method of manufacturing a semiconductor device, characterized in that, in chip dividing a semiconductor device having a via-hole, a groove for chip division is formed at the same time as the via-hole is formed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2075117A JPH03293747A (en) | 1990-03-23 | 1990-03-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2075117A JPH03293747A (en) | 1990-03-23 | 1990-03-23 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03293747A true JPH03293747A (en) | 1991-12-25 |
Family
ID=13566930
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2075117A Pending JPH03293747A (en) | 1990-03-23 | 1990-03-23 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03293747A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003036712A1 (en) * | 2001-10-19 | 2003-05-01 | Applied Materials, Inc. | Method and apparatus for dicing a semiconductor wafer |
WO2002070401A3 (en) * | 2001-03-07 | 2003-12-31 | Applied Materials Inc | Method for fabrication of silicon octopole deflectors and electron column employing same |
US6784022B2 (en) * | 1998-09-02 | 2004-08-31 | Texas Instruments Incorporated | Method of dicing a semiconductor wafer and heat sink into individual semiconductor integrated circuits |
US6878608B2 (en) * | 2001-05-31 | 2005-04-12 | International Business Machines Corporation | Method of manufacture of silicon based package |
US6881649B2 (en) | 2002-07-18 | 2005-04-19 | Fujitsu Limited | Method of making device chips collectively from common material substrate |
-
1990
- 1990-03-23 JP JP2075117A patent/JPH03293747A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6784022B2 (en) * | 1998-09-02 | 2004-08-31 | Texas Instruments Incorporated | Method of dicing a semiconductor wafer and heat sink into individual semiconductor integrated circuits |
WO2002070401A3 (en) * | 2001-03-07 | 2003-12-31 | Applied Materials Inc | Method for fabrication of silicon octopole deflectors and electron column employing same |
US6878608B2 (en) * | 2001-05-31 | 2005-04-12 | International Business Machines Corporation | Method of manufacture of silicon based package |
WO2003036712A1 (en) * | 2001-10-19 | 2003-05-01 | Applied Materials, Inc. | Method and apparatus for dicing a semiconductor wafer |
US6881649B2 (en) | 2002-07-18 | 2005-04-19 | Fujitsu Limited | Method of making device chips collectively from common material substrate |
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