JPH03292742A - J-fet type semiconductor device - Google Patents
J-fet type semiconductor deviceInfo
- Publication number
- JPH03292742A JPH03292742A JP9432390A JP9432390A JPH03292742A JP H03292742 A JPH03292742 A JP H03292742A JP 9432390 A JP9432390 A JP 9432390A JP 9432390 A JP9432390 A JP 9432390A JP H03292742 A JPH03292742 A JP H03292742A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- active layer
- semiconductor device
- doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 15
- 238000005253 cladding Methods 0.000 claims description 7
- 230000005669 field effect Effects 0.000 claims description 4
- 125000005842 heteroatom Chemical group 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000000206 photolithography Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 241000283986 Lepus Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
Landscapes
- Junction Field-Effect Transistors (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体装置に関し、更に詳しくは光電子回路の
集積に通した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor devices, and more particularly to semiconductor devices integrated with optoelectronic circuits.
（従来の技術）
従来より光電子回路の集積度を上げるため、半導体レー
ザとしてもトランジスタとしても使用できる構造が考案
され、例えば図２に示したラテラル型へテロ接合バイポ
ーラトランジスタ型半導体レーザが考案されている。こ
の装置では、エミッタｌとへ一ス２の間を順方向にバイ
アスし活性層６に電子と正札を注入することにより、レ
ーザ発振器として使用でき、また同様にヘース２とコレ
クタ３の間を逆ハいアスすることにより、バイポーラト
ランジスタとしても使用できるような構造をしていた。(Prior Art) In order to increase the degree of integration of optoelectronic circuits, structures that can be used both as semiconductor lasers and transistors have been devised, for example, the lateral heterojunction bipolar transistor semiconductor laser shown in FIG. 2 has been devised. There is. This device can be used as a laser oscillator by applying a forward bias between the emitter 1 and the hemisphere 2 and injecting electrons and genuine tags into the active layer 6. It had a structure that allowed it to be used as a bipolar transistor by adding a high voltage.
（発明が解決しようとする課題）
しかしながら上記従来のラテラル型へテロ接合バイポー
ラトランジスタ型半導体装置を用いた場合、電流増幅率
βを大きくとろうとすると、ベース幅をサブミクロンオ
ーダーとすることが必要となるという課題があった。(Problem to be Solved by the Invention) However, when using the above-described conventional lateral heterojunction bipolar transistor semiconductor device, in order to increase the current amplification factor β, it is necessary to make the base width on the submicron order. There was an issue of becoming.
（課題を解決するための手段）
そこで本発明者らは、鋭意検討の結果、電界効果トラン
ジスタ構造をとることにより、従来製造上の難点となっ
ていたベース幅をサブミクロンオーダーにする必要が無
くなることを見出し本発明に到達した。すなわち本発明
の目的は、トランジスタとしても、レーザ発振器として
も使用でき、かつ容易に製造できる半導体装置を提供す
ることにあり、かかる目的は、ダブルヘテロ埋込み型半
導体装置において活性層と活性層の両端に接するクラッ
ド層をｎ型にドープし、活性層の下のクラッド層は、高
抵抗層とし、活性層の上のクラッド層をＰ型にドープし
たことを特徴とする半導体装置により達成される。(Means for Solving the Problem) As a result of intensive study, the inventors of the present invention found that by adopting a field effect transistor structure, it is no longer necessary to reduce the base width to the submicron order, which has traditionally been a difficult point in manufacturing. This discovery led to the present invention. That is, an object of the present invention is to provide a semiconductor device that can be used both as a transistor and a laser oscillator and that can be easily manufactured. This is achieved by a semiconductor device characterized in that the cladding layer in contact with the active layer is doped n-type, the cladding layer below the active layer is a high-resistance layer, and the cladding layer above the active layer is doped p-type.
以下に本発明の半導体装置の構造の実施例を示す。Examples of the structure of the semiconductor device of the present invention will be shown below.
この図１を用いて本構造の作動原理を説明する。本構造
においてゲート電極１１とソース電極１０またはドレイ
ン電極１２との間を順方向にバイアス電圧を印加するこ
とにより、ｎ型ＧａＡｓ活性層１４に正孔と電子を注入
し、その再結合により光増幅作用を誘起させレーザ発振
する。一方ドレイン電極１２にソース電極ｌＯに対して
正の電圧を印加すると、ｎ型ＧａＡｓ層中に電流が流れ
、ゲート電極１１にバイアス電圧を印加することにより
、ソース電極１０とドレイン電極１２間に流れる電流を
制御でき電界効果トランジスタとしても動作する。バイ
アス電圧は通常はゲート接合の逆方向になるように印加
する。The operating principle of this structure will be explained using FIG. 1. In this structure, by applying a forward bias voltage between the gate electrode 11 and the source electrode 10 or the drain electrode 12, holes and electrons are injected into the n-type GaAs active layer 14, and optical amplification is achieved by their recombination. The laser oscillates by inducing the action. On the other hand, when a positive voltage is applied to the drain electrode 12 with respect to the source electrode lO, a current flows in the n-type GaAs layer, and when a bias voltage is applied to the gate electrode 11, a current flows between the source electrode 10 and the drain electrode 12. It can control the current and also operates as a field effect transistor. The bias voltage is typically applied in the opposite direction of the gate junction.
本装置は、以下のようにして製造することが出来る。This device can be manufactured as follows.
まず最初に半絶縁性ＧａＡｓ基板１９に高抵抗層Ａ１．
Ｇａ、−ＸＡｓ層（アンドープ）１５を０．５μｍ〜５
．０μｍ厚、好ましくは、１．０μｍ〜４０μｍにエピ
タキシャル成長させる。該高抵抗層１５のＸは、０．２
〜０．８５好ましくは０．３〜０．６である。次にその
上にｎ型ＣｙａＡｓ活性層１４を、厚さ、０００５〜０
．５ａｍ好ましくは０゜０５〜０．２μｍ、幅０．５か
ら２０μｍ好ましくは１〜３μｍにエピタキシャル成長
させる。ｉｎ型ＧａＡｓ層はドープされた層であり、そ
のキャリア濃度は１×１０１６〜２Ｘ１０”、好ましく
は、５×ｌ０１６〜５Ｘ１０′７である。 さらにその
上にＰ型Ａｌｙ Ｇａ１−、Ａｓ層１３（ｙは０〜０．
８５好ましくは０．３〜０．６）を０．５μｍ〜３．０
μｍ好ましくは１．０μｍ〜１．５μｍをエピタキシャ
ル成長さセる。該Ｐ型Ａｌ、Ｇａ、−、Ａｓ層１３もド
ープ層であり、キャリア濃度はｌＸｌ０Ｉ７〜５×１０
”、好ましくは、５Ｘ１０”〜２ＸＩＯ１１＋である。First, a high resistance layer A1.
Ga, -XAs layer (undoped) 15 with a thickness of 0.5 μm to 5
．． Epitaxial growth is performed to a thickness of 0 μm, preferably 1.0 μm to 40 μm. X of the high resistance layer 15 is 0.2
-0.85, preferably 0.3-0.6. Next, an n-type CyaAs active layer 14 is formed thereon to a thickness of 0005 to 0.
．． It is epitaxially grown to a thickness of 5 am, preferably 0°05 to 0.2 μm, and a width of 0.5 to 20 μm, preferably 1 to 3 μm. The in-type GaAs layer is a doped layer, and its carrier concentration is 1×10 16 to 2×10”, preferably 5×10 16 to 5 y is 0 to 0.
85 preferably 0.3 to 0.6) to 0.5 μm to 3.0
The epitaxial growth is preferably 1.0 μm to 1.5 μm. The P-type Al, Ga, -, As layer 13 is also a doped layer, and the carrier concentration is lXl0I7~5x10
", preferably 5X10" to 2XIO11+.
その上にはＰ型ＧａＡｓ層１６を、０．０１〜１．０μ
ｍ好ましくは０．０５〜０．２μｍエピタキシャル成長
させる。該Ｐ型ＧａＡｓ層１６のキャリア濃度はｌＸｌ
０”〜５Ｘ１０”、好ましくは５ｘ ｌ Ｑ Ｉ１１〜
５Ｘ１０′９である。この上に窒化シリコン膜を堆積さ
せ、これをフォトリソグラフィー法によりパターンニン
グを行った後、ソース部及びドレイン部となる部分の窒
化シリコン膜を除去する。その後ソース部及びドレイン
部をウエントエンチング又は、ドライエツチングにより
取り除き取り除かれた部分にｎ型Ａｌｚ Ｇａ＋−ｚ
Ａｓ層１７（厚さ ０１〜２μｍ好ましくは０．５〜１
．０μｍ、 ｚは０〜０．６好ましくは０．２〜０．
５．キャリア濃度は１ｘｌＯ１７〜５×１０１８、好ま
しくは、５×１０′７〜２Ｘ１０１８）とキャップ層で
あるｎ型 ＣａＡｓ層１８（キャリア濃度は５×ｌ０１
７〜５×１０１、好ましくは、ｌＸｌ０”〜３Ｘ１０”
）を選択エピタキシャル成長させ、最後にそれぞれソー
ス電極１０．ゲート電極１１．トレイン電極１２を取り
つけ、またケート部のＰ型ＧａＡｓキャ、プ層を、ウェ
ットエツチングにより一部除去して製造する。On top of that, a P-type GaAs layer 16 of 0.01 to 1.0μ
It is preferably epitaxially grown to a thickness of 0.05 to 0.2 μm. The carrier concentration of the P-type GaAs layer 16 is lXl
0" ~ 5X10", preferably 5x l Q I11 ~
It is 5X10'9. A silicon nitride film is deposited on this and patterned by photolithography, and then the silicon nitride film in the portions that will become the source and drain portions is removed. After that, the source part and the drain part are removed by wet etching or dry etching, and the removed part is covered with n-type Alz Ga+-z.
As layer 17 (thickness: 01 to 2 μm, preferably 0.5 to 1
．． 0 μm, z is 0 to 0.6, preferably 0.2 to 0.
5. The carrier concentration is 1xlO17 to 5x1018, preferably 5x10'7 to 2x1018) and the n-type CaAs layer 18 as a cap layer (the carrier concentration is 5x101).
7 to 5×101, preferably lXl0” to 3×10”
) are selectively epitaxially grown, and finally source electrodes 10.) are selectively grown. Gate electrode 11. A train electrode 12 is attached, and a portion of the P-type GaAs cap layer in the gate portion is removed by wet etching.
（発明の効果）
本発明によれば、電界効果トランジスターと半導体レー
ザとを、同一の基板上で構成できるため高度集積化を可
能とするのみならず、従来の同種の装置の課題であった
製造上の困難さを大幅に滅し、実用性を増した。(Effects of the Invention) According to the present invention, a field effect transistor and a semiconductor laser can be configured on the same substrate, which not only makes it possible to achieve a high degree of integration, but also improves manufacturing efficiency, which was a problem with conventional similar devices. This greatly eliminates the above-mentioned difficulties and increases practicality.
図１は本発明のＪ−ＦＥＴ型半導体装置の実施例を模式
的に示した説明図であり、図２は、従来から提案されて
いたラテラル型へテロ接合バイポーラトランジスタ型半
導体装置の構造の説明図である。FIG. 1 is an explanatory diagram schematically showing an embodiment of the J-FET type semiconductor device of the present invention, and FIG. 2 is an explanation of the structure of a conventionally proposed lateral heterojunction bipolar transistor type semiconductor device. It is a diagram.
ｌ：エミッタ ２：ヘース ３：コレクター４：ｎ型Ｇ
ａＡｓ層 ５：ｎ型ＡｌＧａＡｓ層６：活性層 ７：Ｐ
型ＡｌＧａＡｓ層
８：高抵抗ＡｌＧａＡｓ層
９：半絶縁性ＧａＡｓ基板 １０：ソース電極１１：ゲ
ート電極 １２ニドレイン電極１３：Ｐ型ＡｌｙＧａ＋
−、Ａｓ層
１４：ｎ型ＧａＡｓ層（活性層）
１５：高抵抗Ａｌｘ Ｇａ＋−ｘ Ａｓ層１６：Ｐ型Ｇ
ａＡｓ層
１７：ｎ型ＡＩ２ Ｇａ＋−、Ａｓ層
１８：ｎ型ＧａＡｓ層
１９：半絶縁性ＧａＡｓ基板
出 願 人 工業技術院長 （ほか１名）復代理人 弁
理士 長谷用 −（ばか１名）図２l: Emitter 2: Heath 3: Collector 4: N-type G
aAs layer 5: n-type AlGaAs layer 6: active layer 7: P
Type AlGaAs layer 8: High resistance AlGaAs layer 9: Semi-insulating GaAs substrate 10: Source electrode 11: Gate electrode 12 Nidrain electrode 13: P-type AlyGa+
-, As layer 14: n-type GaAs layer (active layer) 15: high resistance Alx Ga+-x As layer 16: P-type G
aAs layer 17: n-type AI2 Ga+-, As layer 18: n-type GaAs layer 19: semi-insulating GaAs substrate Applicant Director of Institute of Industrial Science and Technology (1 other person) Sub-agent Patent attorney For Hase - (1 idiot) Figure 2
Claims (4)
と活性層の両端に接するクラッド層をｎ型にドープし、
活性層の下のクラッド層は、高抵抗層とし、活性層の上
のクラッド層をＰ型にドープしたことを特徴とする半導
体装置。(1) In a double hetero buried semiconductor device, the active layer and the cladding layer in contact with both ends of the active layer are doped n-type,
A semiconductor device characterized in that a cladding layer below an active layer is a high resistance layer, and a cladding layer above the active layer is doped to be P-type.
Ａｓキャップ層を持ち、キャップ層の一方の上にソース
電極、他方の上にドレイン電極を設置し、さらに活性層
の上のＰ型にドープされた該活性層上にＰ型ＧａＡｓキ
ャップ層を、さらにその上にゲート電極を持つ請求項１
記載の半導体装置(2) N-type Ga on the cladding layer in contact with both ends of the active layer
It has an As cap layer, a source electrode is placed on one side of the cap layer, a drain electrode is placed on the other side, and a P type GaAs cap layer is placed on the P type doped active layer above the active layer. Claim 1 further comprising a gate electrode thereon.
Semiconductor device described
に順方向に電圧を印加することによりレーザ発振する請
求項２記載の半導体装置(3) The semiconductor device according to claim 2, which oscillates by applying a voltage in the forward direction between the gate electrode and the source or drain electrode.
可し、さらにゲート電極にバイアス電圧を印加すること
により電界効果トランジスタとして働く請求項２記載の
半導体装置(4) The semiconductor device according to claim 2, which operates as a field effect transistor by applying a positive voltage to the drain electrode with respect to the source electrode and further applying a bias voltage to the gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2094323A JP3036600B2 (en) | 1990-04-10 | 1990-04-10 | J-FET type transistor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2094323A JP3036600B2 (en) | 1990-04-10 | 1990-04-10 | J-FET type transistor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03292742A true JPH03292742A (en) | 1991-12-24 |
| JP3036600B2 JP3036600B2 (en) | 2000-04-24 |
Family
ID=14107076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2094323A Expired - Lifetime JP3036600B2 (en) | 1990-04-10 | 1990-04-10 | J-FET type transistor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3036600B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4507285B2 (en) * | 1998-09-18 | 2010-07-21 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
-
1990
- 1990-04-10 JP JP2094323A patent/JP3036600B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4507285B2 (en) * | 1998-09-18 | 2010-07-21 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3036600B2 (en) | 2000-04-24 |
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