JPS63102258A - Manufacture of bipolar semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate a plurality of stepwise mesa etching and the like thereby to facilitate a high integration of a semiconductor device by forming a step on a GaAs substrate, exposing a surface having (111)A of an index as an oblique surface of the step, and then forming an Si-doped GaAs compound semiconductor layer. CONSTITUTION:A GaAs substrate 1 is selectively etched to form a step. A surface having (111) of an index is exposed on an oblique surface 1A which forms the step. Then, an undoped GaAs active layer 2, an Si-doped AlGaAs carrier supplying layer 3 and an Si-doped GaAs contact layer 4 are formed by an MBE method. A semiconductor layer grown on a part having (100) of an index on the substrate 1 becomes an n-type, and a semiconductor layer grown on a part having (111)A of an index becomes a p-type. This p-type GaAs region is used as a base region B, the n-type GaAs regions at both sides are used as an emitter region E and a collector region C to form a lateral bipolar semiconductor device.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a method for manufacturing a bipolar semiconductor device.
A GaAs substrate with a (100) plane has a (111) slope.
A step is formed on the A side, and then a small (Si-doped GaAs-based compound semiconductor layer) is formed on the entire surface.
111) P-wall region on A-plane and n-wall region on (100) plane
A high-speed lateral bipolar transistor that can be highly integrated by forming a type region, a base electrode on the p-type region, and an emitter electrode and a collector electrode on the n-type region sandwiching it. This makes it easy to manufacture.

[Industrial application field]

The present invention relates to a method for manufacturing a bipolar semiconductor device suitable for manufacturing a lateral force bipolar transistor that can be easily manufactured at high speed and highly integrated.

[Conventional technology]

Currently, as one of the next-generation high-speed semiconductor devices, much research and development is being conducted on bipolar semiconductor devices that use compound semiconductors that have higher electron mobility than silicon and their higher integration.

A conventional compound semiconductor bipolar semiconductor device is a heterojunction bipolar semiconductor device (heterojunction bipolar semiconductor device).
bipolar transistor:H
Various semiconductor layers, including BT), are grown by molecular beam epitaxial growth (molecular beam epitaxial growth).
It has a vertical structure laminated using the beam epitaxy (MBE) method.

[Problem that the invention seeks to solve]

In order to manufacture a semiconductor device according to the above-mentioned conventional technology, when forming electrodes such as a base electrode and an emitter electrode, it is necessary to perform step-like mesa etching with large steps on each semiconductor layer, and this etching is easy. Not only is it not,
Due to the presence of the plurality of large steps, it is extremely disadvantageous for high integration. Also, between base and emitter,
Alternatively, there is a structural limit to reducing the capacitance between the base and the collector.

The present invention provides a method for manufacturing a high speed lateral bipolar semiconductor device that does not require multiple stepped mesa etchings and is easily highly integrated.

[Means for solving problems]

In the method for manufacturing a bipolar semiconductor device according to the present invention, a GaAs substrate (
For example, a step is formed on a semi-insulating GaAs substrate 1), and a slope (for example, slope IA) at the step has a surface index of (1).
11) A step of exposing the surface A, and then exposing at least a 3i-doped GaAs-based compound semiconductor layer (for example, Si
doped AAGaAs carrier supply layer 3, etc.), and then a base electrode (for example, base electrode 8) corresponding to the plane with the plane index of (111) A, and a step of forming a base electrode (for example, the base electrode 8) with the plane index of (111) A on both sides of the base electrode. The configuration includes a step of forming an emitter electrode (for example, emitter electrode 6) and a collector electrode (for example, collector electrode 7) corresponding to the plane where is (100).

[Effect]

By adopting the above-mentioned method, a so-called lateral transistor in which pn junctions are arranged laterally can be easily manufactured without requiring a complicated process such as mask alignment, and the bipolar transistor thus obtained can be easily manufactured. Since the semiconductor device has a planar structure, all electrodes are taken out from the surface side, which is very advantageous when integrating compared to a vertical structure, and also depends on the selection of the semiconductor layer structure. Since it is possible to use a two-dimensional carrier gas layer, it is possible to obtain an extremely high-speed bipolar semiconductor device, and furthermore, because the parasitic capacitance between the base and collector can be reduced, it is possible to achieve even higher speeds. It is.

〔Example〕

1 to 3 are cross-sectional side views of essential parts of a bipolar semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures.

Refer to FIG. 1. (1) By applying ordinary photolithography technology, a semi-insulating GaAs substrate 1 with a surface index of (100) is selectively etched to a depth D of, for example, 0.2 [
[μm]] is formed.

In this way, the slope IA that forms a step has a surface index (
111) The surface that is A is exposed.

(2) By applying the MBE method, undoped G
aAs active layer 2, Si-doped Aj! A GaAs carrier supply layer 3 and a Si-doped GaAs contact layer 4 are formed.

Examples of main data in each semiconductor layer in this case are as follows.

■ Active layer 2 thickness: 0.5Cμm] ■Carrier supply layer 3 thickness: 0.1Cμm] Impurity concentration: I x 10I8 (cm-”) ■ Contact layer 4 thickness: 0.2Cμm] Impurity 4 degree = I X 10''(am-') In this way, the semiconductor layer grown on the part of the substrate 1 whose plane index is (100) becomes n-type, and whose plane index is (am-').
111) The semiconductor layer grown on the part A becomes p-type. Therefore, the active layer 2 is composed of an n-type GaAs region 2A and a p-type GaAs pJi region 2B, and the carrier supply layer 3 is composed of an n-type GaAs region 3A and a p-type GaAs pJi region 2B.
s region 3B, and the contact layer 4 is made of n-type Ga.
It is composed of an As region 4A and a p-type Ga As region 4B.

Therefore, the p-type GaAs regions 2B, 3B, and 4B are sandwiched between the n-type GaAs jl regions 2A, 3A, and 4A from both sides.

Therefore, a lateral bipolar semiconductor device is constructed in which this p-type Q a A S jJ region is used as a base region B, and the n-type Ga As regions on both sides thereof are used as an emitter region E and a collector region C. Incidentally, since the interface between the active layer 2 and the carrier supply layer 3 is a heterojunction surface, a two-dimensional carrier gas layer 5 is generated on the active layer 2 side near the interface.

Since the formation of such n-type and p-type regions occurs naturally according to the planar index of the underlying semiconductor layer, there are no troublesome problems in the process.

Refer to FIG. 3 (3) By applying a vacuum evaporation method and a lift-off method, a base electrode 8 is formed, and an alloying heat treatment is performed to establish ohmic contact with the semiconductor layer.

Examples of main data regarding this electrode 8 are as follows.

Material: A u / Z n / A u thickness: 300
0 (people) / 300 (people) / 300 [people] Heat treatment temperature: 460 ('C) Heat treatment time = 5 [minutes] (4) By applying the vacuum evaporation method and lift-off method, the emitter electrode 6 , a collector electrode 7 is formed, and alloying heat treatment is performed to establish ohmic contact with the semiconductor layer.

Examples of main data regarding these electrodes 6.7 are as follows.

Material: Au/AuGe Thickness: 3000 (person)/300 (person) Heat treatment temperature:
430 ("C) Heat treatment time: 1 [minute] Accordingly, alloying regions 6A, 7 reach from each electrode 6.7.8 to the corresponding two-dimensional carrier gas layer 5, respectively.
A, 8A is formed.

The bipolar semiconductor device obtained according to the above embodiment utilizes a two-dimensional carrier gas layer, but does not use combinations such as the active layer 2 and the carrier supply layer 3 (or only the Si-doped GaAs layer). It is also possible to form a normal npn lateral bipolar semiconductor device.

〔Effect of the invention〕

In the method for manufacturing a bipolar semiconductor device according to the present invention, a GaAs substrate having a (100) plane has an inclined plane (11
1) Form a step on side A, then create a small (
In both cases, a Si-doped GaAs-based compound semiconductor layer is formed, a p-type head region is formed on the (111) A plane, an n-type region is formed on the (100) plane, and a base electrode is formed on the p-type region. An emitter electrode and a collector electrode are formed on the n-type region sandwiching the.

By adopting the above structure, a so-called lateral transistor in which pn junctions are arranged in a horizontal direction can be easily manufactured without requiring a complicated process such as mask alignment, and the bipolar transistor thus obtained can be easily manufactured. Since the semiconductor device has a planar structure, all electrodes are taken out from the surface side, which is very advantageous when integrating compared to a vertical structure, and also depends on the selection of the semiconductor layer structure. Because a two-dimensional carrier gas layer can be used, an extremely high-speed bipolar semiconductor device can be obtained, and furthermore, because the parasitic capacitance can be reduced, the speed can be further increased.

[Brief explanation of the drawing]

1 to 3 are cross-sectional side views of essential parts of a lateral bipolar semiconductor device 7 at key points in the process for explaining one embodiment of the present invention. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an undoped GaAs active layer, 3 is a Si-doped AAGaAs carrier supply layer, 4 is a Si-doped GaAs contact layer, and 5 is a Si-doped GaAs contact layer.
denotes a two-dimensional carrier gas layer, 6 an emitter electrode, 7 a collector electrode, and 8 a base electrode. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney: Shoji Aitani Representative Patent Attorney: Hiroshi Watanabe - Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] A step is formed on a GaAs substrate whose main surface has a surface index of (100), and the slope of the step has a surface index of (111).
A step of exposing the surface that is A, and then at least
a step of forming an i-doped GaAs-based compound semiconductor layer, and then forming a base electrode corresponding to the plane with the plane index of (111)A and sandwiching the base electrode with the plane index of (111)A;
100) A method for manufacturing a bipolar semiconductor device, comprising the step of forming an emitter electrode and a collector electrode corresponding to a surface.