JPH03290974A - Thin film transistor memory - Google Patents

Abstract

PURPOSE:To enable execution of stable writing, erasure and reading and also to increase component density and to facilitate manufacture by constructing a thin film transistor for a memory and a thin film transistor for selection in lamination and by preventing the effect of a gate voltage. CONSTITUTION:A thin film transistor TrT20 for selection is constructed in lamination on a thin film TrT10 for a memory which is constructed by laminating a lower gate electrode G10, a lower gate insulation film 13, a semiconductor layer 14 and source and drain electrodes S and D. In this case, the TrT20 is so constructed that an upper gate electrode G20 and an upper gate insulation film 16 are laminated and that the layer 14 and the electrodes S and D are shared. The film 13 is formed on a flattening insulation film 12 and the electrode G20 is formed to be opposite to the whole of the layer 14, while the film thickness of the film 16 is made large on the part of the layer 14 corresponding to a memory area. Accordingly, a malfunction due to the effect of a gate voltage impressed on the electrode G10 and the electrode G20 is eliminated and execution of stable writing, erasure and reading is enabled. Besides, component density is increased and easy manufacture can be realized by a reduced number of processes.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to thin film transistor memories.

[Conventional technology]

Recently, E2FR that can be electrically written, erased, and read
As a memory such as an OM, a thin film transistor memory in which a memory transistor and a selection transistor are formed of thin film transistors has been considered.

Conventionally, this thin film transistor memory is formed by forming a thin film transistor for memory (hereinafter referred to as a memory transistor) and a thin film transistor for selection (hereinafter referred to as a selection transistor) adjacent to each other on an insulating substrate made of glass or the like. A transistor memory is known in which a transistor and a selection transistor are connected in series through a connection wiring that connects the source electrode of one transistor and the drain electrode of the other transistor. Note that the memory transistor and the selection transistor are each constructed by stacking a gate electrode, a gate insulating film, an i-type semiconductor layer, and a source and drain electrode, and the gate insulating film of the memory transistor has a charge storage function. The gate insulating film of the selection transistor is formed of an insulating film that does not have a charge storage function.

FIG. 18 is an equivalent circuit diagram of the conventional thin film transistor memory. Here, an equivalent circuit of a thin film transistor memory provided with two selection transistors for one memory transistor is shown.

In FIG. 18, T1 is a memory transistor, T2 is two selection transistors arranged on both sides of the memory transistor T1, and the source electrode S1 of the memory transistor T1 is connected to the drain electrode D2 of one selection transistor T2. The drain electrode D1 of the transistor T1 is the source electrode S2 of the other selection transistor T2.
It is connected to the. The source electrode S2 of the one selection transistor T2 is the source electrode S of a transistor memory. The drain electrode D2 of the other selection transistor T2 is the drain electrode of the transistor memory. The source electrode So is connected to a source line (not shown), and the drain electrode So is connected to a source line (not shown). is connected to a drain line (not shown). Furthermore, the gate electrode G1 of the memory transistor T is connected to a first gate line (not shown), and the gate electrodes G2 of the two selection transistors T2 are commonly connected to a second gate line (not shown). Note that a large number of the first and second gate lines are wired in parallel, and a large number of source lines and drain lines are wired orthogonally to the gate lines,
The thin film transistor memory constituted by the memory transistor T1 and the selection transistor T2 includes the first . Second
They are formed at the intersections of the gate line and the source and drain lines, respectively.

Writing and erasing of this thin film transistor memory.

Reading is performed as follows.

In FIG. 18, (a) shows the state of voltage application during writing, (b) shows the state of voltage application during erasing, and (c) shows the state of voltage application during reading.

First, writing will be explained. During writing, as shown in FIG. 18(a), the source electrode S is opened. and drain electrode. is grounded (GND), an ON voltage VON is applied to the gate electrode G2 of the selection transistor T2, and a write voltage + is applied to the gate electrode G of the memory transistor T1.
Apply vP.

When such a voltage is applied, the selection transistor T2 is turned on, and a write voltage voltage VP is applied between the gate electrode G1 and the source and drain electrodes St, D+ of the memory transistor T1, and the memory transistor T is in the write state (OFF). state).

Further, during erasing, as shown in FIG. 18(b), the source electrode S. and drain electrode. is grounded (GND) and connected to the gate electrode G2 of the selection transistor T2.
Applying a voltage ■i to the gate electrode G1 of the memory transistor T1, an erase voltage −v, which is a potential opposite to the write voltage +■, is applied to the gate electrode G1 of the memory transistor T1.
Apply P. When such a voltage is applied, the selection transistor T2 is turned on, and the gate electrode G1 and the source and drain electrodes S, D of the memory transistor T1 are turned on.

A potential difference (Vp) opposite to the write voltage +V is generated between the write voltage +V and the memory transistor T becomes in an erased state (ON state).

On the other hand, during reading, as shown in FIG. 18(c), the gate electrode G1 and source electrode S of the memory transistor T.

is grounded (GND), and the selection transistor T2
ON voltage ■ to the gate electrode G2. Apply N and connect the drain electrode. A voltage vp is applied one after another. When such a voltage is applied, the memory transistor T1 goes into the erased state (O
If it is in N state), it is the drain electrode. from the source electrode S.

A current flows through the memory transistor T1, and the memory transistor T1 enters the write state (
OFF state), the current does not flow, so the source electrode S. Read data is output depending on the presence or absence of current flowing through the source line.

Note that although a thin film transistor memory including two selection transistors T2 for one memory transistor T1 has been described here, some thin film transistor memories include one selection transistor for one memory transistor. .

[Problem to be solved by the invention]

However, the conventional thin film transistor memory
A thin film transistor for memory and a thin film transistor for selection are formed adjacent to each other on a substrate, and the memory transistor and selection transistor are connected in series by connection wiring. Therefore, it is difficult to increase the degree of integration of a memory matrix formed by arranging transistor memories vertically and horizontally.

Moreover, in conventional thin film transistor memories, the gate insulating film of the memory thin film transistor is an insulating film with a charge storage function, and the gate insulating film of the selection thin film transistor is an insulating film without a charge storage function. There is also a problem in that the thin film transistor for selection and the thin film transistor for selection must be manufactured in separate processes, and therefore a large number of processes are required to manufacture the thin film transistor memory.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to reduce the element area of a transistor memory composed of a memory thin film transistor and a selection thin film transistor, thereby increasing the degree of integration. It is an object of the present invention to provide a thin film transistor memory that can be manufactured into a package with a small number of steps.

[Means to solve the problem]

The thin film transistor memory of the present invention includes a lower gate electrode formed on an insulating substrate, a lower gate insulating film having a charge storage function and formed on the substrate covering the lower gate electrode, and the lower gate insulating film. a semiconductor layer formed thereon, source and drain electrodes formed on both sides of this semiconductor layer, and an upper gate insulator without a charge storage function formed on the semiconductor layer and the source and drain electrodes. film and the upper gate formed on this upper gate insulating film? IS pole, the lower gate electrode, the lower gate insulating film, the semiconductor layer, and the source.

The drain electrode constitutes a memory thin film transistor,
The semiconductor layer, the source and drain electrodes, the upper gate insulating film, and the upper gate electrode constitute a selection thin film transistor, and the lower gate electrode is formed on a portion of the semiconductor layer on the lower gate line formed on the substrate. a portion of the lower gate insulating film facing the lower gate electrode is formed as a memory region;
The lower gate insulating film is formed on a planarizing insulating film formed on the substrate to a thickness that covers the lower gate line and exposes the upper surface of the lower gate electrode, and the upper gate electrode is formed on the semiconductor substrate. The upper gate insulating film is formed to face the entire layer, and the thickness of the upper gate insulating film is increased over a portion of the semiconductor layer corresponding to the memory region.

[Effect]

That is, the thin film transistor memory of the present invention has an upper part without a charge storage function on top of a memory thin film transistor configured by laminating a lower gate electrode, a lower gate insulating film with a charge storage function, a semiconductor layer, and source and drain electrodes. A gate insulating film and an upper gate electrode are laminated to form a selection thin film transistor that shares the semiconductor layer and source and drain electrodes with a memory thin film transistor. Although this thin film transistor memory is constructed by stacking a memory thin film transistor and a selection thin film transistor, it is possible to increase the degree of integration by reducing the element area of the transistor memory composed of a memory thin film transistor and a selection thin film transistor. Furthermore, since the semiconductor layer and the source and drain electrodes are shared by the memory thin film transistor and the selection thin film transistor, it can be easily manufactured with a small number of steps. In this thin film transistor memory, the lower gate electrode is formed to protrude above the lower gate line formed on the substrate so as to face a part of the semiconductor layer, and the part of the lower gate insulating film facing the lower gate electrode is formed to protrude above the lower gate line formed on the substrate. The lower gate insulating film is formed on the flattening insulating film formed on the substrate in a JV shape covering the lower gate line and exposing the upper surface of the lower gate electrode, and the upper gate electrode is formed on the semiconductor layer as a memory area. The upper gate insulating film is formed so as to face each other as a whole, and the thickness of the upper gate insulating film is made thicker on the portion of the semiconductor layer corresponding to the memory region, so that the selection thin film transistor region of the semiconductor layer and the gate of the memory thin film transistor are formed. between the lower gate electrode, which is an electrode (between the lower gate line), and between the memory thin film transistor region of the semiconductor layer (the portion corresponding to the memory region of the lower gate insulating film) and the upper gate, which is the gate electrode of the selection thin film transistor. It is possible to reliably insulate and separate the electrodes from each other. Therefore, according to this thin film transistor memory, the selection thin film transistor does not malfunction due to the influence of the gate voltage applied to the gate electrode (lower gate electrode) of the memory thin film transistor, and the memory thin film transistor Because it does not malfunction due to the influence of the gate voltage applied to the upper gate electrode (upper gate electrode), the memory The thin film transistor for use and the thin film transistor for selection operate normally for stable writing.

Erasing and reading can be performed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

1 to 10 show a first embodiment of the present invention, and FIGS. 1 and 2 are a sectional view and a plan view of a thin film transistor memory.

To explain the structure of this thin film transistor memory, numeral 11 in the figure is an insulating substrate made of glass or the like;
1 has a lower gate electrode G on it. is formed. This lower gate electrode G1o is a lower gate line GL formed on the substrate 11. The lower gate electrode G is formed to protrude locally on top of the lower gate electrode G. is the lower gate line G
It is formed to have the same width as L and o and a thickness of 3000 people. Further, on the substrate 11, an upper gate electrode GIO
The lower gate line GL, except for the top surface of. A planarizing insulating film 12 is formed to cover the entire structure. ``This planarizing insulating film 12 is made of an insulating film that does not have a charge storage function, and the upper surface of this planarizing insulating film 12 is connected to the lower gate electrode G.

The thickness of the film is almost flush with the top surface of the film. Then, on this planarizing insulating film 12, a lower gate insulating film 13 covering the lower gate electrode GIO is formed over almost the entire surface of the substrate 11. This upper gate insulating film 13 has a charge storage function throughout its upper layer, and this lower gate insulating film 13 has a lower layer insulating film 1''3 made of SiN (silicon nitride) that does not have a charge storage function.
On a, a memory insulating film 1 made of SiN having a charge storage function by increasing the composition ratio of Si (silicon).
It is a two-layer film in which 3b is laminated.

The thickness of the lower insulating film 13a is 1900, and the thickness of the memory insulation N15b is 100.

On this lower gate insulating film 13 (memory insulating film 13b)
An L-type semiconductor layer 14 made of amorphous silicon or polysilicon is formed in a pattern corresponding to the element shape of a transistor memory. (Amorphous silicon or polysilicon doped with n-type impurities)
A source electrode S and a drain electrode are formed via an ohmic contact layer 15 consisting of the following. The source electrode S and drain electrode line are connected to a source line SL and a drain line DL, respectively, which are wired on the lower gate insulating film 13 so as to be perpendicular to the lower gate lines GL and o. On the semiconductor layer 14 and the source and drain electrodes S and D, an upper gate insulating film 16 made of silicon nitride and having no charge storage function is formed over almost the entire surface of the substrate 11. On top of this upper gate insulating film 16, there is an upper gate line GL.
2o is wired parallel to the lower gate line GL+o, and a portion of the upper gate line GL2o above the semiconductor layer 14 is used as an upper gate electrode G20.

The lower gate electrode Gltl, the lower gate insulating film 13 having a charge storage function, the semiconductor layer 14, and the source and drain electrodes S and D are connected to an inverted staggered memory thin film transistor (hereinafter referred to as a memory transistor) Too. It consists of

Also, a lower gate electrode G, which is the gate electrode of this memory transistor T1o. is formed to face the central part of the semiconductor layer 14 in the channel length direction (the central part between the source and drain electrodes S and D) and has a width that is approximately 1/3 of the width of the semiconductor layer 14 in the channel length direction. Therefore, only the central portion of the lower gate insulating film 13 facing the lower gate electrode GIO serves as a memory region.

On the other hand, the upper gate electrode G20 is an electrode facing the entire semiconductor layer 14.
The upper gate insulating film 16 between 20 and the semiconductor layer 14 is
Memory region of lower gate insulating film 13 (lower gate electrode G
,. The thickness of the film is increased in the upper part of the upper part (the same part of the same part) and the part outside from the position facing approximately the center of the source and drain electrodes S and D, and the film thickness is increased between the memory region and the source electrode S and the memory region. The insulating film is made thinner in the portion between the drain electrode and the drain electrode. Note that this upper gate insulation W! The film thickness portion 16 is formed over the entire length of the insulating film in the length direction of the source and drain lines SL and DL. The thickness of the upper gate insulating film 16 is such that a gate voltage is applied from the upper gate electrode G20 to the memory transistor Tlo region of the semiconductor layer 14 (a portion corresponding to the memory region of the lower gate insulating film 13). The film thickness of the thin film portion of the upper gate insulating film 16 is set to be a thickness sufficient to prevent this from occurring (5,000 layers in this embodiment), and the thickness of the thin film portion of the upper gate insulating film 16 is such that a sufficient gate voltage can be applied to the semiconductor layer 14 from the upper gate electrode G20. (2,000 people in this example).

Then, on the memory transistor T Ill,
The semiconductor layer 14 and the source and drain electrodes S.

Two selection thin film transistors (hereinafter referred to as selection transistors) that share D with the memory transistor TIO
Tzo and T2O are formed. These two selection transistors T2o and T2o are Coplanar thin film transistors composed of the semiconductor layer 14, source and drain electrodes S and D, an upper gate insulating film 16 without a charge storage function, and an upper gate electrode G20. , one selection transistor T2° has a semiconductor layer 14 and a source,
Drain electrode S.

D, one thin film portion of the upper gate insulating film 16, and an upper gate electrode G20, and the other selection transistor T20 is composed of the semiconductor layer 14, the source and drain electrodes S, D, and the upper gate insulating film 16. and the upper gate electrode G20.

These two selection transistors T20+T2o are
The gate electrode (upper gate electrode) G20 is connected to the semiconductor layer 1
By making the electrodes opposite to the entirety of T4, they are commonly connected on the gate side, and both selection transistors T2o and T2o are connected in common on the gate side.
, T2o is a memory transistor T, by sharing its source and drain voltages iS,D with the memory transistor T1o. connected in series with.

Further, the two thin film portions of the upper gate insulating film 16 constituting the selection transistors T 2o and T 2o each have a width in the channel length direction of the film thickness portion of the lower gate insulating film 13 corresponding to the memory area. Electrode G
,. By making the width smaller than the width in the channel length direction, it is possible to overlap both sides of the lower gate electrode GIO.

This is done in order to ensure electrical connection between the memory transistor T1o and both selection transistors T2O1720, and the thin film portions of the upper gate insulating film 16 constituting the selection transistors T2n and T20 are connected to the lower gate electrode GIO. By wrapping the memory transistor T1o region of the semiconductor layer 14 and the selection transistor T2
A memory transistor T1 is provided at the boundary with the ゜ region (both sides of the portion of the lower gate insulating film 13 corresponding to the memory region).
o gate electrode (lower gate electrode) G+.

Since the gate voltage can be applied from the gate electrode (upper gate electrode) G20 of the selection transistors T2° and T2°, the memory transistor TIO and the selection transistor T2. ．． When both T2o and T2o are turned on, a current flows from the drain electrode to the source electrode S via the semiconductor layer 14. In this embodiment, the width of the thick portion of the upper gate insulating film 16 above the memory region is approximately 1/2 of the width of the upper gate electrode Czo, or the width of the thick portion of the upper gate insulating film 16 is approximately 1/2 of the width of the lower gate electrode GIG. Any width may be used as long as it is less than the width of .In short, it is sufficient that the thin film portion of the upper gate insulating film 16 faces at least the side edge of the lower gate electrode GILL.

FIG. 3 shows a method for manufacturing the thin film transistor memory, and this thin film transistor memory is manufactured through the following steps.

First, as shown in FIG. 3(a), a metal film 30 that will become the gate line G L is deposited to a thickness of 500 nm on the substrate 11, and a lower gate electrode G is deposited thereon.

A metal film 31 is deposited to a thickness of 3000 mm.

Note that the upper metal film 31 that becomes the lower gate electrode GIO is formed of Ta (tantalum) or the like, and the gate line GL,
The lower metal film 30, which is the metal film 30, is formed of a metal having a different etching rate from that of the upper metal film 31, such as Cr (chromium).

Next, as shown in FIG. 3(b), the upper metal film 31 is patterned by photolithography to form a lower gate electrode G. is formed, and then the lower metal film 30 is patterned by photolithography to form gate lines G L , .

Next, as shown in FIG. 3(c), a planarizing insulating film 12 made of SIN or the like is deposited on the entire surface of the substrate 11 to the same thickness (3000 layers) as the lower gate electrode G,1. Next, as shown in FIG. 3(d), a lower gate electrode G of this flattened insulating film 12 is formed. The portion covering the lower gate voltage tlfi is removed by etching using photolithography.
A planarizing insulating film 12 is formed to cover the entire lower gate lines G L and o except for the top surface of r o.

Next, as shown in FIG. 3(e), the planarized insulating film 1
2 and the lower gate electrode GIO, a lower insulating film (SIN film) 13a without a charge storage function, and a memory insulation film (SIN film with a high composition ratio of Sl) having a charge storage function.
membrane) 13b, 1900 people.

A two-layer lower gate insulating film 13 consisting of a lower insulating film 13a and a memory insulating film 13b is formed by sequentially depositing the film to a thickness of 100 nm, and on top of this, an i-type amorphous silicon or i-type insulating film 13 is formed. Semiconductor layer 1 made of polysilicon
4 and n-type semiconductor (n-type amorphous silicon or n-type semiconductor
ohmic contact layer 15 made of (type polysilicon)
1000 people.

The metal film 40 for source and drain electrodes made of Cr or the like is deposited successively to a thickness of 250 mm.
Deposit to a thickness of 500 people.

Next, the metal film 40 for source and drain electrodes is patterned by photolithography, as shown in FIG. 3(f).
As shown in the figure, the source and drain electrode metal If!
The source and drain electrodes S, D and the source and drain line 5LDL are formed, and then the ohmic contact layer 15 is formed between the source and drain electrodes S, D and the source.

Patterning is performed in the shape of drain lines SL and DL.

Next, as shown in FIG. 3(g), the semiconductor layer 14 is patterned into the shape of a transistor memory element by photolithography to form a memory transistor T. Configure. Note that this semiconductor layer 14 is connected to the source line S
L and also remain under the drain line DL over its entire length.

Next, as shown in FIG. 3(h), an upper gate insulating film (SiN film without charge storage function) 1 is applied over the entire surface of the substrate 11.
6 to a thickness of 5000.

Next, as shown in FIG. 3(i), in the upper gate insulating film 6, between the memory region of the lower gate insulating film 13 (a portion facing the lower gate electrode GIO) and the source electrode S, The portion between the memory region and the drain electrode is half-etched to a depth of 3000 Å by photolithography, and this upper gate insulating film 16 is formed between the portion above the memory region and the source and drain electrodes S, D
The film thickness is 50 mm from the position facing approximately the center to the outer part.
A thick film part with a thickness of 2,000 µm is formed, and a thin film part with a thickness of 2,000 µm is formed between the memory region and the source and drain electrodes S and D.

Next, as shown in FIG. 3(j), a metal film of 8Ω (aluminum) or the like is deposited on the upper gate insulating film 16 for 40 min.
This metal film is patterned by photolithography to form an upper gate electrode G20 and an upper gate line GL2°, and two selection transistors T20. T2° is constructed to complete the thin film transistor memory.

Note that in this manufacturing method, the lower gate electrode G□.

Although the lower gate electrode GIO and the planarizing insulating film 12 are formed by the steps shown in FIGS. 3(a) to 3(d), the lower gate electrode GIO and the planarizing insulating film 12 can also be formed by other methods. .

That is, FIGS. 4 to 9 show the lower gate electrode GIO.
This shows another method of forming the planarizing insulating film 12.

The method shown in FIG. 4 uses the lower gate electrode G. and lower gate line GL,. is formed by the method described above as shown in FIGS. 4(a) and 4(b), and then, as shown in FIG. 4(c), SiN or SOG (
A planarizing insulating film 12 made of spin-on glass or the like is used as the lower gate electrode G.

The flattening insulating film 12 is deposited or coated to a thickness sufficiently thicker than the film thickness (3000 layers) (thickness that makes the film surface almost flat), and the flattening insulating film 12 is dry etched until the upper surface of the lower gate electrode GIO is exposed. This is a method of etching back as shown in Figure (d) to form a planarized insulating film 12 that covers the entire lower gate line GL+o except for the upper surface of the lower gate electrode GIO.

In addition, in the method shown in FIG. 5, first, as shown in FIG. 5(a), a metal W!30 such as C', which will become the gate lines G L and o, and a lower gate electrode GIO are placed on the substrate 11. 500 people with Ta'S metal film 31.

After this, the underlying metal film 3 is deposited to a thickness of 3000 nm.
0 is patterned by photolithography to form gate lines GL, , and then the upper metal film 31 is patterned by photolithography as shown in FIG. 5(b) to form lower gate electrodes GIO. Then, a photoresist (etching mask used for patterning the metal film 31) 5 is formed on the lower gate electrode G1o.
As shown in FIG. 5(c), a flattening insulating film made of SiN or the like is applied to the entire surface of the substrate 11 while leaving the lower gate voltage i! The insulating film 12 deposited on the photoresist 50 is deposited on the same film jv (3ooo people) as G+o, and then the photoresist 50 is peeled off.
In this method, a flattened insulating film 12 as shown in FIG. 5(d) is formed by lift-off removal.

Furthermore, in the method shown in FIG. 6, first, as shown in FIG. 6(a), a gate line GL+ is formed on the substrate 11.

After depositing a metal film such as C to a thickness of 500 mm and patterning this metal film by photolithography to form a gate line GL+o, a flat film made of SiN or the like is deposited on the entire surface of the substrate 11. A planarized insulating film 12 is deposited on the 11th area (3000 layers) of the lower gate electrode GIO to be formed, and then a portion of this planarized insulating film 12 corresponding to the lower gate electrode forming region is deposited using a photolithography method. As shown in FIG. 6(b), the photoresist 51 on the planarized insulating film 12 is removed by etching, and as shown in FIG. A metal film 31 is deposited to a thickness of 3,000 nm, and a lower gate electrode GIO is formed using the metal film 31 deposited on the gate lines GL and o exposed in the etched portions of the planarizing insulating film 12. After that, by peeling off the photoresist 51, the metal film 31 deposited on the photoresist 51 is lifted off and removed to form the lower gate electrode GI as shown in FIG. 6(d).
This is a way to complete O.

Further, the method shown in FIG. 7 is a method in which the lower gate electrode G1o is formed of a two-layer metal film, and the lower gate electrode G1o is
The O and planarizing insulating film 12 are formed as follows. First, as shown in FIG. 7(a), a metal film 30 such as C", which will become the gate lines G L and O, is deposited to a thickness of 500 nm on the substrate 11, and a lower layer of the lower gate electrode GIO is deposited on the substrate 11. A first metal film, such as Ta, constituting the part is deposited to a thickness of 2,000 mm.Next, as shown in FIG.
The metal film 31a is patterned into the shape of the lower gate electrode cra by photolithography, and then the metal film 30 thereunder is tanned by photolithography to form gate lines GL, O. Next, Figure 7 (
As shown in C), a planarizing insulating film 12 made of SIN or the like is formed on the entire surface of the substrate 11.
It is deposited to the same thickness as the O layer (3000 layers). Next, a portion of the flattened insulating film 12 corresponding to the gate electrode forming region is formed by photolithography as shown in FIG. 7(d).
7(e), the photoresist 52 on the planarized insulating film 12 is removed by etching as shown in FIG. ) etc., the second metal film 31b is
The second metal film 31b deposited on the etched portion of the flattened insulating film 12 and the second metal film 31a thereunder form a lower gate electrode GIO with a total thickness of 3000 nm. do.

Thereafter, by peeling off the photoresist 52, the second metal film 31b deposited on the photoresist 52 is lifted off and removed, and the lower gate electrode GIO is removed as shown in FIG. 7(f). complete.

Further, in the method shown in FIG. 8, first, as shown in FIG. 8(a), a gate line G L + is formed on the substrate 11.

After depositing a metal film such as C' to a thickness of 500 mm and patterning this metal film by photolithography to form a gate line GL+o, a flattened film made of SiN or the like is deposited on the entire surface of the substrate 11. The insulating film 12 is deposited to the thickness of the lower gate electrode G (3,000 layers), and the portion of the planarized insulating film 12 corresponding to the lower gate electrode forming region is formed by photolithography as shown in FIG. 8(b). As shown, the etching is removed, and then a metal (
For example, in the case of electroless plating, N1, etc.) is deposited to a thickness of 3,000 yen to form the lower gate electrode GIO as shown in FIG. 8(C).

On the other hand, the method shown in FIG. 9 is a method in which the planarizing insulating film 12 is formed of a metal oxide, and the lower gate electrode GILI and the planarizing insulating film 12 are formed as follows. First, the 9th
As shown in Figure (a), on the substrate 11, a gate line G
A metal film 30 such as Cr that becomes L, , and a lower gate electrode G
500 people, 300
The metal films 30 and 31 are deposited to a thickness of 0.03 mm and patterned into the shape of gate lines G L and O by photolithography. Next, as shown in FIG. 9(b), a portion of the upper metal film 31 that will become the lower gate electrode GIO is masked with a photoresist 53, and in this state, the upper metal film 31 is anodized. The entire area of this metal film 31 other than the portion that will become the gate electrode Gln is made into a 1-Si planarization insulating film 12 made of metal oxide (Ta 20q when the metal film 31 is Ta), and then photoresist is applied. 53
is removed to complete the lower gate electrode G1o and the planarizing insulating film]2 as shown in FIG. 9(C).

Note that the lower gate electrode G is
1(+) and when forming the planarizing insulating film 12,
After this, a thin film transistor memory is manufactured through the steps shown in (e) to ('') in FIG.

FIG. 10 is an equivalent circuit diagram of the thin film transistor memory, and this thin film transistor memory has a structure in which memory transistors T, o and two selection transistors T2o, T2o are stacked in one thin film transistor. There is. Note that although FIG. 10 shows an equivalent circuit of one thin film transistor memory, this thin film transistor memory has a lower gate line Goo and an upper gate line G2 (+, source, drain line SL,
They are each formed at the intersection with DL.

Writing and erasing/reading of this thin film transistor memory is performed as follows.

In FIG. 10, (a) shows the state of voltage application during writing, (b) shows the state of voltage application during erasing, and (c) shows the state of voltage application during reading.

First, writing will be explained. During writing, as shown in FIG. 10(a), the source electrode S and the drain electrode are grounded (GND), and the selection transistor T
2o, an ON voltage V is applied to the gate electrode G20 of T2o. N is applied to the memory transistor T,.

A write voltage +V is applied to the gate electrode GIO.

When such a voltage is applied, the two selection transistors T 20+ T 2o are turned on, and the memory transistor TI (+ gate electrode G, and source and drain electrodes S
, and D, charges are trapped in the memory region of the lower gate insulating film 13 (the portion of the memory insulating film 13b facing the gate electrode G1o), and the memory transistor TIO is brought into the write state (OFF state). Become.

Furthermore, during erasing, as shown in FIG. 10(b), the source electrode S and the drain electrode are grounded (GND), and the gate electrode G20 of the selection transistor T2° is turned ON.
A voltage VON is applied, and an erase voltage -P, which is a potential opposite to the write voltage +V, is applied to the gate electrode GIG of the memory transistor T1o. When such a voltage is applied, the selection transistors T2o and T2o are turned on, and the gate electrode GIO, source, and drain electrode S of the memory transistor T1o are turned on.

A potential difference (Vp) between the write voltage +vP and the opposite potential between
occurs, the charges trapped in the memory region of the lower gate insulating film 13 are released, and the memory transistors T, O
becomes an erased state (ON state).

On the other hand, during reading, as shown in FIG. 10(C), the gate electrode G of the memory transistor T1o. The source electrode S is grounded (GND), and the ON voltage V is applied to the gate electrode G20 of the selection transistors T2o and T2o. N
is applied, and a read voltage V is applied to the drain electrode. When such a voltage is applied, the memory transistor T
If IO is in the erased state (ON state!!), current flows from the drain electrode to the source electrode S, and the memory transistor T
If 1o is in the write state (OFF state), the current does not flow, so read data is output depending on the presence or absence of current flowing from the source electrode S to the source line.

That is, the thin film transistor memory includes a lower gate electrode GIO and a lower gate insulating film 1 having a function of accumulating electricity.
3, a semiconductor layer 14, and source and drain electrodes S and D are stacked on top of the memory transistor T1o.
Two selection transistors T20. An upper gate insulating film 16 without a charge storage function and an upper gate electrode G20 are laminated, and the semiconductor layer 14 and the source and drain electrodes SD are shared with the memory transistor TIO. This is what makes up T20.

This thin film transistor memory includes a memory transistor Tlo and a selection thin film transistor T2n+
Since it is constructed by stacking the memory transistors T and T2o. and selection transistor T20+T2
It is possible to increase the degree of integration by reducing the element area of the transistor memory configured with the transistor memory. Further, in this thin film transistor memory, the semiconductor layer 14 and the source,
The drain electrodes S and D are connected to the memory transistor T. Since it is shared by the selection transistor T20+T2o,
It can be easily manufactured with a small number of components as described above.

Moreover, in this thin film transistor memory, the lower gate electrode G1° is formed protrudingly on the lower gate line G L formed on the substrate 11, facing a part of the semiconductor layer 14, and the lower gate insulating film 13 lower gate electrode G,. The upper gate insulating film 13 has an F part gate line G on the substrate 11.
formed on a planarizing insulating film 12 formed to a thickness that covers L, , and exposes the upper surface of the lower gate electrode G+o,
In addition, the upper gate electrode G20 is formed to face the entire semiconductor layer 13, and the thickness of the upper gate insulating film 16 is increased over the portion of the semiconductor layer 14 corresponding to the memory area, so that between the selection transistor T20 region of the layer 14 and the lower gate electrode GOO which is the gate electrode of the memory transistor TIO (between the lower gate line GL+o), and the memory transistor TIO region of the semiconductor layer 14 (the memory region of the lower gate insulating film 13). ) and the selection transistor T2. ．． T
2. It is possible to reliably insulate and separate the upper gate electrode G2o, which is the gate electrode of the upper gate electrode G2o. Therefore, according to this thin film transistor memory, the selection transistor T1o is connected to the gate electrode (
Lower gate [pole] G+. There is no malfunction due to the influence of pressure applied to the memory transistor T,
o does not malfunction due to the influence of the gate voltage applied to the gate electrode (upper gate electrode) G20 of the selection transistor T20+T2o, so the memory transistor T, which shares the semiconductor layer 14 and the source and drain electrodes S and D, . and selection transistor T2. ．． Although the memory transistor Tlo and the selection transistors T2o and T2o are stacked, it is possible to operate the memory transistor Tlo and the selection transistors T2o and T2o normally to perform stable writing, erasing, and reading.

In addition, in this thin film transistor memory, since the film J- in the outer portion of the upper gate insulating film 16 from the position facing approximately the center of the source and drain electrodes S and D is also thickened, there is a gap between the upper gate electrode G20 and the source and drain electrodes. Electrode S
, D is also sufficient.

Note that the thin film transistor memory of the above embodiment includes one memory transistor T. However, the present invention can also be applied to a thin film transistor memory having one selection transistor for one memory transistor.

11 to 13 show a second embodiment of the present invention. The thin film transistor memory of this embodiment has one selection transistor T2o for one memory transistor TIO, and FIGS. 11 and 12 are a cross-sectional view and a plan view of the thin film transistor memory, and FIG. 13 is a FIG. 2 is an equivalent circuit diagram of a thin 11+transistor memory.

The thin film transistor memory of this embodiment has a lower gate electrode GIO which is the gate electrode of the memory transistor T1o.
is formed protrudingly on the lower gate line GL formed on the substrate 11, facing a part of the semiconductor layer 14,
a lower gate electrode G of the lower gate insulating film 13; The lower gate insulating film 13 has a lower gate line GL on the substrate 11, and a portion facing the lower gate line GL is a memory area. and the lower gate electrode G,. 14 formed to a thickness that exposes the top surface of the
Formed on the planarization insulating film 12, and the selection transistor T
The upper gate electrode G20, which is the gate electrode of 2o, is formed to face the entire semiconductor layer 14, and the thickness of the upper gate insulating film 16 is set to Jv< in the soil of the portion corresponding to the memory area. memory transistor T
Io is the lower gate electrode GIO and the lower gate insulating film 1
'3, the semiconductor layer 14 and the source and drain electrodes S,
D, and the selection transistor T2o includes the semiconductor layer 14 and source and drain electrodes S, D,
The thin film portion of the upper gate insulating film 16 and the upper gate electrode G
20.

Note that the thin film transistor memory of this embodiment has only one selection transistor T2o, and the basic configuration is the same as that of the first embodiment. Omitted.

In addition, writing of the thin film transistor memory of this example,
Erasing and reading can be performed in the same manner as in the thin film transistor memory of the first embodiment.

In addition, in the example of the front 5 pins, the upper gate insulating film 16 is
Although the thick film portion and the thin film portion are formed by half-etching a single layer film, the upper gate insulating film 16 may have a two-layer film structure.

14 and 15 show a third embodiment of the present invention, and FIGS. 16 and 17 show a fourth embodiment of the present invention. The insulating film 16 has a two-layer film structure consisting of a lower layer film 16a and an upper layer film 16b.

First, the third embodiment will be described. As shown in FIG. .
b is formed on the entire surface of the substrate 11 covering the lower layer film 16a, and both the lower layer film 16a and the upper layer film 16b are insulating II! without charge storage function. (for example, a silicon nitride film). Further, the thickness of the lower layer 16a is 3000, and the thickness of the upper layer 16b is 2000.
The thickness of the thick film portion consisting of the lower layer film 16a and the upper layer film 16b is 5000 people. Note that the thin film transistor memory of this embodiment only has a two-layer structure for the upper gate insulating film 16, and other configurations are the same as those of the first embodiment, so duplicate explanations will be given the same reference numerals in the figures. and omitted.

The thin film transistor memory of this embodiment is shown in FIG. 3(a).
The lower gate electrode GIO and the planarization film 12 are formed in the steps of ~(d) or any of FIGS. 4 to 9, and then the third
The memory transistor T1 is formed by the steps shown in FIGS.
After forming the upper gate insulating film 16, the upper gate insulating film 16 is formed in the step shown in FIG. 15, and the upper gate electrode G20 is formed thereon. It is formed.

First, as shown in FIG. 15(a), the lower film 16a of the upper gate insulating film 16 is deposited to a thickness of 3000 nm over the entire surface of the substrate 11 forming the memory transistor T1o.

Next, as shown in FIG. 15(b), the upper layer film 16a
Of these, the portions of the lower gate insulating film 13 between the memory region and the source electrode S and between the memory region and the drain electrode are removed by photolithography.

Next, as shown in FIG. 15(c), the upper layer film 16b of the upper gate insulating film 16 is deposited on the entire surface of the substrate 11 to a thickness of 2000 nm to complete the upper gate insulating film 16.

That is, this upper gate insulating film 16 connects a portion of the lower gate insulating film 13 above the memory region and a portion outward from a position facing approximately the center of the source and drain electrodes S and D to a lower layer film 16a and an upper layer film 16b. A thick film part (film thickness: 5000 m) of a two-layer film structure consisting of That is.

Note that the upper gate electrode G20 formed on the upper gate insulating film 16 is formed by depositing a metal film such as aluminum to a thickness of 4,000 mm, as in the first embodiment, and depositing this metal film by photolithography. It is formed by patterning.

On the other hand, in the thin film transistor memory of the fourth embodiment, the first
As shown in FIG. 6, the lower layer film 16 of the upper gate insulating film 16
a is formed over the entire surface of the substrate 11, and an upper layer film 16b is formed on the memory region of the lower gate insulating film 13 (the portion facing the lower gate electrodes G, .) and on the source and drain electrodes S, D.
The lower layer film 16a and the upper layer film 16b are both insulating films without a charge storage function, and the lower layer film 16
The upper layer film 16a and the upper layer film 16b are formed of insulating materials having different etching rates. In addition, in this example,
The upper layer film 16a is a silicon nitride (SiN) film, and the upper layer film 16b is a silicon oxide (SiO2) film.

Furthermore, the thickness of the upper layer film 16a is 2000 layers, the thickness of the upper layer layer 16b is 3000 layers, and the film jma' of one film portion (consisting of the lower layer layer 16a and the upper layer layer 16b) is 5000 layers. ing. Note that the thin film transistor memory of this embodiment also has the same structure as the first embodiment except that the upper gate insulating film 6 has a two-layer structure. It will be omitted.

The thin film transistor memory of this embodiment is shown in FIG. 3(a).
~(d) or any of FIGS. 4 through 9], the lower gate electrode GIO and the planarization film 12 are formed, and then the memory transistor T is formed through the steps shown in FIGS. 3(e) through (g).
After configuring the IO, the upper gate insulating film 16 is formed in the step shown in FIG. 17, and the upper gate electrode G20 is formed thereon. It is formed.

First, as shown in FIG. 17(a), a memory transistor T. A lower layer film (silicon nitride film) 16a of the upper gate insulating film 16 is formed over the entire surface of the substrate 11 comprising
An upper layer film (silicon oxide film) 16b is deposited over the entire surface of the lower layer film 16a.
Deposit to a thickness of 3000 people.

Next, as shown in FIG. 17(b), the upper layer film 16b
Of these, portions of the lower gate insulating film 13 between the memory region and the source electrode S and between the memory region and the drain electrode are removed by photolithography to complete the upper gate insulating film 16. In this case, since the lower layer film 16a has a different etching rate from the upper layer film 16b, the lower layer film 16a is etched when the upper layer film 16b is etched.
will not be etched.

That is, this upper gate insulating film 16 connects a portion of the lower gate insulating film 13 above the memory region and a portion outward from a position facing approximately the center of the source and drain electrodes S and D to a lower layer film 16a and an upper layer film 16b. A thick film part (film thickness: 5,000 layers) of a two-layer film structure consisting of the above is used, and a thin film part (film thickness: 2,000 layers) consisting of only the lower layer film 16a is defined between the memory region and the source and drain electrodes S and D. That is.

In this embodiment as well, the upper gate electrode G20 formed on the upper gate insulating film 16 is formed by depositing a metal film such as aluminum to a thickness of 40 μm, as in the first embodiment. This metal film is formed by patterning using a photolithography method.

The thin film transistor memories of the third and fourth embodiments also include memory transistors T. and a selection thin film transistor T 20+T 2o are stacked, so the memory transistor T. The element area of the transistor memory composed of the memory transistor TIO and the selection transistor T2o can be reduced and the degree of integration can be increased. Since it is shared with T20°T2O, it can be manufactured into containers with a small number of steps. Also, in the thin film transistor memories of these embodiments, the memory transistors T. The lower gate electrode GIO is the gate electrode of
, the lower gate line GL formed on the substrate 11,
is formed protrudingly on the semiconductor layer 14 to face a part of the semiconductor layer 14, and the part of the lower gate insulating film 13 facing the lower gate electrode COO is used as a memory region, and the lower gate insulating film 11%1
3 is formed on the planarizing insulating film 12 formed on the substrate 11 to a thickness that covers the lower gate lines GL and o and exposes the upper surface of the lower gate electrode GIO, and is formed on the gate of the selection transistor "20+ T2O". Since the thickness of the upper gate insulating film 16 between the upper gate electrode G20, which is an electrode, and the semiconductor layer 14 is increased above the portion of the semiconductor layer 14 corresponding to the memory area, the semiconductor layer 14
It is possible to prevent the gate voltage from being applied from the upper gate electrode G20 to the portion corresponding to the memory region of the semiconductor layer 14 and causing the memory thin film transistor to malfunction.
and a memory transistor TIO and selection transistors T2o and T2 that share the source and drain electrodes S and D.
Although it is constructed by stacking the memory transistor TIO and the selection transistor T2 (1+T2
0 can be operated normally to perform stable writing, erasing, and reading.

Note that the thin film transistor memories of the third and fourth embodiments have two transistors for one memory transistor T1o.
Of course, these embodiments can also be applied to a thin film transistor memory having one selection transistor for one memory transistor.

〔Effect of the invention〕

In the thin film transistor memory of the present invention, an upper gate insulating film without a charge storage function is placed on top of a thin film transistor for memory, which is constructed by laminating a lower gate electrode, a lower gate insulating film with a charge storage function, a semiconductor layer, and a source and drain electrode. The semiconductor layer and the source are stacked by stacking a film and an upper gate electrode.

This is a selection thin film transistor whose drain electrode is shared with a memory thin film transistor. Since this thin film transistor memory is constructed by stacking a memory thin film transistor and a selection thin film transistor, it is possible to increase the degree of integration by reducing the element area of the transistor memory composed of a memory thin film transistor and a selection thin film transistor. Furthermore, since the semiconductor layer and the source and drain electrodes are shared by the memory thin film transistor and the selection thin film transistor, it can be easily manufactured with a small number of steps. In this thin film transistor memory, the lower gate electrode is formed to protrude above the lower gate line formed on the substrate so as to face a part of the semiconductor layer, and the part of the lower gate insulating film facing the lower gate electrode is formed to protrude above the lower gate line formed on the substrate. The lower gate insulating film is formed on the multilayer insulating film formed on the substrate to a thickness that covers the lower gate line and exposes the upper surface of the lower gate electrode, and the upper gate electrode is formed on the semiconductor layer. The upper gate insulating film is formed so as to face each other as a whole, and the thickness of the upper gate insulating film is made thicker on the portion of the semiconductor layer corresponding to the memory region, so that the selection thin film transistor region of the semiconductor layer and the gate of the memory thin film transistor are formed. between the lower gate electrode, which is an electrode (between the lower gate line), and between the memory thin film transistor region of the semiconductor layer (the portion corresponding to the memory region of the lower gate insulating film) and the upper gate, which is the gate electrode of the selection thin film transistor. It is possible to reliably insulate and separate the electrodes from each other. Therefore, according to this thin film transistor memory, the selection thin film transistor does not malfunction due to the influence of the gate voltage applied to the gate electrode (lower gate electrode) of the memory thin film transistor, and the memory thin film transistor does not function as the selection thin film transistor. Because it does not malfunction due to the influence of the gate voltage applied to the gate electrode (upper gate electrode), it is constructed by stacking a memory thin film transistor and a selection thin film transistor that share the semiconductor layer and source and drain electrodes. However, the memory thin film transistor and selection thin film transistor each operate normally for stable writing and erasing.

Reading can be performed.

[Brief explanation of the drawing]

1 to 10 show the first embodiment of the present invention, so FIGS. 1 and 2 are a cross-sectional view and a plan view of a thin film transistor memory, and FIG. 3 is a process showing the thin film forming method. figure,
FIG. 10 is an equivalent circuit diagram of a thin film transistor memory. 11 to 13 show a second embodiment of the present invention. FIGS. 11 and 12 are a cross-sectional view and a plan view of a thin film transistor memory, and FIG. 13 is an equivalent circuit diagram of the thin film transistor memory. be. 14 and 15 are cross-sectional views of a thin film transistor memory showing a third embodiment of the present invention and a process diagram for forming the upper gate insulating film thereof, and FIGS. 16 and 17 are diagrams showing a fourth embodiment of the present invention. FIG. 2 is a cross-sectional view of a thin film transistor memory and a process diagram for forming an upper gate insulating film thereof. FIG. 18 is an equivalent circuit diagram of a conventional thin film transistor memory. 1]...Substrate, TIO...thin film transistor for memory, Too/thin film transistor for selection, GL,. ...
Lower Getlein, G.・・Lower gate electrode, 〕2・・
・Heiwaka insulation film, 13...lower gate insulation film, 14・
... Semiconductor layer, 15... Ohmic contact layer, S
... Source electrode, D... Drain electrode, 16... Upper gate insulating film, G2o... Upper gate electrode.

Claims (1)

[Claims] A lower gate electrode formed on an insulating substrate, a lower gate insulating film having a charge storage function formed on the substrate covering the lower gate electrode, and a semiconductor formed on the lower gate insulating film. a source and drain electrode formed on both sides of the semiconductor layer, an upper gate insulating film without a charge storage function formed on the semiconductor layer and the source and drain electrodes, and the upper gate insulator. and an upper gate electrode formed on the film, the lower gate electrode, the lower gate insulating film, the semiconductor layer, and the source and drain electrodes constitute a memory thin film transistor, and the semiconductor layer and the source and drain electrodes and the upper The gate insulating film and the upper gate electrode constitute a selection thin film transistor, and the lower gate electrode is formed to protrude above the lower gate line formed on the substrate so as to face a part of the semiconductor layer. A portion of the lower gate insulating film facing the lower gate electrode is used as a memory region, and the lower gate insulating film is formed on the substrate to a thickness that covers the lower gate line and exposes an upper surface of the lower gate electrode. The upper gate electrode is formed on a planarized insulating film, and is formed to face the entire semiconductor layer, and the thickness of the upper gate insulating film is set at a portion of the semiconductor layer corresponding to the memory region. A thin film transistor memory characterized by being thicker on the top.