JPH03293774A - Thin-film transistor memory - Google Patents

Abstract

PURPOSE:To reduce an element area and to manufacture this memory by the small number of processes by a method wherein an upper-part gate insulating film and an upper-part gate electrode are laminated and a semiconductor layer, a source electrode and a drain electrode are used in common together with a thin-film transistor for memory. CONSTITUTION:Two thin-film transistors for selection use (selection transistors) which use a semiconductor layer 15, a source electrode S and a drain electrode D in common together with a memory transistor T10 are formed on the memory transistor T10. Since the thin-film transistor T10 for memory and the thin-film transistor T20 for selection are constituted so as to be laminated in this manner, the element area of a transistor memory can be reduced and its integration density can be increased; the semiconductor layer 15, the source electrode S and the drain electrode D are used in common together with the thin-film transis tor T20 for selection. As a result, the transistor memory can easily be manufac tured by the small number of processes.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to thin film transistor memories.

[Conventional technology]

Recently, E2 F that can be written, erased and read electrically
2. Description of the Related Art As a memory such as a ROM, a thin film transistor memory is considered in which a memory transistor and a selection transistor are formed of thin film transistors.

Conventionally, this thin film transistor memory is formed by forming a thin film transistor for memory (hereinafter referred to as a memory transistor) and a thin film transistor for selection (hereinafter referred to as a selection transistor) adjacent to each other on an insulating substrate made of glass or the like. A transistor memory is known in which a transistor and a selection transistor are connected in series through a connection wiring that connects the source electrode of one transistor and the drain electrode of the other transistor. Note that the memory transistor and the selection transistor are each configured by laminating a gate electrode, a gate insulating film, an i-type semiconductor layer, and a source and drain electrode. The gate insulating film of the selection transistor is formed of an insulating film that does not have a charge storage function.

FIG. 13 is an equivalent circuit diagram of the conventional thin film transistor memory. Here, an equivalent circuit of a thin film transistor memory provided with two selection transistors for one memory transistor is shown.

In FIG. 13, T1 is a memory transistor, T2 is two selection transistors arranged on both sides of the memory transistor T1, and the source electrode S1 of the memory transistor T is connected to the drain electrode D2 of one selection transistor T2. The drain electrode D1 of the memory transistor T1 is the source electrode S2 of the other selection transistor T2.
It is connected to the. The source electrode S2 of the one selection transistor T2 is the source electrode S of a transistor memory. The drain electrode D2 of the other selection transistor T2 is the drain electrode of the transistor memory. The source electrode So is connected to a source line (not shown), and the drain electrode So is connected to a source line (not shown). is connected to a drain line (not shown). Further, the gate electrode G1 of the memory transistor T1 is connected to a first gate line (not shown), and the gate electrodes G2 of the two selection transistors T2 are commonly connected to a second gate line (not shown). Note that a large number of the first and second gate lines are wired in parallel, and a large number of source lines and drain lines are wired orthogonally to the gate lines,
The thin film transistor memory constituted by the memory transistor T1 and the selection transistor T2 includes the first . Second
They are formed at the intersections of the gate line and the source and drain lines, respectively.

Writing and erasing of this thin film transistor memory.

Reading is performed as follows.

In FIG. 13, (a) shows the state of voltage application during writing, (b) shows the state of voltage application during erasing, and (c) shows the state of voltage application during reading.

First, writing will be explained. During writing, as shown in FIG. 13(a), the source electrode S is opened. and drain electrode. is grounded (GND), and an ON voltage V is applied to the gate electrode G2 of the selection transistor T2. N is applied, and the write voltage + is applied to the gate electrode G1 of the memory transistor T1.
Apply VP.

When such a voltage is applied, the selection transistor T2 turns on, and a write voltage V is applied between the gate electrode G1 and the source and drain electrodes S, D, of the memory transistor T1.
P is applied, and the memory transistor T is in the write state (
OFF state).

Further, during erasing, as shown in FIG. 13(b), the source electrode S. and drain electrode.゛ is grounded (GND), and O is connected to the gate electrode G2 of the selection transistor T2.
N voltage V. N is applied to the gate electrode G of the memory transistor T1, and an erase voltage -■, which is a potential opposite to the write voltage +■P, is applied to the gate electrode G of the memory transistor T1. When such a voltage is applied, the selection transistor T2 is turned on, and a potential difference (-VP) opposite to the write voltage +vP is generated between the gate electrode G of the memory transistor T and the source and drain electrodes St and D+. As a result, the memory transistor T1 enters an erased state (ON state).

On the other hand, during reading, as shown in FIG. 13(c), the gate electrode G1 and the source electrode S of the memory transistor T1.

is grounded (GND), and the selection transistor T2
ON voltage V is applied to the gate electrode G2. Apply N and connect the drain electrode. A read voltage VD is applied to. When such a voltage is applied, the memory transistor T is placed in the erased state (O
If it is in N state), it is the drain electrode. from the source electrode So
A current flows through the memory transistor T1, and the memory transistor T1 enters the write state (
OFF state), the current does not flow, so the source electrode S. Read data is output depending on the presence or absence of current flowing through the source line.

Note that although a thin film transistor memory including two selection transistors T2 for one memory transistor T1 has been described here, some thin film transistor memories include one selection transistor for one memory transistor. .

[Problem to be solved by the invention]

However, the conventional thin film transistor memory
Since a thin film transistor for memory and a thin film transistor for selection are formed adjacent to each other on a substrate, and the memory transistor and selection transistor are connected in series by connection wiring, the element surface a ( Therefore, it is difficult to increase the degree of integration of a memory matrix formed by arranging transistor memories vertically and horizontally.

Moreover, in conventional thin film transistor memories, the gate insulating film of the memory thin film transistor is an insulating film with a charge storage function, and the gate insulating film of the selection thin film transistor is an insulating film without a charge storage function. There is also a problem in that the thin film transistor for selection and the thin film transistor for selection must be manufactured in separate processes, and therefore a large number of processes are required to manufacture the thin film transistor memory.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to reduce the element area of a transistor memory composed of a memory thin film transistor and a selection thin film transistor, thereby increasing the degree of integration. It is an object of the present invention to provide a thin film transistor memory that can be easily manufactured with a small number of steps.

[Means to solve the problem]

The thin film transistor memory of the present invention includes a lower gate electrode formed on an insulating substrate, a lower gate insulating film having a charge storage function and formed on the substrate covering the lower gate electrode, and the lower gate insulating film. a semiconductor layer formed thereon, source and drain electrodes formed on both sides of this semiconductor layer, and an upper gate insulator without a charge storage function formed on the semiconductor layer and the source and drain electrodes. an upper gate electrode formed on the upper gate insulating film, the lower gate electrode, the lower gate insulating film, a semiconductor layer, and a source.

The drain electrode constitutes a memory thin film transistor,
The semiconductor layer, the source and drain electrodes, the upper gate insulating film, and the upper gate electrode constitute a selective thin film transistor, and a protruding film is formed on the substrate to face a part of the semiconductor layer, The protruding portion of the lower gate electrode formed by overcoming the protruding film is used as the lower gate electrode, the portion of the lower gate insulating film facing the lower gate electrode is used as a memory region, and the lower gate insulating film is formed on a planarizing insulating film formed on the substrate to a thickness that covers the lower gate line and exposes the upper surface of the lower gate electrode, and the upper gate electrode faces the entire semiconductor layer. At the same time, the thickness of the upper gate insulating film is
The semiconductor layer is made thicker on a portion corresponding to the memory area.

[Effect]

That is, the thin film transistor memory of the present invention has an upper part without a charge storage function on top of a memory thin film transistor configured by laminating a lower gate electrode, a lower gate insulating film with a charge storage function, a semiconductor layer, and source and drain electrodes. A selection thin film transistor is formed by laminating a gate insulating film and an upper gate electrode to share the semiconductor layer and the source and drain electrodes with a memory thin film transistor. Since the semiconductor layer and the source and drain layers are stacked, the element area of the transistor memory consisting of the memory thin film transistor and the selection thin film transistor can be reduced and the degree of integration can be increased. Since the electrode is shared by the memory thin film transistor and the selection thin film transistor, it can be easily manufactured with a small number of steps.

In this thin film transistor memory, a protruding film is formed on the substrate so as to face a part of the semiconductor layer, and the protruding film crossing portion of the lower gate line formed on the substrate by crossing over the protruding film is connected to the lower gate line. As an electrode, a portion of the lower gate insulating film facing the lower gate electrode is used as a memory region, and a planarized insulating film is formed on the substrate to a thickness that covers the lower gate line and exposes the upper surface of the lower gate electrode. A lower gate insulating film is formed on this planarized insulating film, and an upper gate electrode is formed to face the entire semiconductor layer, and the thickness of the upper gate insulating film is adjusted to correspond to the memory area of the semiconductor layer. Because it is thicker above the part where the semiconductor layer is used, it is thicker between the selection thin film transistor region of the semiconductor layer and the lower gate electrode which is the gate electrode of the memory thin film transistor (between the lower gate line), and the memory thin film transistor region of the semiconductor layer. (
The portion of the lower gate insulating film corresponding to the memory region) and the upper gate electrode, which is the gate electrode of the selection thin film transistor, can be reliably isolated from each other.

Therefore, according to this thin film transistor memory, the selection thin film transistor does not malfunction due to the influence of the gate voltage applied to the gate electrode (lower gate electrode) of the memory thin film transistor, and the memory thin film transistor Because it does not malfunction due to the influence of the gate voltage applied to the upper gate electrode (upper gate electrode), the memory The selective thin film transistor and the selective thin film transistor can each operate normally to perform stable writing, erasing, and reading.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

1 to 5 show a first embodiment of the present invention, and FIGS. 1 and 2 are a sectional view and a plan view of a thin film transistor memory.

To explain the structure of this thin film transistor memory, numeral 11 in the figure is an insulating substrate made of glass or the like;
1, a lower gate electrode GIO is formed. This lower gate electrode GIO is a lower gate line GL formed on the substrate 11. By a part of the lower gate line G
It is formed to protrude above L and o. That is, the lower gate lines G.sub.L, . . . are formed by crossing over a thick protrusion film 12 formed on the substrate 11 in correspondence with the formation portion of the lower gate electrode G1. . is the lower gate line GL. It is formed by a protruding membrane crossing part. In addition, the protrusion W! ! 12 is formed of an insulating film such as SiN (silicon nitride) or a metal film such as Ta (tantalum) to a thickness of 3000 nm, and the lower gate electrodes G and o are connected to the lower gate line on the substrate 11. It protrudes from GL+o by the thickness of the protruding membrane 12 (3000 people).

Further, on the substrate 11, the lower gate electrode W c
+. A planarizing insulating film 13 is formed that covers the entire lower gate line GL+o except for the upper surface of the gate line GL+o. This planarizing insulating film 13 is made of an insulating film without a charge storage function, and the upper surface of this planarizing insulating film 13 is connected to the F section gate electrode GI.
It is formed to have a film thickness (3000 mm) that is almost flush with the upper surface of O.

Then, on this V carrier insulating film 13, a lower gate insulating film 14 covering the lower gate electrode G+o is formed on the substrate 1.
It is formed over almost the entire surface of 1. This lower gate insulating film 14 has a charge storage function in the entire upper layer part, and this lower gate insulating film 14 is made of SiN on a lower layer insulating film 14a made of SiN that does not have a charge storage function.
It is a two-layer film in which memory insulation films 14b made of SiN with a high composition ratio of silicon (silicon) and a charge storage function are laminated. The thickness of the lower insulating film 14a is 1900, and the thickness of the memory insulating film 14b is 100.
It's a person. On the lower gate insulating film 14 (on the memory insulating film 14b), an i-type semiconductor layer 15 made of amorphous silicon or polysilicon is formed in a pattern corresponding to the element shape of the transistor memory. On both sides of the semiconductor layer 15, an n-type semiconductor (n
A source electrode S and a drain electrode are formed via an ohmic contact layer 16 made of amorphous silicon or polysilicon doped with type impurities.

The source electrode S and the drain electrode are formed on the lower gate line GLt on the lower gate insulating film 14, respectively.
The source line SL and the drain line DL are connected to the source line SL and the drain line DL, which are wired perpendicularly to the source line SL and the drain line DL.

Further, the semiconductor layer 15 and the source and drain electrodes S
, D, an upper gate insulating film 1 made of silicon nitride without a charge storage function is formed over almost the entire surface of the substrate 11.
7 is formed. Above this upper gate insulating film 17, an upper gate line GL20 is connected to a lower gate line G.
The upper gate line GL2o is wired in parallel with the semiconductor layer 15, and a portion of the upper gate line GL2o above the semiconductor layer 15 is used as an upper gate electrode G2o.

The lower gate electrode GIO, the lower gate insulating film 14 having a charge storage function, the semiconductor layer 15, and the source and drain electrodes S and D are an inverted staggered memory thin film transistor (hereinafter referred to as a memory transistor).
It constitutes Too.

Further, the lower gate electrode GIG, which is the gate electrode of the memory transistor T1o, is arranged so as to face the central part of the semiconductor layer 15 in the channel length direction (the central part between the source and drain electrodes S and D). It is formed to have a width of approximately 173 mm in the longitudinal direction, so that only the central portion of the lower gate insulating film 14 facing the lower gate electrode G1o serves as a memory region.

On the other hand, the upper gate electrode G20 is an electrode facing the entire semiconductor layer 15.
The upper gate insulating film 17 between 20 and the semiconductor layer 15 is
Memory area of the lower gate insulating film 14 (lower gate electrode G
The film thickness is increased in the upper part of the IO (opposing part) and in the outer part from the position facing approximately the center of the source and drain electrodes S and D, and the film thickness is increased between the memory area and the source electrode S and between the memory area and the source electrode S and the drain electrode S. The insulating film is made thinner in the portion between the drain electrode and the drain electrode. Note that the thick portion of the upper gate insulating film 17 is connected to the source and drain lines S.
It is formed over the entire length of the insulating film in the length direction of L and DL. Further, the film thickness of the upper gate insulating film 17 is such that a gate voltage is applied from the upper gate electrode G20 to the memory transistor TIO region of the semiconductor layer 15 (a portion corresponding to the memory region of the lower gate insulating film 14). (in this example, 5000 people),
The thickness of the thin film portion of the upper gate insulating film 17 is equal to that of the semiconductor layer 1.
The thickness is such that a sufficient gate voltage can be applied to the gate electrode G20 from the upper gate electrode G20 (2000 in this embodiment).

The semiconductor layer 15 and source and drain electrodes S are provided on the memory transistor TIo.

D is a memory transistor T, Two selection thin film transistors (hereinafter referred to as selection transistors) shared with
T20. T20 is formed. These two selection transistors T 20 + T 2o include the semiconductor layer 15, source and drain electrodes S and D, an upper gate insulating film 17 without a charge storage function, and an upper gate electrode G.
One selection transistor T2° is a coplanar thin film transistor composed of a semiconductor layer 15 and source and drain electrodes S.

D, one thin film portion of the upper gate insulating film 17, and an upper gate electrode G20, and the other selection transistor T20 is composed of the semiconductor layer 15, the source and drain electrodes S, D, and the upper gate insulating film 17. , and an upper gate electrode G2°.

These two selection transistors T2o, T2o are connected in common on the gate side by making their gate electrode (upper gate electrode) G20 an electrode facing the entire semiconductor layer 15, and the reselection transistors T2o, T2o are connected in common on the gate side.
2o is connected in series with the memory transistor T1o by sharing its source and drain electrodes S and D with the memory transistor T1o.

Further, the two thin film portions of the upper gate insulating film 17 constituting the selection transistors T2° and T2o have a width in the channel length direction of the film thickness portion corresponding to the memory area of the lower gate insulating film 14 as the lower gate insulating film 14. The lower gate electrode G is made smaller than the width in the channel length direction of Gta. It is wrapped on both sides. This is done by the memory transistor T. and reselection transistor T2. ．． This is to ensure electrical connection with T2o, and if the thin film portions of the upper gate insulating film 17 constituting the selection transistors T2o and T2o are wrapped around the lower gate electrode GIG, the memory transistor T1o region of the semiconductor layer 15 can be A gate electrode (lower gate electrode) G+ of the memory transistor T1o is provided at the boundary between the region and the selection transistor T2° region (both sides of the portion of the lower gate insulating film 14 corresponding to the memory region).

Since the gate voltage can be applied from the gate electrode (upper gate electrode) G20 of the selection transistors T2o and T2o, when both the memory transistor T1° and the selection transistor T20+T2o are turned on, the semiconductor A current flows from the drain electrode to the source electrode S through the layer 15. In this embodiment, the width of the thick portion of the upper gate insulating film 17 above the memory region is the width of the lower gate electrode G. However, the width of this film thickness portion may be any width as long as it is less than the width of the lower gate electrode GIo.In short, the thin film portion of the upper gate insulating film 17 It is sufficient that it faces at least the side edge of the electrode GIO.

FIG. 3 shows a method for manufacturing the thin film transistor memory, and this thin film transistor memory is manufactured through the following steps.

First, as shown in FIG. 3(a), an insulating film such as SIN or a metal film such as Ta, which will become the protruding film 12 under the lower gate electrode GIO, is deposited to a thickness of 3000 nm on the substrate 11. The lower gate electrode G is formed by patterning the deposited film using photolithography. A protruding film 12 corresponding to the shape of is formed.

Next, as shown in FIG. 3(b), a lower gate line GL is formed on the substrate 11. Then, a metal film such as Cr (chromium), which will become the lower gate electrode G1°, is deposited to a thickness of 500 mm, and this metal film is patterned by photolithography to form the lower gate lines G L and o. A portion of the lower gate line G L , . on the protruding film 12 is defined as a lower gate electrode G1°.

Next, as shown in FIG. 3(c), a planarizing insulating film 13 made of SiN or the like is deposited on the entire surface of the substrate 11 to a thickness equal to the protrusion height (3000 layers) of the lower gate electrode GIO. Then, as shown in FIG. 3(d), the portion of the planarized insulating film 13 that covers the lower gate electrode G1° is removed by photolithography to form the lower gate electrode G1.
,. Planarized insulation l! covering the entire lower gate line GL, . Complete 13.

Next, as shown in FIG. 3(e), the planarized insulating film 1
3 and the lower gate electrode GIO, a lower insulating film (SiN film) 14a without a charge storage function, and a memory insulating film (SiN film with a high composition ratio of Si) having a charge storage function.
membrane) 14b, 1900 people.

A two-layer lower gate insulating film 14 consisting of a lower insulating film 14a and a memory insulating film 14b is formed by sequentially depositing the film to a thickness of 100 nm, and on top of this, l-type amorphous silicon or n-type amorphous silicon is deposited. Semiconductor layer 1 made of polysilicon
5, and an n-type semiconductor (n-type amorphous silicon or n
Ohmic contact layer 16 made of polysilicon)
1000 people.

The metal film 30 for source and drain electrodes made of Cr or the like is deposited successively to a thickness of 250 mm.
Deposit to a thickness of 500 people.

Next, the metal film 30 for source and drain electrodes is patterned by photolithography, as shown in FIG. 3(f).
As shown in FIG.
source and drain electrodes S and D and source and drain lines SL.

DL is formed, and then the ohmic contact layer 16 is connected to the source, drain electrodes S, D, and the source.

Patterning is performed in the shape of drain lines SL and DL.

Next, as shown in FIG. 3(g), the semiconductor layer 15 is patterned into the shape of a transistor memory element by photolithography to form a memory transistor TIO. Note that this semiconductor layer 15 is connected to the source line S
L and also remain under the drain line DL over its entire length.

Next, as shown in FIG. 3(h), an upper gate insulating film (1! SiN film without load storage function) is applied over the entire surface of the substrate 11.
17, the thickness of the thick film part formed on this (5000 people)
to be deposited.

Next, as shown in FIG. 3(i), a portion of the upper gate insulating film 17 between the memory region of the lower gate insulating film 14 (a portion facing the lower gate electrode GIG) and the source electrode S and the memory The upper gate insulating film 17 is half-etched to a depth of 3,000 mm using photolithography to form the upper gate insulating film 17 between the memory region and the source and drain electrodes S and D. The film thickness is 5000 from the position facing almost the center to the outer part.
It is processed into a shape in which the thick film part is made 2,000 thick, and the part between the memory area and the source and drain electrodes S and D is made into a thin film part with a thickness of 2000 people.

Next, as shown in FIG. 3(j), a metal film such as AI (aluminum) is formed on the upper gate insulating film 17.
This metal film is patterned by photolithography to form the upper gate electrode G2o.
and upper gate lie>'G L 20 to form 2
one selection transistor T2. ．． T2° is constructed to complete the thin film transistor memory.

In addition, in this manufacturing method, the planarization insulating film 13 is formed as shown in FIG.
Although it is formed by the steps shown in C) and (d), this planarizing insulating film 13 can also be formed by other methods.

That is, FIG. 4 shows another method of forming the planarizing insulating film 13.

In this method, the thrust film 12 and the lower gate line G L r
o and the lower gate electrode GIO by the method described above.
After the formation as shown in FIG. 4(a), a planarizing insulating film 13 made of SiN or SOG (spin-on-glass) is formed on the entire surface of the substrate 11 for the lower gate as shown in FIG. 4(b). Electrode G. The planarized insulating pIIe13 is deposited or coated to a thickness sufficiently thicker than the protrusion height (3000) (thickness that makes the film surface almost flat), and the planarized insulating pIIe13 is dry-etched until the upper surface of the lower gate electrode GIO is exposed. As shown in Figure (C), the lower gate line G is etched back except for the upper surface of the lower gate electrode Go.
This method completes the planarization insulating film 13 that covers the entire L.

Note that even when the planarizing insulating film 13 is formed by the method shown in FIG. 4, the thin film transistor memory is thereafter manufactured by the steps shown in FIGS. 3(e) to (j).

FIG. 5 is an equivalent circuit diagram of the thin film transistor memory, which has a structure in which a memory transistor TIO and two selection transistors T2o and T2o are stacked in one thin film transistor. Note that although FIG. 5 shows an equivalent circuit of one thin film transistor memory, this thin film transistor memory has a lower gate line G, They are formed at the intersections of the upper gate line G20 and the source and drain lines SL and DL, respectively.

Writing and erasing of this thin film transistor memory.

Reading is performed as follows.

In FIG. 5, (a) is when writing, (b) is when erasing,
(c) shows the voltage application state during reading.

To explain about writing, when writing, Figure 5 (
As shown in a), the source electrode S and the drain electrode are grounded (GND), and the selection transistor T2
o, ON voltage V is applied to the gate electrode G20 of T2o. N is applied, and a write voltage +vP is applied to the gate electrode G1o of the memory transistor TIO.

When such a voltage is applied, the two selection transistors T 20+ T 2o are turned on, and the gate electrode CtO, source, and drain electrode S of the memory transistor T1o are connected to each other.
.

A write voltage +vP is applied between TIO and D, charges are trapped in the memory region of the lower gate insulating film 14 (the portion of the memory insulating film 14b facing the gate electrode GIO), and the memory transistor TIO enters the write state (OFF state). .

Further, during erasing, as shown in FIG. 5(b), the source electrode S and the drain electrode are grounded (GND), and the ON voltage V is applied to the gate electrode G20 of the selection transistor T20. N is applied, and a write voltage +V is applied to the gate electrode GIG of the memory transistor TIO.

An erase voltage -vP having an opposite potential is applied. When such a voltage is applied, the selection transistor T20+T2o is turned on, and the gate electrode GIO of the memory transistor T1o is turned on.
A write voltage +V is applied between the source and drain electrodes S and D.
A potential difference (Vp) opposite to P is generated, the charges trapped in the memory region of the lower gate insulating film 14 are released, and the memory transistor T1o enters an erased state (ON state).

On the other hand, at the time of reading, as shown in FIG. 5(c), the gate electrode G1o of the memory transistor T1o and the source electrode S
is grounded (GND), and the selection transistor T2
An ON voltage VON is applied to the gate electrode G2° of T2o, and a read voltage VD is applied to the drain electrode. When such a voltage is applied, a current flows from the drain electrode to the source electrode S if the memory transistor TIO is in an erased state (ON state), and the current flows if the memory transistor TIO is in a written state (OFF state). Therefore, read data is output depending on the presence or absence of current flowing from the source electrode S to the source line.

That is, the thin film transistor memory includes a lower gate electrode GIG and a lower gate insulating film 14 having a charge storage function.
and the semiconductor layer 15 and the source and drain electrodes S, D.
An upper gate insulating film 17 having no charge storage function and an upper gate electrode G2o are stacked on the memory transistor T1o configured by stacking the semiconductor layer 15 and the source and drain electrodes S and D. T+u
This configuration includes two selection transistors T2o and T2o that are shared with the same.

This thin film transistor memory has a memory transistor T
,. The memory transistor T1
o and selection transistor T20. It is possible to increase the degree of integration by reducing the element area of the transistor memory configured with T2°. Further, in this thin film transistor memory, the semiconductor layer 15 and the source and drain electrodes S, D
The memory transistor TIO and the selection transistor T20
．． Since it is shared with T20, it can be easily manufactured with a small number of steps as described above.

In this thin film transistor memory, a protruding film 12 is formed on the substrate 11 so as to face a part of the semiconductor layer 15.
A lower gate electrode G, of the lower gate insulating film 14 is formed by forming a lower gate electrode G1o on the substrate 11, with the protruding film crossing portion of the lower gate line G L , formed on the substrate 11 over the protruding film 12 as the lower gate electrode G1o. A portion facing the substrate 11 is used as a memory area, and a lower gate line G is formed on the substrate 11.
A planarizing insulating film 13 is formed to a thickness that covers L+o and exposes the upper surface of the lower gate electrode GIO, a lower gate insulating film 14 is formed on this planarizing insulating film 13, and the upper gate electrode G20 is formed to face the entire semiconductor layer 15, and the thickness of the upper gate insulating film 17 is increased over the portion of the semiconductor layer 15 corresponding to the memory area, so that the selection transistor of the semiconductor layer 15 Between the T2o region and the lower gate electrode which is the gate electrode of the memory transistor T1o (lower gate line G
Between the memory transistor T1o region of the semiconductor layer 15 (the part corresponding to the memory region of the lower gate insulating film 14) and the selection transistor T2°, T2
It is possible to reliably insulate and separate the upper gate electrode G2°, which is the gate electrode of the upper gate electrode G2°.

Therefore, according to this thin film transistor memory, the selection transistor T1o will not malfunction due to the influence of the gate voltage applied to the gate electrode (lower gate electrode) Goo of the memory transistor TIO, and the memory transistor TIO will not malfunction due to the influence of the gate voltage applied to the gate electrode (lower gate electrode) Goo of the memory transistor TIO. 2o
The semiconductor layer 1 does not malfunction due to the influence of the gate voltage applied to the gate electrode (upper gate electrode) G20.
5, and a memory transistor T1o and a selection transistor T20+ that share the source and drain electrodes S and D.
72. Although the memory transistor T1o and the selection transistors T2°, T2 .
and operate normally to ensure stable writing, erasing,
Reading can be performed.

In addition, in this thin film transistor memory, since the film thickness of the upper gate insulating film 17 on the outer side from the position facing the source and drain electrodes S and D is thicker, the upper gate electrode G20 and the source and drain electrodes are thicker. S, D
The dielectric strength between the two is also sufficient.

Note that the thin film transistor memory of the above embodiment is provided with two selection transistors T2 for one memory transistor T1o, but in the present invention, one selection transistor is provided for one memory transistor. It can also be applied to thin film transistor memories.

6-7 show a second embodiment of the invention.

The thin film transistor memory of this embodiment has one selection transistor T for one memory transistor TIO.
2Q, FIGS. 6 and 7 are a sectional view and a plan view of the thin film transistor memory, and FIG. 8 is an equivalent circuit diagram of the thin film transistor memory.

The thin film transistor memory of the second embodiment has a lower gate electrode C1 which is the gate electrode of the memory transistor TIO.
A lower gate line GL is formed on the substrate 11 by forming a protruding film 12 below the semiconductor layer 15 so as to face substantially a part of the semiconductor layer 15, so as to cross over the protruding film 12. The lower gate electrode G, o consisting of the protruding film bundle crossing portion is made to face substantially a part of the semiconductor layer 15, and the lower gate insulating film 1 is
The lower gate insulating film 14 has a thickness that covers the lower gate line G L , , on the substrate 11 and exposes the upper surface of the lower gate electrode GIO. It is formed on the planarization insulating film 13 formed in the above. Further, the upper gate electrode G20, which is the gate electrode of the selection transistor T20, is formed to face the entire semiconductor layer 15, and the upper gate insulating film 17 is thicker on the portion corresponding to the memory area. It has become. The memory transistor T1° is composed of a lower gate electrode G1°, a lower gate insulating film 14, a semiconductor layer 15, and source and drain electrodes S and D, and the selection transistor Tz
o is the semiconductor layer 15 and the source and drain electrodes S
, D, a thin film portion of the upper gate insulating film 17, and an upper gate electrode G20.

Note that the thin film transistor memory of this embodiment has only one selection transistor T20, and the basic configuration is the same as that of the first embodiment. Omitted.

In addition, writing of the thin film transistor memory of this example,
Erasing and reading can be performed in the same manner as in the thin film transistor memory of the first embodiment.

Further, in the above embodiment, the upper gate insulating film 17 was formed by half-etching a single layer film to form a thick film part and a thin film part, but this upper gate insulating film 17 has a two-layer film structure. Good too.

9 and 10 show a third embodiment of the present invention,
11 and 12 show a fourth embodiment of the present invention, and in each of these embodiments, the upper gate insulating film 1
7 has a two-layer film structure consisting of a lower layer film 17a and an upper layer film 17b.

First, the third embodiment will be described. As shown in FIG. 9, the thin film transistor memory of this embodiment has a lower layer film 17 . a is the memory region of the lower gate insulating film 14 (the part facing the lower gate electrode G1o)
an upper layer film 17b is formed on the entire surface of the substrate 11, covering the lower layer film 17a, Both the lower layer film 17a and the upper layer film 17b are made of an insulating film (for example, a SiN film) without a charge storage function. The thickness of the lower layer 17a is 3,000 layers, the thickness of the upper layer 17b is 2,000 layers, and the thickness of the thick portion consisting of the lower layer 17a and the upper layer 17b is 5,000 layers. Note that the thin film transistor memory of this embodiment only has a two-layer structure for the upper gate insulating film 17, and other configurations are the same as those of the first embodiment.
Duplicate explanations will be omitted by attaching the same reference numerals to the figures.

The thin film transistor memory of this embodiment is shown in FIG. 3(a).
-(d) or the protruding film 12 and the lower gate line GL in any of the steps of FIGS. 4(a)-(e). Then, a lower gate electrode GIG and a planarization film 13 are formed, and then a third
The memory transistor TI is formed by the steps shown in Figures (e) to (g).
After configuring G, an upper gate insulating film 17 is formed in the step shown in FIG. 10, and an upper gate electrode G20 is formed thereon. It is formed.

First, as shown in FIG. 10(a), the lower layer film 17g of the upper gate insulating film 17 is deposited to a thickness of 3000 nm over the entire surface of the substrate 11 forming the memory transistor T1o.

Next, as shown in FIG. 10(b), the lower layer film 17H
Of these, the portions of the lower gate insulating film 14 between the memory region and the source electrode S and between the memory region and the drain electrode are removed by photolithography.

Next, as shown in FIG. 10(c), the upper layer film of the upper gate insulating film 17: l, 7b is deposited on the entire surface of the substrate 11.
The upper gate insulating film 17 is completed by depositing it to a thickness of 0.00 mm.

That is, this upper gate insulating film 17 connects a portion of the lower gate insulating film 14 above the memory region and a portion outward from a position facing approximately the center of the source and drain electrodes S and D to a lower layer film 17a and an upper layer film 17b. A thick film part (film thickness: 5000 m) of a two-layer film structure consisting of the above is used, and a thin film part (film thickness: 2000 mcm) consisting of only the upper layer film 17b is defined as a part between the memory region and the source and drain electrodes S and D. That is.

Incidentally, the upper gate electrode G20 formed on the upper gate insulating film 17 is formed by depositing a metal film such as aluminum to a thickness of 4000 nm, and depositing this metal film by photolithography, as in the first embodiment. Form by buttering.

On the other hand, in the thin film transistor memory of the fourth embodiment, the first
As shown in FIG. 1, the lower layer film 17 of the upper gate insulating film 17
a is formed over the entire surface of the substrate 11, and an upper layer film 17b is formed on the memory region of the lower gate insulating film 14 (the part facing the lower gate electrode GIO) and on the source and drain electrodes S and D.
The lower layer film 17a and the upper layer film 17b are both insulating films without a charge storage function, and the lower layer film 17
The upper film 17a and the upper film 17b are formed of insulating materials having different etching rates. In addition, in this example,
The lower layer film 17a is a SiN film, and the upper layer film 17b is a 5in2
(silicon oxide) film. Further, the lower layer film 1
The film thickness of 7a is 2000, and the film thickness of upper layer 17b is 300.
There are 0 people, and the thickness of the thick film portion consisting of the lower layer film 17a and the upper layer film 17b is 5000 people. Note that the thin film transistor memory of this embodiment also has an upper gate insulating film 1.
7 only has a two-layer film structure, and the other structure is the same as the above-mentioned No. 1.
Since this is the same as the embodiment shown in FIG.

The thin film transistor memory of this embodiment is shown in FIG. 3(a).
The protrusion film 12, the lower gate line G L , the lower gate electrode GIO and the planarization film 13 are formed in any of the steps shown in ~(d) or FIGS. 4(a) to (c), and then After configuring the memory transistor T1o through the steps shown in FIGS. 3(e) to (g), the upper gate insulating film 17 is formed in the steps shown in FIG. 12, and the upper gate electrode G20 is formed thereon. The upper gate insulating film 17 is formed as follows.

First, as shown in FIG. 12(a), over the entire surface of the substrate 11 on which the 7R moly transistors T and O are formed,
A lower layer film (StN film) 17a of the upper gate insulating film 17 is deposited to a thickness of 2000 nm, and an upper layer film (Si02 film) 17b is deposited over the entire surface of the lower layer film 17a to a thickness of 300 nm.
Deposit to a thickness of 0.00 people.

Next, as shown in FIG. 12(b), the upper layer film 17b
Of these, portions of the lower gate insulating film 14 between the memory region and the source electrode S and between the memory region and the drain electrode are removed by photolithography to complete the upper gate insulating film 17. In this case, since the lower layer film 17a has a different etching rate from the upper layer film 17b, the lower layer film 17a is etched when the upper layer film 17b is etched.
will not be etched.

That is, this upper gate insulating film 17 connects a portion of the lower gate insulating film 14 above the memory region and a portion outward from a position facing approximately the center of the source and drain electrodes S and D to a lower layer film 17a and an upper layer film 17b. A thick film part (film thickness: 5,000 layers) of a two-layer film structure consisting of the above, and a thin film part (film thickness: 2,000 layers) consisting only of the lower layer film 17a between the memory area and the source and drain electrodes S and D. That is.

In the case of this embodiment as well, the upper gate electrode G2o formed on the upper gate insulating film 17 is formed by depositing a metal film such as aluminum to a thickness of 4000 nm, as in the first embodiment. This metal film is formed by patterning using a photolithography method.

The thin film transistor memories of the third and fourth embodiments are also constructed by stacking the memory transistor TIO and the selection thin film transistors T2o, T2o. It is possible to reduce the element area of transistor memory and increase the degree of integration.
Further, the semiconductor layer 15 and the source and drain electrodes S
, D are the memory transistor TIO and the selection transistor 7
Since it is shared with 201T2o, it can be easily manufactured with a small number of steps. Also, in the thin film transistor memories of these embodiments, the memory transistor T
The lower gate electrode G1o, which is the gate electrode 1o, is formed by the protruding film bundle crossing portion of the lower gate line G L r o, which is formed by crossing the protruding film 12 formed opposite to a part of the semiconductor layer 15. Lower gate insulating film 14
The lower gate insulating film 14 is formed on the substrate 11 to a thickness that covers the lower gate lines G L and o and exposes the upper surface of the lower gate electrode GIO. The selection transistors T20. T
The thickness of the upper gate insulating film 17 between the upper gate electrode G20, which is the gate electrode of No. 20, and the semiconductor layer 15 is made thicker on the portion of the semiconductor layer 15 corresponding to the memory area. It is possible to prevent the memory thin film transistor from malfunctioning due to application of gate voltage from the upper gate electrode G20 to the portion corresponding to the memory region of 15. Therefore, the memory transistor T1 that shares the semiconductor layer 15 and the source and drain electrodes S and D can be prevented. Although it is constructed by stacking the memory transistor T1° and the selection transistors T2o, T, and o, it is possible to operate the memory transistor T1° and the selection transistors T2o, T2o normally to perform stable writing, erasing, and reading. can.

Note that the thin film transistor memories of the third and fourth embodiments have two transistors for one memory transistor T, o.
Although these embodiments are provided with one selection transistor T2°, it goes without saying that these embodiments can also be applied to a thin film transistor memory provided with one selection transistor for one memory transistor.

〔Effect of the invention〕

In the thin film transistor memory of the present invention, an upper gate insulating film without a charge storage function is placed on top of a thin film transistor for memory, which is constructed by laminating a lower gate electrode, a lower gate insulating film with a charge storage function, a semiconductor layer, and a source and drain electrode. The semiconductor layer and the source are stacked by stacking a film and an upper gate electrode.

A selection thin film transistor whose drain electrode is shared with a memory thin film transistor is constructed, and this thin film transistor memory is constructed by stacking a memory thin film transistor and a selection thin film transistor. It is possible to increase the degree of integration by reducing the element area of the transistor memory, which is composed of It can be easily manufactured in large quantities.

In this thin film transistor memory, a protruding film is formed on the substrate corresponding to a part of the semiconductor layer, and the protruding film crossing portion of the lower gate line formed on the substrate by overcoming the protruding film is used as the lower gate electrode. The part of the lower gate insulating film facing the lower gate electrode is used as a memory area, and the lower gate insulating film is a planarized insulating film formed on the substrate to a thickness that covers the lower gate line and exposes the upper surface of the lower gate electrode. The upper gate insulating film is formed on the semiconductor layer, and the upper gate electrode is formed to face the entire semiconductor layer, and the thickness of the upper gate insulating film is increased above the portion of the semiconductor layer corresponding to the memory region. Therefore, between the selection thin film transistor region of the semiconductor layer and the lower gate electrode which is the gate electrode of the memory thin film transistor (between the lower gate line), and the memory thin film transistor region of the semiconductor layer (between the memory region of the lower gate insulating film). It is possible to reliably insulate and separate the corresponding portion) from the upper gate electrode which is the gate electrode of the selection thin film transistor. Therefore, according to this thin film transistor memory, the selection thin film transistor does not malfunction due to the influence of the gate voltage applied to the gate electrode (lower gate electrode) of the memory thin film transistor, and
Since the memory thin film transistor does not malfunction due to the influence of the gate voltage applied to the gate electrode (upper gate electrode) of the selection thin film transistor, it is possible to stack the memory thin film transistor and the selection thin film transistor, which share the semiconductor layer and the source and drain electrodes. Despite the structure, the memory thin film transistor and the selection thin film transistor each operate normally for stable writing and erasing.

Reading can be performed.

[Brief explanation of drawings]

1 to 5 show a first embodiment of the present invention, FIGS. 1 and 2 are a sectional view and a plan view of a thin film transistor memory, and FIG. 3 is a manufacturing process diagram of a thin film transistor memory. FIG. 4 is a process diagram showing another method of forming a flattened insulating film, and FIG. 5 is an equivalent circuit diagram of a thin film transistor memory. 6 to 8 show a second embodiment of the present invention. FIGS. 6 and 7 are a sectional view and a plan view of a thin film transistor memory, and FIG. 8 is an equivalent circuit diagram of the thin film transistor memory. be. 9 and 10 are a cross-sectional view of a thin film transistor memory showing an embodiment of fS3 of the present invention, a process chart for forming the upper gate insulating film, and a 11th
This figure and FIG. 12 are a cross-sectional view of a thin film transistor memory showing a fourth embodiment of the present invention, and a process diagram for forming an upper gate insulating film thereof. FIG. 13 is an equivalent circuit diagram of a conventional thin film transistor memory. 11... Substrate, TIO... thin film transistor for memory, T2O... thin film transistor for selection, 12...
Protruding membrane, GL. ...Lower gate line, G1゜...
・Lower gate electrode, 13... Flattening insulating film, 14...
- Lower gate insulating film, 15... semiconductor layer, 16...
Ohmic contact layer, S... source electrode, D...
・Drain electrode, 17... Upper gate insulating film, G2o
...Top gate electrode.

Claims (1)

[Claims] A lower gate electrode formed on an insulating substrate, a lower gate insulating film having a charge storage function formed on the substrate covering the lower gate electrode, and a semiconductor formed on the lower gate insulating film. a source and drain electrode formed on both sides of the semiconductor layer, an upper gate insulating film without a charge storage function formed on the semiconductor layer and the source and drain electrodes, and the upper gate insulator. and an upper gate electrode formed on the film, the lower gate electrode, the lower gate insulating film, the semiconductor layer, and the source and drain electrodes constitute a memory thin film transistor, and the semiconductor layer and the source and drain electrodes and the upper A selection thin film transistor is configured by a gate insulating film and an upper gate electrode, and a protruding film is formed on the substrate to face a part of the semiconductor layer, and a lower part is formed on the substrate by overcoming the protruding film. A portion of the gate line that crosses over the protruding film is used as the lower gate electrode, a portion of the lower gate insulating film facing the lower gate electrode is used as a memory region, and the lower gate insulating film covers the lower gate line on the substrate. The upper gate electrode is formed on a planarizing insulating film formed to a thickness that exposes the upper surface of the lower gate electrode, and the upper gate electrode is formed to face the entire semiconductor layer, and A thin film transistor memory characterized in that the film thickness is increased above a portion of the semiconductor layer corresponding to the memory region.