JPH03290971A - Thin film transistor memory - Google Patents

Abstract

PURPOSE:To enable execution of stable writing, erasure and reading, to increase component density and to facilitate manufacture by laminating a thin film transistor for selection on a thin film transistor for a memory and by enlarging the film thickness of an upper gate insulation film. CONSTITUTION:A thin film transistor TrT10 for a memory and a thin film TrT20 for selection are constructed in lamination, while an upper gate insulation film 16 is constructed of a lower layer film 16a and an upper layer film 16b and made thick on the part of a semiconductor layer 14 corresponding to a memory area. Accordingly, insulative separation can be attained without fail between the region of the TrT20 in the layer 14 and a lower gate electrode G10 of the TrT10 and between the TrT10 and an upper gate electrode G20, respectively. According to this constitution, a malfunction due to the effect of a gate voltage is prevented and the TrT10 and the TrT20 are made to operate normally, so that stable writing, erasure and reading can be executed. Besides, component density is increased by lessening the element area of the memory, and the memory can be manufactured by a reduced number of processes.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to thin film transistor memories.

[Conventional technology]

Recently, E2F with hJ capability for electrical writing, erasing, and reading
2. Description of the Related Art As a memory such as a ROM, a thin film transistor memory is considered in which a memory transistor and a selection transistor are formed of thin film transistors.

Conventionally, this thin film transistor memory is formed by forming a thin film transistor for memory (hereinafter referred to as a memory transistor) and a thin film transistor for selection (hereinafter referred to as a selection transistor) adjacent to each other on an insulating substrate made of glass or the like. A transistor memory is known in which a transistor and a selection transistor are connected in series through a connection wiring that connects the source electrode of one transistor and the drain electrode of the other transistor. Note that the memory transistor and the selection transistor are each composed of a gate electrode, a gate insulating film, an i-type semiconductor layer, and a source and drain electrode, and the gate insulating film of the memory transistor has a multilayer storage function. The gate insulating film of the selection transistor is formed of an insulating film that does not have a charge storage function.

FIG. 13 is an equivalent circuit diagram of the conventional thin film transistor memory. Here, an equivalent circuit of a thin film transistor memory provided with two selection transistors for one memory transistor is shown.

In FIG. 13, T1 is a memory transistor, T2 is two selection transistors arranged on both sides of the memory transistor T1, and the source electrode S of the memory transistor T1 is connected to the drain electrode D2 of one selection transistor T2. The drain voltage h p + of the memory transistor T is connected to the source electrode S2 of the other selection transistor T2. The source electrode S7 of the one selection transistor T2 is the source electrode S of a transistor memory. The drain electrode D2 of the other selection transistor T2 is the drain electrode of the transistor memory. The source electrode So is connected to a source line (not shown), and the drain electrode So is connected to a source line (not shown). I! It is connected to a drain line (not shown). Furthermore, the gate electrode G of the memory transistor T is connected to a first gate line (not shown), and the gate electrodes G2 of the two selection transistors T2 are commonly connected to a second gate line (not shown). Note that a large number of the first and second gate lines are wired in parallel, and a large number of source lines and drain lines are wired orthogonally to the gate lines, and the memory transistor T1 and the selection transistor T
2, the thin film transistor memory is composed of 1.2 and 1.2. They are formed at the intersections of the second gate line and the source and drain lines, respectively.

Writing and erasing of this thin film transistor memory.

Reading is performed as follows.

In FIG. 13, (a) shows the state of voltage application during writing, (b) shows the state of voltage application during erasing, and (c) shows the state of voltage application during reading.

First, writing will be explained. During writing, as shown in FIG. 13(a), the source electrode S is opened. and drain electrode. is grounded (GND), and an ON voltage VON is applied to the gate electrode G2 of the selection transistor T2.

A write voltage voltage vP is applied to the gate electrode G of .

When such a voltage is applied, the selection transistor T2 is turned on, and a write voltage +V is applied between the gate electrode G and the source and drain electrodes S, D, of the memory transistor T1.
, the memory transistor T is in the write state (
OFF state).

Further, during erasing, as shown in FIG. 13(b), the source electrode S. and drain electrode. is grounded (GND) and connected to the gate electrode G2 of the selection transistor T2.
A voltage VoN is applied to the gate electrode G1 of the memory transistor T1, and an erase voltage -, which has a potential opposite to that of the write voltage element VP, is applied to the gate electrode G1 of the memory transistor T1.
Apply V. When such a voltage is applied, the selection transistor T2 is turned on, and the gate electrode G1 and the source and drain electrodes S, D of the memory transistor T are turned on.

A potential difference (Vp) opposite to the write voltage +V occurs between the memory transistor T1 and the memory transistor T1 in the erased state (ON state g
).

On the other hand, at the time of reading, as shown in FIG. 13(e), the gate electrode G and source electrode S of the memory transistor T1.

is grounded (GND), and the selection transistor T2
0Nffi pressure V to the gate electrode G2. Apply N and connect the drain electrode. A read voltage VD is applied to. When such a voltage is applied, if the memory transistor T is in the erased state (ON state), the drain electrode becomes the same. from the source electrode S. A current flows through the source electrode S, and if the memory transistor T is in the write state (OFF state), the current does not flow. Read data is output depending on the presence or absence of current flowing through the source line.

Note that although a thin film transistor memory including two selection transistors T2 for one memory transistor T1 has been described here, some thin film transistor memories include one selection transistor for one memory transistor. .

[Problem to be solved by the invention]

However, the conventional thin film transistor memory
A thin film transistor for memory and a thin film transistor for selection are formed adjacent to each other on a substrate, and the memory transistor and selection transistor are connected in series by connection wiring. Therefore, it is difficult to increase the degree of integration of a memory matrix formed by arranging transistor memories vertically and horizontally.

Moreover, in conventional thin film transistor memories, the gate insulating film of the memory thin film transistor is an insulating film with a charge storage function, and the gate insulating film of the selection thin film transistor is an insulating film without a charge storage function. There is also a problem in that the thin film transistor for selection and the thin film transistor for selection must be manufactured in separate processes, and therefore a large number of processes are required to manufacture the thin film transistor memory.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to reduce the element area of a transistor memory composed of a memory thin film transistor and a selection thin film transistor, thereby increasing the degree of integration. It is an object of the present invention to provide a thin film transistor memory that can be easily manufactured with a small number of steps.

[Means to solve the problem]

The thin film transistor memory of the present invention includes a lower gate electrode formed on an insulating substrate, a lower gate insulating film having an MQ accumulation function and formed on the substrate covering the lower gate electrode, and the lower gate insulating film formed on the substrate. A semiconductor layer formed on the film, source and drain electrodes formed on both sides of this semiconductor layer, and an upper gate without a charge storage function formed on the semiconductor layer and the source and drain electrodes. An insulating film, an upper gate electrode formed on the upper gate insulating film, the lower gate electrode, the lower gate insulating film, a semiconductor layer, and a source.

The drain electrode constitutes a memory thin film transistor,
The semiconductor layer, the source and drain electrodes, the upper gate insulating film, and the upper gate electrode constitute a selection thin film transistor, and the lower gate electrode is formed on a portion of the semiconductor layer on the lower gate line formed on the substrate. a portion of the lower gate insulating film facing the lower gate electrode is formed as a memory region;
Further, a planarizing insulating film is formed on the lower gate line and the lower gate electrode to cover the lower gate line thickly and the lower gate electrode thinly, and the lower gate insulating film is formed on the planarizing insulating film. and the upper gate electrode is formed to face the entire semiconductor layer, and the upper gate insulating film is thicker on a portion of the semiconductor layer corresponding to the memory region. It is.

[Effect]

That is, the thin film transistor memory of the present invention has an upper part without a charge storage function on top of a memory thin film transistor configured by laminating a lower gate electrode, a lower gate insulating film with a charge storage function, a semiconductor layer, and source and drain electrodes. A gate insulating film and an upper gate electrode are laminated to form a selection thin film transistor that shares the semiconductor layer and source and drain electrodes with a memory thin film transistor. Since this thin film transistor memory is constructed by stacking a memory thin film transistor and a selection thin film transistor, the element area of the transistor memory composed of the memory thin film transistor and the selection thin film transistor can be reduced to increase the degree of integration. Furthermore, since the semiconductor layer and the source and drain electrodes are shared by the memory thin film transistor and the selection thin film transistor, it can be easily manufactured with a small number of steps. In this thin film transistor memory, the lower gate electrode is formed to protrude above the lower gate line formed on the substrate so as to face a part of the semiconductor layer, and the part of the lower gate insulating film facing the lower gate electrode is formed to protrude above the lower gate line formed on the substrate. A planarizing insulating film that thickly covers the lower gate line and thinly covers the lower gate electrode is formed on the lower gate line and the lower gate electrode. A lower gate insulating film is formed, and an upper gate electrode is formed to face the entire semiconductor layer, and the upper gate insulating film is thickened over a portion of the semiconductor layer corresponding to the memory region. Therefore, between the selection thin film transistor region of the semiconductor layer and the lower gate electrode which is the gate electrode of the memory thin film transistor (between the lower gate line), and the memory thin film transistor region of the semiconductor layer (the memory region of the lower gate insulating film) It is possible to reliably insulate and separate the upper gate electrode, which is the gate electrode of the selection thin film transistor, from the upper gate electrode, which is the gate electrode of the selection thin film transistor.

Therefore, according to this thin film transistor memory, the selection thin film transistor does not malfunction due to the influence of the gate voltage applied to the gate electrode (lower gate electrode) of the memory thin film transistor, and the memory thin film transistor Because it does not malfunction due to the influence of the game hm pressure applied to the upper gate electrode, even though it is constructed by stacking a memory thin film transistor and a selection thin film transistor that share the semiconductor layer and source and drain electrodes Thin film transistor for memory〉The lister and the thin film transistor for selection are operated at all times to ensure stable writing, erasing, and reading [
, can be done.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

1 to 5 show a second embodiment of the present invention, and FIGS. 1 and 2 are a sectional view and a plan view of a thin film transistor memory.

To explain the structure of this thin film transistor memory, 1 in the figure is an insulating substrate made of glass or the like;
A lower gate electrode GIO is formed at IJ. This lower gate electrode G. is formed locally protruding above the lower gate line GL, formed on the substrate 11, and this lower gate electrode (J I Il) has a width of 3,000 people, with the same width as the lower gate line GL, . Further, a planarizing insulating film 12 is formed on the substrate 11 to cover the lower gate lines GL, o and the lower gate electrode GIO.
2 consists of an insulating film without a charge storage function, and this flattening insulating film J2 is connected to the lower gate line G L . Thickly cover the bottom gate? It is formed to a thickness that thinly covers the 4-pole C+IO. Note that the lower gate line OL of this planarization insulating film 12. The thickness of the upper part is 4000, and the lower gate electrode G. The thickness of the upper part is 1000 people. A lower gate insulating film] 3 is formed on the planarizing insulating film 12 over almost the entire surface of the substrate 11. This upper gate insulating film 13 has a charge storage function throughout its upper layer, and this lower gate insulating film]3
In this method, a memory insulation film 13b made of SiN, which has a charge storage function by increasing the composition ratio of Si (silicon), is added to the base of the lower insulation film 13a made of SiN (silicon nitride), which does not have a charge storage function. It is laminated to form a two-layer film.

The thickness of the lower insulating film 13a is 900, and the thickness of the memory insulating film 13b is 100.

This lower gate insulating film] 3 (memory insulating film 13b)
A semiconductor layer 14 of the type made of amorphous silicon or polysilicon is formed in a pattern corresponding to the element shape of the transistor memory. (Amorphous silicon or polysilicon doped with n-type impurities)
A source electrode S and a drain electrode are formed through an ohmic contact layer 15 consisting of the following. These source electrodes S and drain electrodes are formed on the lower gate insulating film 13 by the lower gate lines GL, o, respectively.
The source line SL and the drain line DL are connected to the source line SL and the drain line DL, which are wired perpendicularly to the source line SL and the drain line DL. Then, the semiconductor layer 1
4 and on the source and drain electrodes S and D, the substrate 1
An upper gate insulating film 16 made of silicon nitride and having no charge storage function is formed over almost the entire surface of the semiconductor device 1 .

Above this upper gate insulating film 16, upper gate lines GL2. is wired parallel to the lower gate line GL2I, and the portion of the upper gate line GL2I above the semiconductor layer 14 is set to the upper gate electrode G2(+).

The lower gate electrode G, the flattening insulating film 12, the lower gate insulating film 13 having a charge storage function, the semiconductor layer 14, and the source and drain electrodes S and D are an inverted staggered memory thin film transistor ( It constitutes Tlo (hereinafter referred to as a memory transistor). Further, the lower gate electrode G, which is the gate electrode of the memory transistor TIo, is arranged so as to face the central part of the semiconductor layer 14 in the channel length direction (the central part between the source and drain electrodes S and D). Approximately 1 of the longitudinal width
Therefore, the lower gate insulating film 13 is formed to have a width of /3, so that the lower gate insulating film 13 is formed to have a width of /3. The central portion facing the area is the memory area.

On the other hand, the upper gate electrode G20 is an electrode facing the entire semiconductor layer 14.
The upper gate insulating film 16 between 20 and the semiconductor layer 14 is
Above the memory region of the lower gate insulating film 13 (the part facing the upper gate electrodes G, .) and the source and drain electrodes S, D
The insulation is made thicker in the outer part from a position facing approximately the center of the insulator, and thinner in the parts between the memory region and the Saone 7 electrode S and between the memory region and the drain electrode. It is considered to be a membrane. That is, this partial gate insulating film 16 consists of a lower layer film 16a formed over the entire surface of the substrate 11 on the semiconductor layer 14 and the source and drain electrodes is and p, and the F layer film 16
An upper layer film 16b having a thickness of 3,000 yen is formed on top of a to correspond to the memory region of the lower gate insulating film 13 described in fFJ and to the outer portions of the source and drain electrodes S and D, respectively, from approximately the center. The film thickness of the upper gate insulating film 16 (the two-layer film part consisting of the lower layer film 16a and the upper layer film 16b) is the same as that of the memory transistor T1o region of the semiconductor layer 14 (the memory region of the lower gate insulating film 13). The thickness is sufficient to prevent the gate voltage from being applied from the upper gate electrode G20 to the portion corresponding to
The thickness of the thin film portion of the upper gate insulating film 16 (single-layer film portion consisting only of the upper layer film 16a) is set to a value such that a partial gate voltage can be applied to the semiconductor layer 14 from the upper gate electrode G2o (2,000 people). ). Note that the film j portion of the "two-part gate insulating film" 6 is formed over the entire length of the insulating film in the length direction of the source and drain lines SL and DL.

Further, on the memory transistor TIU, the semiconductor layer ] 4 and source and drain electrodes S are provided.

Two selection thin film transistors (hereinafter referred to as selection transistors) that share D with the memory transistor T1o
T20. T20 is formed. These two selection transistors T20+ T20 are connected to the +! -Conductor layer 1
4, source and drain electrodes S and D, an upper gate insulating film 16 without a charge storage function, and an upper gate electrode G2.
0, and one selection transistor T2,) includes a semiconductor layer 14, source and drain electrodes SD, and an upper gate insulating film 1.
6 and an upper gate electrode G2o; and upper gate electrode G
,. It is made up of.

These two selection transistors T 2o+ T 2Ll
By making the gate electrode (upper gate electrode) G20 an electrode facing the entire semiconductor layer 14, the C gate
Both selection transistors T 2o, T 2 . is connected in series with the memory transistor TIO by sharing its source 2 and drain electrodes S and D with the memory transistor T1o.

Further, each of the 2m thin film portions of the upper gate insulating film 16 that constitutes the selection transistors T2o and T2o has a width in the channel length direction of the film thickness portion corresponding to the memory area of the upper gate insulating film 13 that is smaller than the lower gate G. ,. By making the width of the lower gate electrode G, smaller than the width of the channel in the longitudinal direction. It is wrapped on both sides. This is done by the memory transistor TIO and both selection transistors T2. , T, , and the selection transistor T2 of the upper gate insulating film 16. , T , , is wrapped around the lower gate electrode C3°, the semiconductor layer 1
A gate electrode (lower gate electrode) G+ of the memory transistor T1o is provided at the boundary between the memory transistor T1o region of No. 4 and the selection transistor T2° region (both sides of the portion of the lower gate insulating film 13 corresponding to the memory region).

Since the gate voltage can also be applied from the gate electrode (upper gate electrode) G20 of the selection transistor "I' 20+ 720, both the memory transistor T1° and the selection transistor T 20+ T 2o are
When N is applied, a current flows from the drain electrode to the source electrode S via the semiconductor layer 14. In this embodiment, the width of the thick portion of the upper gate insulating film 16 above the memory region is approximately 1/2 of the width of the lower gate electrode COO; G. Any width may be used as long as it is less than the width of , and in short, it is sufficient that the thin film portion of the upper gate insulating film 16 faces at least the side edge of the lower gate electrode (710).

FIG. 3 shows a method for manufacturing the thin film transistor memory, and this thin film transistor memory is manufactured through the following steps.

First, as shown in FIG. 3(a), a metal film 30 that will become the gate line G L is deposited on the substrate 1 to a thickness of 500 mm, and a metal film 30 that will become the lower gate electrode G1 is deposited on top of the metal film 30 that will become the lower gate electrode G1. Film 31 is deposited to a thickness of 3000 nm.

Note that the upper metal film 3 that becomes the lower gate electrode G 1t+
1 is made of Ta (tantalum) or the like, and the gate line G
L. The lower metal film 30 is the same as the upper metal film 3.
1 and a metal with a different etching rate, such as Cr (
Chromium), etc.

Next, as shown in FIG. 3(b), the upper layer metal Jl
! 31 by photolithography to form a lower gate electrode GIO, and then the lower metal film 30 is patterned by photolithography to form a gate line GL. form.

Next, as shown in FIG. 3(c), a silanol-based inorganic insulator called SOG (spin-on glass) is coated on the entire surface of the substrate 11 by a spin code method, and this is heated at about 300°C. Heat for about 1 hour and remove the lower gate line GL.
,. The film thickness of the upper part is 4000, and the lower gate electrode G1
6. Form a planarizing insulating film 12 having a film thickness of 1000 nm in the upper part and having a flat upper surface over the entire area.

Next, as shown in FIG. 3(d), the planarized insulating film 1
2, a lower insulating film (SiN film) 13a without a charge storage function and a memory insulating film (St
900 people,
A two-layer lower gate insulating film 13 consisting of a lower insulating film 3a and a memory insulating film 13b is formed, and a type 1 amorphous silicon film is formed on the lower gate insulating film 13. Alternatively, the semiconductor layer 14 made of l-type polysilicon and the ohmic contact layer 15 made of n-type semiconductor (n-type amorphous silicon or n'4!! polysilicon) are successively made by 1000 or 250 people. The metal film 40 for source and drain electrodes made of Cr or the like is further deposited to a thickness of 500 nm.

Next, the metal film 40 for source and drain electrodes is patterned by photolithography, and as shown in FIG.
As shown in FIG.
source and drain electrodes S and D and source and drain lines SL.

DL is formed, and then the ohmic contact layer 15 is connected to the source, drain electrodes S, D, and the source.

Pattern it into the shape of the drain lines SL and DL.

Next, as shown in FIG. 3(f), the semiconductor layer 14 is patterned into the shape of a transistor memory element by photolithography to form a memory transistor T1o. Note that this semiconductor layer 14 is connected to the source line S
L and also remain under the drain line DL over its entire length.

Next, as shown in FIG. 3(g), two SiN films are deposited on the entire surface of the substrate 11 on which the memory transistors T and O are formed.
The lower layer film 16a of the upper gate insulating film 16 is formed by depositing S to a thickness of 1,000 mm, and the entire surface of the lower layer film 16a is covered with S.
An upper layer film 16b is formed by depositing lO□ (silicon oxide) to a thickness of 3000 nm.

Next, as shown in FIG. 3(h), portions of the upper layer film 16b between the memory region of the lower gate insulating film 13 and the source electrode S and between the memory region and the drain electrode are separated. The upper part of the memory region of the lower gate insulating film 13 and the source,
The thickness of the film is thickened in the outer part from the position facing approximately the center of the drain electrodes S and D, and the memory area and the source electrode S are thickened.
An upper gate insulating film 16 is completed in which the film thickness is reduced between the memory region and the drain electrode and between the memory region and the drain electrode. In this case, since the lower layer film 16a has a different etching rate from the soil layer film 16b, the lower layer film 16a is not etched when the upper layer film 16b is etched.

Next, as shown in FIG. 3(i), a metal film of 1 (aluminum) or the like is deposited for 40 minutes on the upper gate insulating film 16.
This metal film is patterned by photolithography to form a pole G20 and an upper gate line GL2 to form two selection transistors T2o and T2. Completed thin film transistor memory.

In addition, in this manufacturing method, the lower gate electrode Gl+'1 and the planarization insulating film 12 are formed by forming the lower gate electrode Gl+'1 as shown in FIGS.
- This lower gate electrode G, which is formed in steps. The planarizing insulating film 12 can also be formed by other methods.

That is, FIG. 4 shows the lower gate electrode G. This shows another method of forming the planarizing insulating film 12.

In this method, the drain electrode G, and lower gate line GL,. After forming the insulating film 12A made of PSG (phosphorous glass) on the entire surface of the substrate 11 using the low pressure CVD method, as shown in FIG. 4(a), as shown in FIG. 4(b). The insulating film 12A is then deposited to a thickness of about 4,000 yen by heating in a steam atmosphere at 850° C. to 1,000° C. for 30 minutes or more or by flow treatment to flatten the insulating film 12A.
As shown in FIG. 4(c), the lower gate line G L is unified. This is a method of forming a flattening insulating film 12 whose upper portion has a thickness of approximately 4000 wafers and the portion above the lower gate electrode G1o has a thickness of approximately 1000 wafers.

Note that even when forming the lower gate electrode GIO and the planarization insulating film 12 by the method shown in FIG. 4, the method shown in FIG.
A thin film transistor memory is manufactured through the steps shown in d) to (i).

FIG. 5 is an isometric circuit diagram of the thin film transistor memory, and this thin film transistor memory has a structure in which a memory transistor T1o and two selection transistors T20+T2o are stacked in one thin film transistor. There is. Note that although the equivalent circuit of one thin film transistor memory is omitted in FIG. 5, this thin film transistor memory has a circuit at the intersection of the upper gate line Czn and the upper gate line G21'l with the source and drain lines SL and DL, respectively. It is formed.

Writing and erasing/reading of this thin film transistor memory are performed as follows.

In FIG. 5, (a) shows the voltage application state during writing IIL, (b) shows the voltage application state during erasing, and (c) shows the voltage application state during reading.

First, to explain about writing, when writing.

As shown in FIG. 5(a), the source electrode S and the drain electrode are grounded (GND), and the gate electrode G2 of the selection transistor T20+T2o is turned ON?
l [i Pressure VON is applied to the gate electrode G of the memory transistor T1°. A write voltage voltage vP is applied to.

When such a voltage is applied, the two selection transistors T 2111 T 20 are turned on, and the gate electrode GIO and the source and drain electrodes S of the memory transistor T I 11 are turned on.

When a write voltage +■ is applied between D and D, charges are trapped in the memory region of the lower gate insulating film 13 (the part of the memory insulating film 13b facing the gate electrode GIO), and the memory transistor TIO becomes in the write state (OFF state). becomes.

Further, during erasing, as shown in FIG. 5(b), the source electrode S and the drain electrode are grounded (GND), and the ON voltage V is applied to the gate electrode G20 of the selection transistor T2o. N is applied, and an erase voltage -VP having a potential opposite to the write voltage +VP is applied to the gate electrode GIO of the memory transistor T10. When such a voltage is applied, the selection transistor T2o+12 (, is turned on, and a potential difference ( -VP) occurs, the charges trapped in the memory region of the lower gate insulating film 13 are released, and the memory transistors T and O enter the erased state (ON state).

On the other hand, during reading, as shown in FIG. 5(c), the gate electrode GIO and the source electrode S of the memory transistor T1o are
is grounded (GND), and the gate electrode G2O1:: ON voltage V of the selection transistor T2O1T20. N is applied, and a read voltage vo is applied to the drain electrode. When such a voltage is applied, the memory transistor T,. If TIO is in an erased state (ON state), a current flows from the drain electrode to the source electrode S, and if the memory transistor TIO is in a written state (OFF state), the current does not flow, so it flows from the source electrode S to the source line. Read data is output depending on the presence or absence of current.

In other words, the thin film transistor memory includes a lower gate electrode G1o and a lower gate insulating film 1 having a charge storage function.
An upper gate insulating film 16 having no charge storage function and an upper gate electrode G20 are stacked on the memory transistor T1O, which is formed by stacking a semiconductor layer 14, a semiconductor layer 14, and source and drain electrodes S and D. Two selection transistors T 20+ T 2o that share the semiconductor layer 14 and source and drain electrodes S and D with the memory transistor T1o.
It is composed of

This thin film transistor memory includes memory transistors T, o and a selection thin film transistor 'r 201
Since it is constructed by stacking the memory transistors T and T2o. and the selection transistor T2゜Tao to reduce the element area of the transistor memory.
The degree of integration can be increased. Also, in this thin film transistor memory, the semiconductor layer 14 and the source and drain electrodes S and D are shared by the memory transistor TIO and the selection transistor T2゜T2(+). , it is possible to manufacture the product with a small number of steps as described above.

Moreover, in this thin film transistor memory, the lower gate electrode GIO is formed on a portion of the semiconductor layer 14 on the lower gate line G L formed on the substrate 11.
The lower gate of the lower gate insulating film 1B is formed to protrude in the J direction. 1llS pole G,. The part facing the memory Cf
i area, and the lower gate line G11o;-i
and above the upper gate electrode Gin, the lower gate line>G
L+. A 1' chloride insulating film 12 is formed to thickly cover the lower gate electrode G, and an upper gate insulating film 13 is formed on this multi-purpose insulating film 12, and the upper gate electrode G is thinly covered.
20 is formed to face the entire semiconductor layer 14, and the thickness of the upper gate insulating film 16 is made thicker in the portion of the semiconductor layer 14 corresponding to the memory area, so that the selection of the semiconductor layer 14 is made easier. The transistor T2o region and the lower gate h which is the gate electrode of the memory transistor T,o
"[Between the pole G1o (between the lower gate line GL1°) and the memory transistor T++ of the semiconductor layer 14"
+ region (portion of the lower gate insulating film 13 corresponding to the memory region) and the selection transistors T,o.

It is possible to reliably insulate and separate the upper gate electrode G20, which is the gate electrode of T2°.

Therefore, according to this thin film transistor memory, the selection transistor TIO is the memory transistor T. gate electrode (lower gate electrode) G. The memory transistor TIO does not malfunction due to the influence of the gate voltage applied to the selection transistor T2. ．． Since there is no malfunction due to the influence of the gate voltage applied to the gate electrode (upper gate electrode) G2o of T2o, the memory transistor T1o and the selection transistors T2o and T2o, which share the semiconductor layer 4 and the source and drain electrodes S and D, Although it is constructed by stacking memory transistors T,. and selection transistor T 20+T 2o can be operated normally to perform stable writing, erasing, and reading.

In addition, in this thin film transistor memory, the thickness of the outer part of the upper gate insulating film 16 from the position facing approximately the center of the source and drain electrodes S and D is also thicker, so that the upper gate electrode G2n and the source and drain electrodes are thicker. S,
The dielectric strength between it and D is also sufficient.

Note that the thin film transistor memory of the above embodiment includes two selection transistors T20 for one memory transistor TIO, but the present invention provides a thin film transistor that includes one selection transistor for one memory transistor. It can also be applied to memory.

6 to 8 show a second embodiment of the invention.

The thin film transistor memory of this example.

One selection transistor T2o is provided for one memory transistor T1o. FIGS. 6 and 7 are a sectional view and a top view of the thin film transistor memory, and FIG. 8 is an equivalent circuit diagram of the thin film transistor memory. be.

The thin film transistor memory of this embodiment has a lower gate electrode GIO which is the gate electrode of the memory transistor T1o.
, the lower gate line GL formed on the substrate 11,
A protruding portion is formed on the semiconductor layer 14 so as to face a part of the semiconductor layer 14, and a portion of the lower gate insulating film 13 facing the lower gate electrode GIO is used as a memory region, and furthermore, a portion of the lower gate insulating film 13 facing the lower gate electrode GIO is formed as a memory region. Above, the lower gate line GL. A pacifying insulating film 12 is formed to thickly cover the lower gate electrodes G1, 1, and a pacifying insulating film 12 is formed to thinly cover the lower gate electrodes G1, 1, and a lower gate insulating film 13 is formed on the pacifying insulating film 12. The electrode G2o is formed to face the entire semiconductor layer 14, and the upper gate insulating film 16 is formed between a lower film 16a that covers the entire semiconductor layer 14 and the source/drain electrodes S and D, and a memory area of the lower gate insulating film 13. This upper gate insulating film is formed as a two-layer film consisting of an upper layer film 16b formed on the portion facing the lower gate electrode G1o and on the outer portion of the source/drain electrodes S, D from a position facing approximately the center thereof. The film 16 is buried at IV< in a portion corresponding to the memory region and the outer portion from approximately the center of the source and drain electrodes S and D, and the memory transistor T1
o is the lower gate electrode GID and the lower gate insulating film]3
, the semiconductor layer 14 and the source and drain electrodes S and D, and the selection transistor T20 includes the semiconductor layer 14 and the source and drain electrodes S and D, a thin film portion of the upper gate insulating film 16, and the upper gate electrode. G2o
It is composed of.

Note that the thin film transistor memory of this embodiment has only one selection transistor T2o, and the basic configuration is the same as that of the previous embodiment. In addition, writing, erasing, and reading of the thin film transistor memory in this embodiment are as follows.
This can be done in the same manner as the thin film transistor memory of the first embodiment.

Further, in the above embodiment, the upper gate insulating film] 6 is composed of a lower layer film 16a covering the entire semiconductor layer 14, and an upper layer film 16b formed thereon to correspond to the memory area of the lower gate insulating film 13. The upper gate insulating film 16 is not limited to the above embodiment, as long as it is made thicker on the portion of the semiconductor layer corresponding to the memory region.

That is, FIGS. 9 and 10 show the third embodiment of the present invention, and FIGS. 11 and 12 show the fourth embodiment of the present invention.1 First, the third embodiment To explain this, in the thin film transistor memory of this embodiment, as shown in FIG. The upper layer film 16b is formed on the memory region (the part facing the lower gate electrode GIO) of the gate insulating film 13 and on the part outside from the position facing substantially the center of the source and drain electrodes S, D. It is formed on the entire surface of the substrate 11 to cover the lower layer film 16a, and both the lower layer film 16a and the upper layer film 16b are insulating films (for example, SiN films) that do not have a charge storage function.
It consists of Further, the thickness of the lower layer film 16a is 30
00 people, the thickness of the upper layer film 16b is 2000 people, and the thickness of the thick film portion consisting of the lower layer film 16a and the upper layer film 16b is 5
000 people.

Note that the thin film transistor memory of this embodiment differs only in the structure of the upper gate insulating film 16, and other configurations are the same as those of the first embodiment, so duplicate explanations will be omitted by assigning the same reference numerals to the figures. do.

The thin film transistor memory of this embodiment is shown in FIG. 3(a).
In the process of ~(C) or the process of FIG.
,. and a planarization film 12 is formed, and then the steps shown in FIGS. 3(d) to (
After configuring the memory transistor T1o in step f), the upper gate insulating film 16 is formed in the step shown in FIG. 10, and the upper gate electrode CZO is formed thereon. 16 is formed as follows.

First, as shown in FIG. 10(a), the lower film 16a of the upper gate insulating film 16 is deposited to a thickness of 3000 nm over the entire surface of the substrate 11 forming the memory transistor T1o.

Next, as shown in FIG. 10(b), the lower layer film 16a
Of these, the portions of the lower gate insulating film 13 between the memory region and the source electrode S and between the memory region and the drain electrode are removed by photolithography.

Next, as shown in FIG. 10(c), the upper layer film 16b of the upper gate insulating film 16 is deposited on the entire surface of the substrate 11 to a thickness of 2000 nm to complete the upper gate insulating film 16.

That is, this upper gate insulating film 16 connects a portion of the lower gate insulating film 13 above the memory region and a portion outward from a position facing approximately the center of the source and drain electrodes S and D to a lower layer film 16a and an upper layer film 16b. A thick film part (film thickness: 5000 m) of a two-layer film structure consisting of That is.

Note that the upper gate electrode G2n formed on the upper gate insulating film 16 is formed by depositing a metal film such as aluminum to a thickness of 4000 nm, and depositing this metal film by photolithography, as in the first embodiment. It is formed by patterning.

On the other hand, in the thin film transistor memory of the fourth embodiment, the first
As shown in FIG. 1, the upper gate insulating film 16 is a single layer film, and its surface is selectively half-etched to form a thick film part and a thin film part.
The thickness of the thick film part of 6 is 5000 people, and the film thickness of the thin film part is 2.
000 people. Note that the thin film transistor memory of this embodiment also differs only in the structure of the upper gate insulating film 16, and other configurations are the same as those of the first embodiment, so duplicate explanations will be omitted by assigning the same reference numerals to the figures. do.

The thin film transistor memory of this embodiment is shown in FIG. 3(a).
In the process of ~(C) or the process of FIG.
oo and a planarization film 12 are formed, and then the steps shown in FIGS. 3(d) to (
Memory transistor T, by the step f). After forming the upper gate insulating film 16, the upper gate insulating film 16 is formed in the step shown in FIG. 12, and the upper gate electrode G 211 is formed thereon. It is formed.

First, as shown in FIG. 12(a), an upper gate insulating film (SiN film with no charge storage function) 16 is formed over the entire surface of the substrate 11 that constitutes the memory transistor T1o. Deposit to thickness (5000 people).

Next, as shown in FIG. 12(b), the memory region (of the lower gate insulating film 13 of the upper gate insulating film 16)
The portions between the lower gate electrode (opposing portion of the lower gate electrode GIO) and the source electrode S and between the memory region and the drain electrode are half-etched to a depth of 3000 mm by photolithography, and this upper gate insulating film 16 The upper part of the memory area and the outer part from the position facing approximately the center of the source and drain electrodes S and D have a film thickness of 5000 mm.
It is processed into a shape in which the thick film part is made 2,000 thick, and the part between the memory area and the source and drain electrodes S and D is made into a thin film part with a thickness of 2000 people.

Note that in this embodiment as well, the upper gate electrode G20 formed on the upper gate insulating film 16 is formed by depositing a metal film such as aluminum to a thickness of 4000 nm, as in the first embodiment. This metal film is patterned and formed by photolithography.

The thin film transistor memories of the third and fourth embodiments also include a memory transistor T1o and a selection thin film transistor T20. Since it is constructed by stacking the memory transistor TIO and the selection transistor T2. , T2. It is possible to increase the degree of integration by reducing the element area of the transistor memory composed of the memory transistor TIO and the selection transistor T2. .

Since it is shared with T2O, it can be easily manufactured with a small number of steps. Furthermore, in the thin film transistor memories of these embodiments, the lower gate electrode GIO, which is the gate electrode of the memory transistor T1o, is placed on the lower gate line GL, o formed on the random plate 11 and facing a part of the semiconductor layer 14. A portion of the lower gate insulating film 13 facing the lower gate electrode G1o is formed to protrude as a memory region, and further the lower gate line GL. and a lower gate line G on the lower gate electrode G1o.
Lower gate electrode G, thickly covering L+o. A thin planarizing insulating film 12 is formed to cover the planarizing insulating film 12.
A lower gate insulating film 13 is formed thereon, and the film thickness of the upper gate insulating film 16 between the upper gate electrode G2Ll, which is the gate electrode of the selection transistor T20+T20, and the semiconductor layer 14 is determined by The semiconductor layer 1 is thicker on the part corresponding to the memory area.
It is possible to prevent the memory thin film transistor from malfunctioning due to application of gate voltage from the upper gate electrode G2o to the portion corresponding to the memory region of semiconductor layer 1.
4, and a memory transistor TIo and a selection transistor T20+T that share the source and drain electrodes S and D.
Although the memory transistor T, is constructed by stacking the memory transistors T and 2o. and selection transistors T2o, T2o
and operate normally to ensure stable writing, erasing,
Reading can be performed.

Note that the thin film transistor memories of the third and fourth embodiments have two transistors for one memory transistor TIO.
Of course, these embodiments can also be applied to a thin film transistor memory having one selection transistor for one memory transistor.

〔Effect of the invention〕

In the thin film transistor memory of the present invention, an upper gate insulating film without a charge storage function is placed on top of a thin film transistor for memory, which is constructed by laminating a lower gate electrode, a lower gate insulating film with a charge storage function, a semiconductor layer, and a source and drain electrode. The semiconductor layer and the source are stacked by stacking a film and an upper gate electrode.

This is a selection thin film transistor whose drain electrode is shared with a memory thin film transistor. Since this thin film transistor memory is constructed by stacking a memory thin film transistor and a selection thin film transistor, it is possible to increase the degree of integration by reducing the element area of the transistor memory composed of the memory thin film transistor and the selection thin film transistor. Furthermore, since the semiconductor layer and the source and drain electrodes are shared by the memory thin film transistor and the selection thin film transistor, the device can be manufactured in a compact manner with a small number of steps. In this thin film transistor memory, the lower gate electrode is formed to protrude above the lower gate line formed on the substrate so as to face a part of the semiconductor layer, and the part of the lower gate insulating film facing the lower gate electrode is formed to protrude above the lower gate line formed on the substrate. A planarizing insulating film is formed on the lower gate line and the lower gate electrode to form a memory area, and a planarizing insulating film is formed on the lower gate line and the lower gate electrode to thickly cover the lower gate line and thinly cover the lower gate electrode. is formed, and the upper gate electrode is formed to face the entire semiconductor layer, and the film 1= of the upper gate insulating film is made thicker on the portion of the semiconductor layer corresponding to the memory region. between the selection thin film transistor region of the semiconductor layer and the lower gate electrode that is the gate electrode of the memory thin film transistor (between the lower gate line), and the memory thin film transistor region of the semiconductor layer (corresponding to the memory region of the lower gate insulating film). portion) and the upper gate electrode, which is the gate electrode of the selection thin film transistor, can be reliably insulated and separated from each other. Therefore, according to this thin film transistor memory, the selection thin film transistor does not malfunction due to the influence of the gate voltage applied to the gate electrode (lower gate electrode) of the memory thin film transistor, and the memory thin film transistor Because it does not malfunction due to the influence of the gate voltage applied to the upper gate electrode (upper gate electrode), the memory The thin film transistor for use and the thin film transistor for selection operate normally for stable writing.

Erasing and reading can be performed.

[Brief explanation of drawings]

1 to 5 show a first embodiment of the present invention. FIGS. 1 and 2 are a sectional view and a plan view of a thin film transistor memory, and FIG. FIG. 5 is an equivalent circuit diagram of a thin film transistor memory. 6 to 8 show a second embodiment of the present invention. FIGS. 6 and 7 are a sectional view and a plan view of a thin film transistor memory, and FIG. 8 is an equivalent circuit diagram of the thin film transistor memory. be. FIGS. 9 and 10 are cross-sectional views of a thin film transistor memory showing a third embodiment of the present invention and a process diagram for forming an upper gate insulating film thereof, and FIGS. 11 and 12 are diagrams showing a fourth embodiment of the present invention. FIG. 2 is a cross-sectional view of a thin film transistor memory and a process diagram for forming an upper gate insulating film thereof. FIG. 13 is an equivalent circuit diagram of a conventional thin film transistor memory. 11... Substrate, Tlo... thin film transistor for memory, T2O... thin film transistor for selection, GL,
,... lower gate line, Gin... lower gate electrode, 12... 1 planarization insulating film, 13... lower gate insulating film, 14... semiconductor layer, 15... ohmic contact layer, S... Source electrode, D... Drain electrode, 16... Upper gate insulating film, G2o... Upper gate electrode.

Claims (1)

[Claims] A lower gate electrode formed on an insulating substrate, a lower gate insulating film having a charge storage function formed on the substrate covering the lower gate electrode, and a semiconductor formed on the lower gate insulating film. a source and drain electrode formed on both sides of the semiconductor layer, an upper gate insulating film without a charge storage function formed on the semiconductor layer and the source and drain electrodes, and this upper gate insulating film. and an upper gate electrode formed on the upper gate, the lower gate electrode, the lower gate insulating film, the semiconductor layer, and the source and drain electrodes constitute a memory thin film transistor, and the semiconductor layer, the source and drain electrodes, and the upper gate The insulating film and the upper gate electrode constitute a selection thin film transistor, and the lower gate electrode is formed protrudingly above the lower gate line formed on the substrate, facing a part of the semiconductor layer, and forming the lower gate electrode. A portion of the gate insulating film facing the lower gate electrode is used as a memory region, and further a planarizing insulating film is provided on the lower gate line and the lower gate electrode, the lower gate line being thickly covered and the lower gate electrode being thinly covered. the lower gate insulating film is formed on the planarized insulating film, the upper gate electrode is formed to face the entire semiconductor layer, and the thickness of the upper gate insulating film is A thin film transistor memory characterized in that the semiconductor layer is thickened on a portion corresponding to the memory region.