JPH03290948A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having a reduced parasitic resistance and a high speed-power product by a method wherein a silicon single crystal layer is formed on a substrate on which a silicon oxide film is formed and U-shaped trenches which reach the substrate are formed from the surface of the silicon single crystal layer and buried layers are buried in the U-shaped trenches with insulating films therebetween. CONSTITUTION:An Si oxide film 203 is formed on the surface of an Si substrate 201 and a single crystal substrate is put on the surface of the film 203 and bonded to the surface by compression and polished. Then a buried layer 212 and an Si epitaxial film 213 are formed. After that, U-shaped trenches 231 which pierce through the film 213, the layer 212 and the film 203 and reach the substrate 201 are formed. After Si oxide films 233 are formed on the side wall surfaces of the trenches 231 only, polycrystalline Si layers 234 are formed in the trenches 231. With this constitution, soft-error strength can be improved, a parasitic resistance can be reduced and a speed-power product can be improved.

Description

[Detailed description of the invention]

[0001]

[Industrial application field]

The present invention relates to semiconductor devices, and particularly to SOI (Sili
The present invention relates to a semiconductor device having an insulating isolation region having a U-shaped groove (hereinafter referred to as a U-groove) structure. [0002]Related Art As the speed of silicon semiconductor devices increases, methods for reducing parasitic capacitance of diffusion layers and the like forming semiconductor elements have become important. SOI structure is an effective way to reduce parasitic capacitance. In the SOI structure, a silicon single crystal film is formed on a substrate or film made of an insulator. A semiconductor element is formed on this silicon single crystal film. [0003] The original SOI structure was 5O3 (Silicon
It had a 5apphireor 5pinel) structure. This is a structure in which silicon is grown heteroepitaxially on the surface of a sapphire or spinel substrate. However, this was disadvantageous in terms of economy. More than that, there was a major problem in that the thermal expansion coefficients of these substrates and the silicon single crystal film were too different, making them difficult to handle and difficult to process. [0004] Subsequently, with the progress of miniaturization of semiconductor devices, it has become important to improve resistance to soft errors induced by α particles. Further, with the progress of miniaturization of semiconductor elements, research and development of three-dimensional devices has been progressing. Along with these trends, SOI with a new structure different from SO8
A structure has emerged. [0005] There are three types of these recent SOI structures. In the first structure, a silicon single crystal film is formed on a silicon substrate on which an insulating film is formed. The method for forming this consists of the following method. An insulating film is formed on the surface of a silicon single crystal, a deposited film made of amorphous silicon or polycrystalline silicon is formed on the surface, and this deposited film is made into a single crystal by, for example, laser irradiation. In this structure, the crystallinity of the silicon single crystal film is difficult. [0006] In a recent second SOI structure, a silicon oxide film is formed in a shallow portion from the surface of a silicon single crystal substrate. This is SIMOX (Separat 1onby
It is called IMplanted Oxygen. This is 1017~ on the surface of a silicon single crystal substrate.
It is obtained by ion-implanting 1011018C oxygen at high energy and annealing at a high temperature of around 1300°C. In this structure, the minimum value of the dislocation density in the silicon single crystal layer on the surface is 104 cm-2. The thickness of the silicon oxide film at this time is approximately 200 nm at most. S.I.
There are two barriers to adopting the MOX structure in actual devices. The first barrier is economics. If the SIMOX structure is to be used in an actual device, the thickness of the silicon oxide film must be increased. In order to reduce parasitic capacitance, it is better that the silicon oxide film under the surface silicon single crystal layer be thicker. This can be achieved by repeating operations consisting of ion implantation, high-temperature annealing, and epitaxial growth of silicon multiple times, if economic efficiency is not considered. The second barrier is junction leakage caused by crystal defects. In this structure, oxygen has a Gaussian distribution in the silicon single crystal layer on the surface. In addition to the presence of dislocations during the formation stage of the SIMOX structure, the precipitation of oxygen in a Gaussian distribution at temperatures of 600-700° C. causes stacking faults and the generation of new dislocations. [0007] Recently (7) SOI (7) The third structure includes BESOI
(Bonding and Etch back
There is a structure called SOI (abbreviation for SOI). In this structure, a silicon single crystal base is thermocompression bonded to a substrate on which a silicon oxide film is formed. This structure has a low crystal defect density in the silicon single crystal on the silicon oxide film, and can be manufactured at low cost. [0008] Schottky clamp type IK bit ECL R
An example of adopting the above-mentioned BESOI in an AM cell is I.
EDM Technical Digest 198
8, pp. 870-872 (IEDM Tech,
Digest, pp870-872.1988). The purpose of this structure in this report is to
These are improved resistance to soft errors induced by alpha particles and reduced parasitic capacitance. For example, the parasitic capacitance between the silicon substrate and the collector region is reduced to about 1/4 compared to when a normal U-groove structure is adopted. The parasitic capacitance between the silicon substrate and the collector region is 6
It accounts for 0 to 70%. FIG. 13 is a schematic cross-sectional view of the semiconductor device in this report. [0009] The configuration of this semiconductor device is as follows. For example, the surface of the P-type silicon substrate 101 has a film thickness of 1 μm.
A silicon oxide film 103 of about 100 mL is formed. The silicon single crystal substrate thermocompressed onto the surface of the silicon oxide film 103 is further thinned by etching back, and an N-type impurity is introduced into it, which becomes an N-type buried layer 112. An N − type silicon epitaxial film 113 is deposited on the surface of the buried layer 112 . In this case, the silicon single crystal layer is the buried layer 11.
2 and a silicon epitaxial film 113. A U-groove 131 is provided extending from a predetermined position on the surface of the silicon epitaxial film 113 to the silicon oxide film 103. A sidewall insulating film 132 is provided on the sidewall surface of the U-groove 131. The thickness of the sidewall insulating film 132 is thinner than that of the silicon oxide film 103. Polycrystalline silicon 134 is buried inside the U-groove 131 with a sidewall insulating film 132 interposed therebetween. On the surface of the silicon epitaxial film 113, Nu
region 141, P type base region 142. and an N type emitter region 143. The collector region in a broad sense is the portion of the silicon epitaxial film 113 that is left without forming the diffusion region. Buried layer 112. and an N type region 141. Silicon epitaxial film 113. N type region 141. P-type base region 142. N type emitter region 143. A surface protection film 148 is provided on the surface of the U-groove 131. N type region 141 of surface protection film 148. P-type base region 142. N type emitter region 143. and the collector electrode 151 . through the opening formed in the silicon epitaxial film 113 . Base electrode 152, emitter electrode 153. and a Schottky electrode 154 are provided. [0010] Parasitic capacitance between the collector region and the substrate in a broad sense (Co8)
is the sum of the parasitic capacitance (C) between the bottom surface of the collector region in a broad sense and the substrate and the parasitic capacitance (C) between the side surface of the collector region in a broad sense and the substrate C5(B). C65 (BO2(S)) in the above-mentioned semiconductor device is lower than that in a normal bipolar semiconductor device due to the presence of the thick silicon oxide film 103 between the silicon substrate 101 and the collector region in a broad sense. C in the above semiconductor device is the same as in a normal bipolar semiconductor device. By reducing C3(S) of C65(B), Ccs becomes 1
It will be about /4. Note that this C is a capacitance (Co process) formed between the side surface of the collector region in a broad sense and the polycrystalline silicon 134, and a capacitance formed between the polycrystalline silicon 134 and the silicon substrate 101. (C18). Due to the difference in the thickness of the insulating film and the facing area, it is Co1)CIs. [0011]

[Problem to be solved by the invention]

In order to increase the speed of semiconductor devices, reducing parasitic capacitance is important from the viewpoint of improving the speed-power product. 2. Description of the Related Art The speed of semiconductor devices has been increased with the progress of miniaturization of semiconductor elements that constitute semiconductor devices. Increasing the speed of semiconductor devices requires a large amount of current to flow in order to drive miniaturized semiconductor elements. The current density in the semiconductor device increases, and the generation of Joule heat locally increases rapidly. If this heat generation is left untreated, the performance of the semiconductor element will deteriorate. Therefore, in order to increase the speed of semiconductor devices, it is important to reduce parasitic capacitance and improve the heat dissipation effect of heat generated from semiconductor elements. A gas with low thermal conductivity exists above the semiconductor element. The bottom surface of the semiconductor element is connected directly or via a material with high thermal conductivity to a metal material that constitutes the package of the semiconductor device. Therefore, Joule heat from the semiconductor element is generally radiated from the bottom surface of the semiconductor element. [0012] However, in the above BESOI structure, the heat dissipation effect is lower than in the normal case. The thermal conductivity of silicon oxide film is about two orders of magnitude lower than that of silicon single crystal. Therefore, the heat dissipation effect at the bottom surface of the bipolar element is reduced. BES
If the thickness of the silicon oxide film on the silicon substrate in the OI structure is made thinner, the heat dissipation effect will be improved. Since the improvement of heat dissipation effect related to the thickness of the silicon oxide film and the reduction of parasitic capacitance are in a contradictory relationship, it is impossible to achieve both in the BESOI structure reported above. [0013] An object of the present invention is to provide a semiconductor device that reduces parasitic resistance while maintaining soft error resistance and has a high speed-power product. An object of the present invention is to provide a semiconductor device having a structure that employs an insulation isolation region of an SOI structure and a U-groove structure, and which approaches the heat dissipation effect of a semiconductor device that does not have an SOI structure but has an insulation isolation region of a U-groove structure. It is something to do. [0014]

[Means to solve the problem]

The semiconductor device of the present invention has a silicon single crystal layer on a substrate having a silicon oxide film formed on the surface thereof, and has an insulating isolation region having a U-groove structure extending from the surface of the silicon single crystal layer to the substrate. The substrate is preferably made of silicon or silicon carbide (SiC). An insulating film is provided on the side wall surface of the U-groove. This insulating film is preferably made of at least one of a silicon oxide film and a silicon nitride film. A buried object is embedded inside the U-groove with an insulating film interposed therebetween. The implant is preferably polycrystalline silicon or silicon carbide. The sum of the thickness of the silicon single crystal layer provided on the substrate and the thickness of the silicon oxide film formed on the substrate is the thickness of the silicon oxide film formed into the U-groove that can be processed, based on the side wall surface of the U-groove. It is preferable that the thickness of the insulating film is greater than that of the insulating film provided on the insulating film. The semiconductor device in the present invention is a bipolar semiconductor device or a MOS semiconductor device. [0015]

【Example】

Next, the present invention will be explained with reference to the drawings. [0016] A case where the first embodiment of the present invention is applied to a bipolar semiconductor device will be described using schematic cross-sectional views in the order of steps shown in FIGS. 1 to 4. [0017] First, a silicon oxide film 203 is formed on the surface of a P-type silicon substrate 201, for example. The film thickness of this is approximately 1.0
It is μm. A silicon single crystal substrate is superimposed on the surface of silicon oxide film 203. A high voltage is applied to this at high temperature, and it is pressed against the silicon oxide film 203. after that,
The silicon single crystal substrate is etched back to form a silicon single crystal substrate 211 with a film thickness of 1.0 μm [FIG. 1] [0018] Next, arsenic is diffused into the silicon single crystal substrate 201, and N
A mold buried layer 212 is formed. Next, an N- type silicon epitaxial film 213 is formed on the surface of the buried layer 212.
is deposited. The thickness of the silicon epitaxial film 213 is approximately 1.0 μm. The silicon single crystal layer in the bipolar semiconductor device to which this embodiment is applied is composed of a silicon epitaxial film 213 and a buried layer 212. Next, a silicon oxide film 221 is formed on the surface of the silicon epitaxial film 213. A silicon nitride film 222 is sequentially formed. Next, anisotropic etching is performed using a normal photolithography technique and 7-reactive ion etching (hereinafter referred to as RIE) to form the silicon epitaxial film 213.
．． Buried layer 212. A U-groove 231 is formed that penetrates the silicon oxide film 203 and reaches the silicon substrate 201 from the surface of the silicon single crystal layer. The width and depth of the U-groove 231 are approximately 1.0 μm and approximately 4 μm. 1i? It is rjf1ushid−ot1υkoj/15jlLjJ. Subsequently, a silicon oxide film 233 is deposited on the entire surface by high temperature CVD (referred to as HTCVD) [FIG. 2]. The thickness of the silicon oxide film 233 is approximately 0.1 μm. The reason for using the HTCVD method is that it has excellent step coverage and the resulting deposited film has excellent film quality (in the case of a silicon oxide film, the film quality is almost the same as that of a silicon oxide film formed by thermal oxidation). Note that instead of this, a silicon oxide film formed by thermal oxidation or a silicon nitride film formed by CVD may be used. [0019] Next, the silicon oxide film 233 is etched back by RIE, and the silicon oxide film 233 on the surface of the silicon nitride film 222 and the bottom of the U-groove 231 is removed. The silicon oxide film 233 remains only on the side wall surface of the U-groove 231. This will function as a sidewall insulating film. Subsequently, polycrystalline silicon having a thickness of 2.0 μm is deposited on the entire surface, and this is etched back to form polycrystalline silicon 234 buried inside the U-groove 231. During this etchback, the silicon nitride film 222 functions as a stopper. Thereafter, a silicon nitride film 222. The silicon oxide film 221 is sequentially etched away. Next, boron ions are selectively implanted into the surface of the silicon epitaxial film 213, and the base region 242 of the silicon
is formed. This is the depth of the diffusion layer of the base region 242. At this stage, the formation of the collector region in a broad sense is completed. This is a silicon epitaxial film 213 . N area 241. and a buried layer 212. Next, a silicon oxide film 249 as a surface protection insulating film is formed over the entire surface. The film thickness of this is about 0.2. An opening is selectively provided in the silicon oxide film 249, phosphorus is diffused, and an N-type emitter region 243 is formed. Subsequently, openings are selectively provided in the silicon oxide film 249 to form collector electrodes 251 . Base electrode 252. Emitter electrode 253
is formed [Figure 4]. These electrodes are made of, for example, an aluminum film. [0021] FIG. 5 is a schematic plan view corresponding to FIG. 4. The area of the bottom surface of the collector region in contact with the silicon oxide film 203 is
This is the same area as the bottom surface of the buried layer 212 divided by the groove 231, which is 200 μm 2 . Also, the area of the side surface of the base region 242 is 0.3X (10+2X12) μ
m2 (approximately 10 μm2), the area where the collector region in a broad sense contacts the U groove 231 is (1+1)X (
2X10+2X20)μm2-10μm2=110μm
It becomes 2. [0022] A bipolar semiconductor device having the conventional BESOI structure shown in FIG. 13 and having an isolation region having a U-groove structure, and a bipolar semiconductor device having an isolation region having a normal U-groove structure were fabricated. The materials and dimensions of each of these components were the same as those shown in this example. A comparison was made between these bipolar semiconductor devices and the bipolar semiconductor device according to this example. [0023] Parasitic capacitance between the collector region and the silicon substrate in a broad sense (
Ccs) in the bipolar semiconductor device according to this embodiment is about 1/4 of that of a bipolar semiconductor device having an ordinary U-groove structure insulation region, as in the conventional device shown in FIG.
Met. As shown in this example, the materials of each component,
In the bipolar semiconductor device according to this embodiment and the conventional device shown in FIG. 13, Cc
Since s(s)=5°50, C (=Cc■) becomes dominant in C. The value of C3(B) C3C3(S)C is almost the same as that of C3(S) in a bipolar semiconductor device having an ordinary U-groove structure insulating isolation region. Nevertheless, the fact that the above results were obtained means that by employing the SOI structure, C has been greatly reduced to about 1/20 of that in the normal case, C3(B). [0024] In the bipolar semiconductor device of this embodiment, heat is mainly radiated from the side surface of the bipolar element rather than from the bottom surface. Regarding the three types of bipolar semiconductor devices described above, the temperature rise ΔT of the semiconductor device with respect to the collector current Ic was measured. Figure 6 shows the results. In the figure, line A is the measurement result of this example, and line B is the measurement result of the bipolar semiconductor device having the structure shown in FIG. Line C is the measurement result of a bipolar semiconductor device having an insulating isolation region with a normal U-groove structure. By comparing the reciprocals of ΔT in the figure, the heat dissipation effects can be compared. The heat dissipation effect of the bipolar semiconductor device having the structure shown in FIG.
/6. In this embodiment, it is approximately 1/2. Assuming that C68 accounts for 60% of the total parasitic capacitance, the speed
Consider the power product. The speed-power product of the semiconductor device having the structure shown in FIG. 13 is about 40% of the speed-power product of a bipolar semiconductor device having an ordinary U-groove structure insulation region. On the other hand, the speed-power product in this embodiment is about 120% of the speed-power product of a bipolar semiconductor device having an ordinary U-groove structure insulation region. This shows the following. In this embodiment, although the heat dissipation effect is lower than that of a bipolar semiconductor device having an ordinary U-groove structure insulating isolation region, the effect of reducing the parasitic capacitance outweighs the heat dissipation effect. Furthermore, the soft error resistance is improved compared to a bipolar semiconductor device having an ordinary U-groove structure insulating isolation region. [0025] When the bipolar element is further miniaturized, the reduction in the side surface area of the bipolar element is less than the reduction in the bottom surface area. Therefore, a structure with good heat dissipation effect from the sides becomes increasingly effective. Incidentally, if only the heat dissipation effect from the side is compared, this embodiment is superior to a bipolar semiconductor device having an ordinary U-groove structure insulating isolation region. [0026]Although this embodiment is an example applied to a bipolar semiconductor device, this embodiment can also be applied to an MO8 semiconductor device. In this case, first, the thickness of the silicon single crystal substrate 211 shown in FIG. 1 is reduced to about 0.2 to 0.5 μm. Thereafter, an insulating isolation region having a U-groove structure is formed, followed by formation of a MOS device. If the MOS half-embodiment is applied to this, all parasitic capacitances other than the side surfaces of the source and drain regions facing each other in the channel region can be reduced to about 1/20. Therefore, effects similar to those of the bipolar semiconductor device described above can be obtained. [0027] FIG. 72 FIG. 8 is a schematic cross-sectional view for explaining a second embodiment of the present invention. FIG. 7 shows an example applied to a bipolar semiconductor device, and FIG. 8 shows an example applied to a MOS semiconductor device. In this embodiment, the material buried inside the U-groove 231 is silicon carbide 235 instead of the polycrystalline silicon in the first embodiment. [0028] The bipolar semiconductor device shown in FIG. 7 is the same as the first embodiment except that silicon carbide 235 is used. A method for forming silicon carbide 235 will be described. First, a silicon oxide film 233 is formed on the side wall surface of the U-groove 231. At this time, the silicon single crystal layer (buried layer 21
2 and a silicon epitaxial film 213) is covered with a silicon nitride film or the like. Subsequently, at a temperature of about 600°C, SiHC1, CH, HCI
, and H2, silicon carbide 235 is selectively grown inside the U-groove 231. [0029] The MOS semiconductor device shown in FIG. 8 will be described. In this case, the silicon single crystal layer is the P well 214 and the N well 21.
It consists of 5. The thickness of the silicon single crystal layer is 0.2
It is about 0.5 μm. Source/drain regions are formed in a self-aligned manner with respect to the gate insulating film 244 and the gate electrode 245. N type source drain region 2
46 is formed in the P well 214, and P type source/drain regions 247 are formed in the N well 215. The bottoms of the source/drain regions 246° and 247 are in contact with the silicon oxide film 203. Source/drain region 24
5.246 is formed in self-alignment with the U-groove 231 except on the channel region side. The gate electrode 245. Source/drain region 246. A metal wiring 255 is provided to connect to the source/drain region 247. [0030] The thermal conductivity of silicon carbide is two to three times higher than that of polycrystalline silicon. Therefore, in the semiconductor device of this example,
The heat dissipation effect from the side surface of the semiconductor element is improved compared to the first embodiment. [00313] FIG. 9 is a schematic cross-sectional view for explaining the third embodiment of the present invention. This figure shows a state before formation of bipolar elements in a bipolar semiconductor device. MOS semiconductor devices also have the following characteristics: Similar to the second embodiment, this embodiment can be applied. In this embodiment, a silicon carbide film 205 formed on a silicon substrate 201 by a CVD method is used as the substrate. The thickness of the silicon carbide film 205 is 2 to 5 μm.
It is about m. The thickness of the silicon oxide film 204 is 0.1~
It is about 0.5 μm. The silicon oxide film 204 is HT
It is preferable to form by CVD method. This silicon oxide film 204 is necessary to obtain the BESOI structure. If the operating speed is, for example, IGH2, these two film thicknesses are set taking into account that the dielectric constant of silicon carbide is about four times that of a silicon oxide film. The rest of this embodiment is the same as the first embodiment. [0032] In this example, the heat dissipation effect on the bottom surface of the bipolar element is the first. This is improved over the second embodiment. U groove 23
Since 1a is connected to the silicon carbide film 205 having high thermal conductivity, the heat dissipation effect on the side surfaces of the bipolar element is somewhat improved compared to the first embodiment. In addition, this example is
Similar effects can be obtained when applied to an OS semiconductor device. [0033] FIG. 10 is a schematic cross-sectional view for explaining a fourth embodiment of the present invention. This figure shows a state before formation of bipolar elements in a bipolar semiconductor device. MOS semiconductor devices also have the following characteristics: Second. This embodiment can be applied similarly to the third embodiment. The difference between this embodiment and the third embodiment is that the material embedded in the U groove 31a is silicon carbide 235. [0034] In this embodiment, the heat dissipation effect of the side surface of the semiconductor element is further improved compared to the third embodiment. [0035] FIG. 11 is a schematic cross-sectional view for explaining a fifth embodiment of the present invention. This figure shows a state before formation of bipolar elements in a bipolar semiconductor device. MOS semiconductor devices also have the following characteristics: Second. Third. Similar to the fourth embodiment, this embodiment can be applied. In this embodiment, the U groove 31
Polycrystalline silicon 234 is embedded within a. Furthermore, a silicon carbide substrate 202 is used as the substrate. Therefore, the silicon oxide film 20 in the third and fourth embodiments
There is no restriction on the film thickness related to the dielectric constant for 4. Although it is preferable to make the silicon oxide film 204 thinner from the viewpoint of heat dissipation effect, only the thickness required for pasting the silicon single crystal layer is necessary. Silicon oxide film 204
The film thickness is preferably about 0.05 to 0.1 μm. In this embodiment, the first. Second. Third. Compared to the fourth embodiment, the heat dissipation effect at the bottom surface of the semiconductor element is improved, and the parasitic capacitance at the bottom surface of the semiconductor element is also reduced. [0036] FIG. 12 is a schematic cross-sectional view for explaining a sixth embodiment of the present invention. This figure shows a state before formation of bipolar elements in a bipolar semiconductor device. Also in MOS semiconductor devices, the first. Second. Third. 4th. This embodiment can be applied similarly to the fifth embodiment. The difference between this embodiment and the fifth embodiment is that the material embedded in the U groove 31a is silicon carbide 235. In this example, compared to the fifth example, the heat dissipation effect on the side surface of the semiconductor element is improved, and the parasitic capacitance on the side surface of the semiconductor element is also reduced. [0037]

【Effect of the invention】

In the semiconductor device of the present invention, by adopting the structure as explained above, a layer with low thermal conductivity does not exist between the buried object inside the U-groove and the substrate, and the heat emitted from the semiconductor element in the semiconductor device is reduced. Heat is radiated to the substrate via the U-groove. As a result, the heat dissipation effect is improved by the BESOI structure.
This is an improvement over conventional semiconductor devices having trench-structured isolation regions. Even if the heat dissipation effect remains below this level compared to a semiconductor device having an ordinary U-groove structure insulation isolation region,
Due to the effect of reducing parasitic capacitance in the semiconductor device of the present invention, the speed-power product is improved compared to a semiconductor device having an ordinary U-groove structure insulating isolation region. Furthermore, with regard to soft error resistance, by employing the BESOI structure, the semiconductor device of the present invention is improved over a semiconductor device having an ordinary U-groove structure insulating isolation region. [0038] When the present invention is applied to a bipolar semiconductor device, the above-mentioned effects can be obtained. - On the other hand, when the present invention is applied to a MOS semiconductor device, MOS semiconductor elements are further miniaturized, and the gate length becomes, for example, about 0.1 to 0.25 μm.
If the operating speed approaches IGHz and the operating temperature is about liquid nitrogen temperature, the effectiveness of the present invention will be greatly increased.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view for explaining a first embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view for explaining the first embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view for explaining the first embodiment of the present invention.

5 is a schematic plan view for explaining the first embodiment of the present invention, and is a schematic plan view of FIG. 4. FIG.

FIG. 6 is a graph showing the temperature rise of the semiconductor device with respect to the collector current for explaining the effects of the first embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view for explaining an example in which the second embodiment of the present invention is applied to a bipolar semiconductor device.

FIG. 8 is a schematic cross-sectional view for explaining an example in which the second embodiment of the present invention is applied to a MOS semiconductor device.

FIG. 9 is a schematic cross-sectional view for explaining a third embodiment of the present invention.

FIG. 101 is a schematic cross-sectional view for explaining a fourth embodiment of the present invention. FIG. 11 is a schematic cross-sectional view for explaining a fifth embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view for explaining a sixth embodiment of the present invention.

FIG. 13 is a schematic cross-sectional view for explaining a semiconductor device having a conventional SOI structure and a U-groove structure.

[Explanation of symbols]

01.201 Silicon substrate 03.203 Silicon oxide film 12.212 Buried layer 13.213 Silicon epitaxial film 31.2
31, 231a U groove 32 Sidewall insulating film 34.234 Polycrystalline silicon 41.241 N type region 42.242 Base region 43.243 Emitter region 48 Surface protective film 51.251 Collector electrode 52.252 Base electrode 153° 253 Emitter electrode Schottky electrodeSilicon carbide substrateSilicon oxide filmSilicon carbide filmSilicon single crystal substrateP-wellN-wellSilicon oxide filmSilicon nitride filmSilicon oxide filmSilicon carbidegate insulation filmGate electrodeN-type source/drain regionP-type source/drain regionSilicon oxide membrane metal wiring

【Document name】

drawing

[Figure 1] 1) Open +3-290948 (18)

[Figure 2] '49 Kaiboshi 3-2210: MW (ZU)

[Figure 3]

[Figure 4]

[Figure 5]

[Figure 6]

[Figure 7]

[Figure 8]

[Figure 9] 231a fart Go to 231 fart

Claims (27)

[Claims] 1. A substrate having a silicon oxide film on its surface, a silicon single crystal layer formed on the substrate via the silicon oxide film, and a U-shaped silicon layer extending from the surface of the silicon single crystal layer to the substrate. A groove, a sidewall insulating film provided on the side wall surface of the U-shaped groove, and a buried object embedded inside the U-shaped groove via the sidewall insulating film. Semiconductor equipment. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a bipolar semiconductor device. 3. The semiconductor device according to claim 1, wherein the semiconductor device is a MOS semiconductor device. 4. The semiconductor device according to claim 1, wherein the substrate is a silicon substrate. 5. The semiconductor device according to claim 4, wherein the semiconductor device is a bipolar semiconductor device. 6. The semiconductor device according to claim 4, wherein the semiconductor device is a MOS semiconductor device. 7. The semiconductor device according to claim 4, wherein the buried material is polycrystalline silicon. 8. The semiconductor device according to claim 7, wherein the semiconductor device is a bipolar semiconductor device. 9. The semiconductor device according to claim 7, wherein the semiconductor device is a MOS semiconductor device. 10. The semiconductor device according to claim 4, wherein the buried material is silicon carbide. 11. The semiconductor device according to claim 10, wherein the semiconductor device is a bipolar semiconductor device. 12. The semiconductor device according to claim 10, wherein the semiconductor device is a MOS semiconductor device. 13. The silicon oxide film has a thickness that is thinner than the difference between the depth at which the U-shaped groove can be formed and the thickness of the silicon single crystal layer, and thicker than the sidewall insulating film. 8. The semiconductor device according to claim 7. 14. The semiconductor device according to claim 13, wherein the semiconductor device is a bipolar semiconductor device. 15. The semiconductor device according to claim 13, wherein the semiconductor device is a MOS semiconductor device. 16. The silicon oxide film is thinner than the difference between the depth at which the U-shaped groove can be formed and the thickness of the silicon single crystal layer, and is thicker than the sidewall insulating film. The semiconductor device according to claim 10. 17. The semiconductor device according to claim 16, wherein the semiconductor device is a bipolar semiconductor device. 18. The semiconductor device according to claim 16, wherein the semiconductor device is a MOS semiconductor device. 19. The semiconductor device according to claim 1, wherein the substrate is a silicon carbide substrate. 20. The semiconductor device according to claim 19, wherein the semiconductor device is a bipolar semiconductor device. 21. The semiconductor device according to claim 19, wherein the semiconductor device is a MOS semiconductor device. 22. The semiconductor device according to claim 19, wherein the buried material is polycrystalline silicon. 23. The semiconductor device according to claim 22, wherein the semiconductor device is a bipolar semiconductor device. 24. The semiconductor device according to claim 22, wherein the semiconductor device is a MOS semiconductor device. 25. The semiconductor device according to claim 19, wherein the buried material is silicon carbide. 26. The semiconductor device according to claim 25, wherein the semiconductor device is a bipolar semiconductor device. 27. The semiconductor device according to claim 25, wherein the semiconductor device is a MOS semiconductor device.