JPH03283879A - Memory drive circuit - Google Patents

Abstract

PURPOSE:To vary the output position of a slave picture by resetting a circuit when a first synchronizing signal is activated by changing the pulse width of the signal and a control pulse is outputted, starting the count of a second synchronizing signal when the first synchronizing signal is inactivated, and outputting a third synchronizing signal when a count value arrives at a preset value. CONSTITUTION:A NAND circuit 3 passes a horizontal synchronizing signal while a vertical synchronizing signal is set at an L level, and the filp-flops DF0, DF1-DFn of a counter 4 are reset by the trailing edge of the vertical synchronizing signal, and counts up the horizontal synchronizing signal, and a constant setting circuit 5 sets all the output terminals at H levels when the output state of the counter 4 is set at a state set in advance. An AND circuit 6 sets the output terminal 7 at the H level when all the output terminals of the constant setting circuit 5 are set at the H levels, and sets the starting position in the vertical direction of the slave picture. Also, the horizontal synchronizing signal whose pulse width is changed is applied to an input terminal 11, and the start position in a horizontal direction can be set by this circuit. In such a way, the output position of the slave picture can be varied.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to memory for TV images, etc.
The present invention relates to a circuit for driving an image memory for a child screen having a function of displaying a parent screen and a child screen called in-picture.

[Conventional technology]

First, the basic configuration of a conventionally used picture-in-picture memory will be explained.

Picture-in-picture is a system that combines two TV screens into one screen as a parent screen and a child screen.It has an image memory that stores compressed data for the child screen, and the child screen written to this memory By reading screen data synchronously when the main screen is displayed, a second TV can be displayed as part of the main screen.
This allows the screen to be displayed as a child screen.

FIG. 3 is a block diagram showing the structure of a conventional picture-in-picture memory of this type.

A field memory 32 is an image memory located behind the picture-in-picture memory and stores one field of compressed data for a child screen.

Buffer memory 31 located before field memory 32
Since the field memory 32 becomes write-prohibited 1 when the field memory 32 is read, this is to store 1H worth of data so that the child screen data sent during that time will not be lost.

Writing/reading of the field memory 32 is asynchronous, and the writing of the field memory 32 is synchronized with the child screen signal, but the reading of the field memory 32 is synchronized with the parent screen.

Next, the data compression method will be explained horizontally and vertically.

In the horizontal direction, the data is compressed to 1/n by increasing the read speed by n times compared to the write speed. If writing is performed at 6MH2 of the signal generator 35 and reading is performed at 18MHz of the signal generator 36, the image will be 1/3
It will be compressed into.

In the vertical direction, the data is compressed to 1/n by extracting one tree from n lines of data or by averaging it. For example, in the averaging process, if three lines of data are averaged and combined into one line, the data will be compressed to 173.

The counter is broadly divided into an address counter for supplying addresses to the buffer memory and field memory, a setting for the writing start position of all field signals for the sub screen, and a start position for sub screen output of all field signals for the main screen. There are two ways to set the counter.

As with normal general-purpose memory, the address counter receives the sub-screen video signal write start signal and sub-screen output start signal, and when the sub-screen output starts, the memory write/read operation starts and the address counter An address is generated.

Also, set the start position of writing the video signal for the sub screen.

The counter for setting the child screen output start position will be described below.

The counter for setting the start of writing when writing data to the picture-in-picture memory among the video signals for the small screen will be explained separately in the horizontal and vertical directions using FIG.

First, in the horizontal direction, assuming a horizontal synchronization signal with an active Trubel, the video signal starts approximately 10 μs after the rise of the horizontal synchronization signal, so it is necessary to input data into the picture-in-picture memory. When entering, at least 10u after the horizontal synchronization signal rises.
C
Wear.

In the case of this picture-in-picture memory, the sixth
As shown in the figure, the counter is configured with a flip-flop, and the counter is reset by the one-shot pulse output at the rising edge of the horizontal synchronization signal for the sub-screen, and the writing system is controlled in synchronization with the sub-screen signal. The counter is incremented by a clock signal output from, for example, a 6MH7 oscillation circuit in the picture-in-view memory.

When the counter output reaches the preset value, A
All the inputs of the ND circuit are torubels, and the output of the AND circuit, which is the small screen video signal writing start signal, is torubel.

Assuming a vertical synchronization signal with an active Trubel in the vertical direction, approximately 208 seconds after the rise of the vertical synchronization signal.
Since the video signal starts after the vertical synchronization signal rises, the data is written in the image memory after the video signal starts at least 20 hours after the vertical synchronization signal rises.

In this case, the writing start position is set by configuring a counter using a flip-flop, similar to the horizontal direction, and resetting the counter with a one-shot pulse output at the rising edge of the vertical synchronization signal, and using the horizontal synchronization signal for the sub-screen. Increment. Then, when the output of the counter reaches a preset value, the output of the AND circuit, which is the small screen video signal reading start signal, becomes a torque signal.

When both the horizontal and vertical sub-screen video signal writing start signals become true, the sub-screen video signal is written to the picture-in-picture memory.

Timing diagrams when horizontal and vertical synchronizing signals are input are shown in FIGS. 7 and 8.

Next, the output start position when outputting the child screen to the parent screen will be explained separately in the horizontal and vertical directions, similar to the setting of the video signal leakage start position for the child screen.

FIG. 5 shows the relationship between the main screen signal and the child screen output position.

The output of the child screen is synchronized with the main screen signal, and in the horizontal direction, after the horizontal synchronization signal for the main screen rises, the child screen output starts several μs after the main screen starts displaying. ing.

The output start position setting of the child screen in the picture-in-picture memory has a counter with the same configuration as the writing start position setting of the video signal for the child screen, and the one-shot A picture signal t11 that resets the counter with a pulse and controls the reading system of the child screen data synchronized with the main screen signal.
The counter is incremented by a clock signal output from an oscillation circuit of, for example, 18 MHz in the in-picture memory.

When the output of the counter reaches a preset value, the output of the AND circuit, which is a small screen output start signal, becomes H level.

In the vertical direction as well, after the vertical synchronization signal for the main screen rises and after several hours have passed since the main screen display starts, the output of the sub screen starts, so a counter with the same configuration as the horizontal counter is used in this case as well. I am using it. This counter is reset by a one-shot pulse output at the rising edge of the main screen vertical synchronization signal, and incremented by the main screen horizontal synchronization signal. When the value of the counter reaches a preset value, the output of the AND circuit, which is a small screen output start signal, becomes H level.

When both the horizontal and vertical sub-screen output start signals become H level, output of the sub-screen to the main screen is started.

As described above, in the conventional memory drive circuit, the horizontal and vertical counters for setting the write start position for the sub-screen and the horizontal and vertical counters for setting the output start position for the sub-screen are all stored in the picture-in-picture memory. Reset by a one shot pulse generated. Conventionally, the pulse width of this one-shot pulse was fixed, so the output of the AND circuit, which is the writing start signal of the sub-screen video signal and the sub-screen output start signal, is always at the same timing after the rise of the horizontal and vertical synchronizing signals. It was H level. As a result, it is not possible to change the writing area of the sub-screen video signal and the output position of the sub-screen.

[Problem to be solved by the invention]

The conventional memory drive circuit described above resets the counter with a one-shot pulse output at the rising edge of the horizontal and vertical synchronization signals, so when outputting the sub screen to the write area of the sub screen video signal and the main screen. The disadvantage is that it is impossible to change the output position of the child screen.

It is an object of the present invention to provide a memory driving circuit free from the above-mentioned drawbacks.

[Means to solve the problem]

The memory driving circuit of the present invention has the following features: 1. A memory driving circuit for driving an image memory for a child screen into which a child screen to be drawn and inserted into a parent screen is written or read in synchronization with a second synchronization signal, the memory driving circuit being configured to use a first synchronization signal. a variable pulse width circuit that outputs a control pulse by changing the pulse width of the control pulse; a counter that is reset when the control pulse becomes active and starts counting a second synchronization signal when the control pulse becomes inactive; The synchronization signal output circuit outputs a third synchronization signal when the count result of the counter reaches a preset count value.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are block diagrams showing a first embodiment of the memory driving circuit of the present invention;
, (b) are for setting the vertical and horizontal starting positions of the child screen, respectively.

A vertical synchronizing signal with a varied pulse width is applied to the input terminal 1 of FIG. 1(a), and a horizontal synchronizing signal is applied to the input terminal 2. The NAND circuit 3 allows the horizontal synchronization signal to pass while the vertical synchronization signal is at a low level (hereinafter referred to as low level). Counter 4 is a D-type flip-flop DFo,
Each flip-flop DFo is composed of DF+, .about., DFn.

DF1 to DFn are reset at the rising edge of the vertical synchronizing signal, and count up the horizontal synchronizing signal that passes through the lint circuit 3 and comes in at 1. Constant setting circuit 5 is counter 4
When the output state reaches a preset state, all output terminals are set to high level (hereinafter referred to as H level).

When the output terminals of the constant setting circuit 5 all reach the L level, the AND circuit 6 sets the output terminal 7 to the H level and sets the vertical start position of the sub-screen. Therefore, writing and reading of the child screen is jittered downward by the sum of the period during which the vertical synchronizing signal is at the 1-level and the period during which the counter 4 counts the number set by the constant setting circuit 5.

A horizontal synchronizing signal with a varied pulse width is applied to the input terminal 11 in FIG. 1(b), and a clock signal is applied to the input terminal 12. The contents of the subsequent stage include the number of bits in the counter 14, the number of settings in the constant setting circuit 15, and the AND circuit 16.
This circuit is the same as the circuit shown in FIG. 1(a) except that the number of inputs is different, so a description thereof will be omitted. This circuit sets the horizontal starting position.

FIG. 2 is a block diagram showing a second embodiment of the invention. (In this figure, the horizontal synchronizing signal is indicated by 0 to simplify the drawing).

Only the output of the vertical synchronization signal for the child screen will be explained.

A horizontal synchronizing signal is applied to the input terminal 21, and the input terminal 2
2 is applied with a vertical synchronizing signal whose pulse width is changed. The counter 24 is reset and does not count while the vertical synchronization signal is active, and counts up the horizontal synchronization signal when the vertical synchronization signal becomes ink active. When the counter 24 reaches a predetermined set value, the constant setting circuit 25 sets all outputs to the H level, and outputs an H level pulse to the output terminal 27 via the AND circuit 26. The movement of the starting position of the child screen due to this is the same as that in the embodiment shown in FIG. 1, so a description thereof will be omitted.

This embodiment has an advantage over the first embodiment in that the NAND circuit can be omitted.

In addition, 1. Although the pulse width is changed in the second embodiment, the circuit for implementing this change is well known, so a description thereof will be omitted.

〔Effect of the invention〕

As explained above, in the present invention, the standard f-screen start position can be changed by changing the preset count value, and furthermore, by simply varying the width of the first synchronization signal, the sub-screen image can be This has the advantage that the signal writing area and the output position for the child screen when combining the main screen and the child screen can be easily varied.

[Brief explanation of the drawing]

1(a) and 1(b) are block diagrams showing a first embodiment of the memory driving circuit of the present invention, and FIG. 2 is a block diagram showing a second embodiment of the present invention. Figure 3 is a block diagram showing a conventional picture-in-picture memory, Figure 4 is a diagram showing the relationship between all field signals of the child screen and the write area, and Figure 5 is the relationship between all field signals of the parent screen and the child screen output. FIG. 6 is a block diagram showing a conventional example, and FIGS. 7 and 8 are tanning charts showing the conventional counter reset operation. 1.2,11. ．． 12,21.22...Input terminal, 3
．． 13... NAND circuit, 4.14.24... Counter, 5.15.25... Constant setting circuit, 6.16.26... AND circuit, 7.17.27... Output terminal . Patent issuer Nippon Den'y Ko; Shikisha

Claims (1)

[Claims] 1. A memory drive for driving an image memory for a child screen in which a child screen drawn in synchronization with the first and second synchronization signals and inserted into the parent screen is written or read. a variable pulse width circuit that outputs a control pulse by changing the pulse width of a first synchronizing signal; and a variable pulse width circuit that outputs a control pulse by changing the pulse width of a first synchronizing signal; A memory driving circuit comprising a counter that starts counting synchronization signals, and a synchronization signal output circuit that outputs a third synchronization signal when the count result of the counter reaches a preset count value.