JPS60166983A - Animation display circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a graphic processing device, and particularly to a moving image display circuit suitable for displaying moving images.

[Background of the invention]

Conventionally, when displaying a moving image on a graphic processing device using a raster scan type CRT, there are n image memories vertically,
A method has been used in which the image is subdivided into n square areas horizontally, and each area is sequentially displayed while being zoomed n times. This was done by periodically rewriting the X-direction origin register and Y-direction origin register, which indicate which part of the image memory is to be zoomed, but in conventional methods, The origin address cannot be changed and the screen flickers, the processor has to constantly rewrite the origin register, it becomes impossible to execute other processes while the video is being displayed, and there are interruptions from input devices, etc. This has the disadvantage that it is no longer possible to stop the video.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention has been made to solve the above-mentioned drawbacks, and it is possible to smoothly switch screens and to perform other processing without occupying the processor while displaying a video. The purpose of the present invention is to provide a display circuit.

[Summary of the invention]

In order to achieve the above object, the present invention is characterized by providing a frame counter that counts up at the timing of switching frames of a moving image, and having a circuit that creates an origin address from the output of this frame counter and a magnification register. shall be.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1, 2, and 3. FIG. 1 shows an example of the configuration of a moving image display circuit according to the present invention.6 In FIG. Magnification register to hold, 10
2 is a frame counter that holds the frame number; 103 is an origin memory that creates a display start point; 104 is a timing generator; 105 is an address counter for display in the Y direction; and 106 is an address counter for display in the X direction. , 107
is an image memory, 108 is a parallel/serial conversion circuit (
PSC), 109 is a raster scan type CRT. As an example of the explanation of this circuit, A, as shown in Fig. 3,
With the image information of B, C, and D stored in the image memory 107, ABCD is displayed while performing double zoom display.
The operation of cyclically displaying a video and displaying a video will be explained.

First, in the case of a zoom magnification of 1x, that is, a display without zooming,
The register 101 receives a signal from the processor 100, 111
The value O is set via 0.

(The magnification register holds the value obtained by subtracting 1 from the zoom magnification.) The output from the magnification register 101 and the output from the frame counter 102 are added to the origin memory 103 as an address via the signal line 111. be done.

The contents of the origin memory 103 are as shown in FIG. 2, and when the magnification is 0, that is, from address 0 to address 3, the value of Yo is used as the signal for the Y origin, regardless of the output of the frame counter 102. On line 113, set Xo as the X origin.
The value of is always output to the signal line 114. The output signal line 113 is set as an initial value in the Y direction display counter 105 by the vertical retrace signal 118 output from the timing generator 104, and the signal line 114 is set as an initial value in the Y direction display counter 105 by the vertical retrace signal 118 output from the timing generator JO4. The signal 119 sets the X direction display counter 106 as an initial value. This fi, in synchronization with the raster scanning of the CRT 109, the signal line 122 performs a countdown in the Y direction.
3 is used to count up in the X direction.

Image data indicated by the address of the display counter is read from the image memory 107 via the signal m120, and is sent to the CRT 109 via the parallel/serial conversion circuit 108 at the display clock indicated by the signal line 117. In this way, the image shown in FIG. 3 will be displayed on the CRT 109 until a new value is set in the magnification register 101.

Next, double zoom display is performed and the ^[lCD
When displaying cyclically, the value 1 is set in the magnification register 101 from the processor 100 via the signal line 110. If the content of the frame counter 102 is O in this state, the output from the magnification register 101 and the output from the frame counter 102 are connected to the origin via the signal line 111.
It is added to the memory 103 as an address. Signal line 11
3 and Xo shown at address 4 in FIG. is set as an initial value in the X-direction display counter.

Further, the output from the magnification register 101 is added to the timing generator 104 via a signal line 112, and a clock obtained by dividing the pixel display clock without zooming by the zoom magnification is connected to the signal line 117. A clock obtained by dividing the count down clock of the Y direction display counter by the zoom magnification is output to 122, and a clock obtained by dividing the count up clock of the X direction display counter by the zoom magnification is output to the signal line 123. . As a result, the image shown by A in FIG. 3 is displayed on the entire screen of the CRT 109. After this state continues for a while, timing generator 1
A signal line 116 for counting up the frame counter 102 is output from 04.

(Normally, video display is performed at approximately 12 frames per second, so a current up signal is output to the signal line 116 at intervals of 1/12 seconds.) This signal causes the frame counter 1 to
02 changes from the value O to the value 1, and the data Y, , X, is output to the signal lines 113 and 114, and the values y, , x, are output to the display counters 105 and 106 as the initial values by the signal lines 118 and 119. Set. As a result, the image shown by B in FIG. 3 is displayed on the entire screen of the CRT 109. Similarly, each time a count-up signal is output to the signal line 116, the CRT 109 displays C, D, A, etc. shown in FIG.
B is displayed continuously and video display becomes possible.

〔Effect of the invention〕

As explained above, according to the present invention, since the origin address can be changed at once, flickering does not occur on the screen, and after setting data in the magnification register, the processor can execute other processing, such as This has the effect that it is also possible to stop displaying a moving image by an interrupt from an input device.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a moving image display circuit of the present invention, FIG. 2 is a diagram showing the contents of an origin memory, and FIG. 3 is a diagram showing an example of images stored in the image memory.

Claims (1)

[Claims] In a graphic processing device that performs image display by dividing an image memory into a plurality of areas and sequentially displaying each area while zooming, there is a frame counter that counts frames at the timing of switching frames of a video, and - A video display circuit characterized by comprising an origin address creation circuit that creates a zoom start address from the output of a counter and the output of a magnification register that holds a zoom magnification.