JPH03282626A - Interruption selection system - Google Patents

Abstract

PURPOSE:To evade the interruption of the working of a microprocessor owing to a manual switching action by permitting or inhibiting the interruption requir ing signal received from a peripheral circuit of the microprocessor based on an address signal. CONSTITUTION:An interruption selection circuit is provided with an address bus 1, an address decoder 10, the AND circuits 20 and 40, and an S-R flip-flop circuit (S-RF/F) 30. Then it is possible to permit or inhibit an interruption signal 7 received from a peripheral circuit of a microprocessor with programming of only an address. Thus, the interruption of working of the microprocessor by the manual switching operation can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt selection method for selecting whether to permit or disable an interrupt request signal from a peripheral circuit of a microprocessor.

[Conventional technology]

Conventionally, this type of interrupt selection method has been configured to be manually switched using a switch or using a pin header or a sector pull.

[Problem to be solved by the invention]

The above-mentioned conventional interrupt selection method has a configuration in which switching is performed manually, and therefore has the drawback that the operation of the microprocessor is temporarily interrupted.

[Means to solve the problem]

The interrupt selection method of the present invention includes an address decoding circuit that receives an address signal from a microprocessor;
A flip-flop circuit receives a set signal and a reset signal outputted from the address decoding circuit as input signals, a set/reset signal outputted from the flip-flop circuit, and an interrupt request signal from a peripheral circuit of the microprocessor. The interrupt selection circuit includes an AND circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing an example of the operation of the embodiment shown in FIG.

In FIG. 1, this embodiment has an address code circuit ii+810 which inputs an address signal from a microprocessor (not shown) via an address passco, a reset signal 3 from an address decode circuit 1o, and an external reset signal 4. An AND circuit 2o that outputs a reset AND signal 5 by AND, and an S-R79717071 circuit (hereinafter referred to as 5-RF/F) whose input signals are the set signal 2 from the address decode circuit 10 and the reset AND signal 5. ) 30, and an AND circuit 40 that outputs a microprocessor input interrupt request signal 8 which is an AND signal of the peripheral circuit interrupt signal 7 of the microprocessor and the set and reset signals 6 from the 5-RF/F 30. It is configured with an interrupt selection circuit consisting of:

Next, the operation of this embodiment will be explained using FIG. 1 and FIG. 2 together.

Address lever 1 to circuit 1 with address bus 1 as input
The set signal 2 from 0 changes from ``1'' to ``O'' and is input to the S-R flip-flop circuit 3o. At this time, the set/reset signal output from the S-R flip-flop circuit 30 Signal 6 outputs ]'.ANDD'ii'!4-0 with set/reset I/signal 6 as input The processor input interrupt request signal becomes 8, and interrupt requests from peripheral circuits are permitted.

tfZ, the reset signal 3 from the address decoding circuit 10 inputting the address bus 1 is the external reset signal 4.
(For example, a reset signal output from the CR integration circuit)
When changes from 1°' to 0'', the reset AND signal 5 output from the AND circuit 2o changes from ``I'' to ``o''.
", and is input to the flip-flop circuit 30 (the set output signal 2 is normally "1").

At this time, the set/reset signal 6 output from the S-R flip-flop circuit 30 outputs "o". When the AND circuit 4o that receives the set/reset signal 6 inputs the set/reset signal 6 '0', the peripheral circuit interrupt request signal 7 is logically ignored, and the microprocessor input interrupt request signal 8 becomes '0'. “, and interrupt requests from peripheral circuits are not permitted.

〔Effect of the invention〕

As explained above, the present invention includes an address decoding circuit that receives an address signal from a microprocessor;
A flip-flop circuit receives the set I signal and reset signal output from the address decoding circuit as input signals, and the set/reset signal output from the flip-flop circuit and the interrupt request signal from the peripheral circuit of the microprocessor. By having an interrupt selection circuit comprising a power product circuit as an input, it is possible to enable an interrupt request signal from a peripheral circuit of the microprocessor;
Since the selection of whether or not permission is to be granted can be made by programming only the address, it is possible to eliminate the temporary interruption of microprocessor operation caused by manual switching as in the past.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing an example of the operation of the embodiment shown in FIG. 1. A) Reshus, 2. Set signal, 3. Reset signal, 4. External reset signal, 5. Reset AND signal, 6. Set/reset signal, 7.
Peripheral circuit interrupt request signal, 8...Microprocessor input interrupt request signal, 1-0...Address decode circuit, 20...AND circuit, 30...S-R79
717071 circuit<5-4F/F), 40...AND circuit.

Claims (1)

[Claims] an address decode circuit that receives an address signal from a microprocessor; a flip-flop circuit that receives a set signal and a reset signal output from the address decode circuit; and a set/reset signal output from the flip-flop circuit. and an AND circuit that receives as input an interrupt request signal from a peripheral circuit of the microprocessor,
An interrupt selection method characterized in that control of whether to permit or disable an interrupt request signal from the peripheral circuit is performed using an address signal.