JPH0328070B2 - - Google Patents
Info
- Publication number
- JPH0328070B2 JPH0328070B2 JP56047447A JP4744781A JPH0328070B2 JP H0328070 B2 JPH0328070 B2 JP H0328070B2 JP 56047447 A JP56047447 A JP 56047447A JP 4744781 A JP4744781 A JP 4744781A JP H0328070 B2 JPH0328070 B2 JP H0328070B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- glass layer
- forming
- conductivity type
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000011521 glass Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 235000019353 potassium silicate Nutrition 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 claims description 3
- 238000002955 isolation Methods 0.000 description 16
- 238000000034 method Methods 0.000 description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 3
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 235000011118 potassium hydroxide Nutrition 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法、特にバイポー
ラ形半導体素子の素子形成領域形成方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an element forming region of a bipolar semiconductor element.
半導体集積回路（IC）では共通基板上に多く
のトランジスタ等の回路素子を形成するが、これ
らの各素子が相互に電気的な影響を受けないよう
に分離絶縁させるためのアイソレーシヨン帯領域
が設けられている。第１図に示す断面図は、最も
多用されているpn接合分離法で、例えばＰ型シ
リコン基板１上にｎ型エピタキシヤル層２を積層
し、アイソレーシヨン帯領域３にｐ型不純物を拡
散してｐ型領域とするが、図はバイポーラ形半導
体素子を形成する場合で、予めｎ型埋没拡散層４
を形成した後、ｎ型エピタキシヤル層２を成長
し、アイソレーシヨン帯領域３を設けている。こ
の様なPn接合分離法の他に、アイソレーシヨン
帯領域を異方性エツチングによつてエツチング除
去し、薄い酸化シリコン（SiO2）膜を介して多
結晶シリコンを埋め込む絶縁分離法などもある
が、これらのアイソレーシヨン帯領域の形成法は
何れもその巾を余り狭くすることは困難であつ
て、第１図に示している様にアイソレーシヨン帯
の巾Ｌは素子形成領域の深さＤに依存し、深さＤ
が大きくなると巾Ｌは広くなる。これは熱拡散又
は異方性エツチングなどによつて形成すると止む
なく巾広くなるもので、この様なアイソレーシヨ
ン巾がICの高集積化を妨げる原因となつている。
特にバイポーラ形高耐圧半導体素子を形成する場
合には、ベース巾やコレクタ領域を拡げる必要か
ら素子形成領域を深くしなければならず、そのた
めICが大型化することは避けられない問題であ
る。 In semiconductor integrated circuits (ICs), many circuit elements such as transistors are formed on a common substrate, but isolation band regions are used to separate and insulate these elements so that they are not affected electrically by each other. It is provided. The cross-sectional view shown in FIG. 1 shows the most commonly used p-n junction isolation method. The figure shows a case where a bipolar type semiconductor element is formed, and an n-type buried diffusion layer 4 is formed in advance.
After forming, an n-type epitaxial layer 2 is grown and an isolation band region 3 is provided. In addition to this Pn junction isolation method, there is also an insulation isolation method in which the isolation band region is removed by anisotropic etching and polycrystalline silicon is buried through a thin silicon oxide (SiO 2 ) film. However, in any of these methods of forming the isolation band region, it is difficult to make the width very narrow, and as shown in Figure 1, the width L of the isolation band is determined by the depth of the element formation region. Depth D
As becomes larger, the width L becomes wider. If this is formed by thermal diffusion or anisotropic etching, the width will inevitably increase, and such isolation width is a cause of hindering high integration of ICs.
Particularly when forming a bipolar type high-voltage semiconductor element, it is necessary to increase the base width and collector region, so the element formation region must be deepened, which inevitably increases the size of the IC.
本発明はかような問題点を解消して、バイポー
ラ形半導体素子からなるICを高密度化すること
を目的とし、その特徴は一導電型シリコン基板上
に保護膜を形成し、該保護膜をパターンニングし
て、素子形成領域を窓あけする工程、次いで異方
性エツチングによつて、窓あけした露出部のシリ
コン基板をエツチングして凹部を形成する工程、
次いで反対導電型不純物を含有する液状のガラス
層を該凹部の底面には厚く、それ以外の底面には
薄く塗布する工程、次いで熱処理を施してガラス
層を硬化する工程、次いでエツチングを施し、該
薄く形成されたガラス層を除去して該凹部の底面
にガラス層を残す工程、次いで高温加熱処理を施
し、該ガラス層中の不純物を拡散して埋没拡散層
を形成する工程、次いで該ガラス層を除去した
後、その反対導電型エピタキシヤル層を積層成長
せしめて、該エピタキシヤル層を素子形成領域と
する工程を含むことを特徴とする製造方法を提案
するもので、以下図面を参照して実施例によつて
詳細に説明する。 The present invention aims to solve these problems and increase the density of ICs made of bipolar semiconductor elements.The present invention is characterized by forming a protective film on a silicon substrate of one conductivity type, and a step of patterning and opening a window in the element formation region; then a step of etching the exposed portion of the silicon substrate in the window by anisotropic etching to form a recess;
Next, a liquid glass layer containing impurities of the opposite conductivity type is applied thickly to the bottom of the recess and thinly to the other bottoms, then heat treatment is applied to harden the glass layer, and then etching is performed to form the glass layer. A step of removing the thinly formed glass layer to leave the glass layer on the bottom of the recess, followed by a step of applying high temperature heat treatment to diffuse impurities in the glass layer to form a buried diffusion layer, and then a step of forming a buried diffusion layer in the glass layer. The present invention proposes a manufacturing method characterized by including a step of removing an epitaxial layer and then growing an epitaxial layer of the opposite conductivity type to use the epitaxial layer as an element formation region. This will be explained in detail by way of examples.
第２図ないし第８図は本発明による一実施例の
工程順図を示しており、先づ第２図に示すように
面指数（100）をもつたＰ型シリコン基板１上に
膜厚数100ÅのSiO2膜５と膜厚1000〜2000Å程度
の窒化シリコン（Si3N4）膜６とを形成する。次
いで、第３図に示すようにフオトプロセスによつ
てフオトレジスト膜パターン（図示せず）を形成
し、これをマスクとして素子形成領域上のSi3N4
膜６とSiO2膜５とをエツチング除去して、シリ
コン基板１の素子形成領域を露出させる。 FIGS. 2 to 8 show a process sequence diagram of an embodiment according to the present invention. First, as shown in FIG. A SiO 2 film 5 with a thickness of 100 Å and a silicon nitride (Si 3 N 4 ) film 6 with a thickness of about 1000 to 2000 Å are formed. Next, as shown in FIG. 3, a photoresist film pattern (not shown) is formed by a photo process, and using this as a mask, Si 3 N 4 on the element formation region is formed.
The film 6 and the SiO 2 film 5 are removed by etching to expose the element formation region of the silicon substrate 1.
次いで、フオトレジスト膜を除去した後、第４
図に示すように数10℃に加熱した苛性カリ
（KOH）とイソプロピルアルコールとの混合液
で、シリコン基板１の露出部をエツチングして、
エツチング深さを約2μｍとする。この様にすれ
ば側面は（111）面が現われる異方性エツチング
がなされて、図示のように梯形状に形成される。
次いで第５図に示すようにスピンオングラス７を
スピンナーを使用して塗布する。スピンオングラ
スは有機系の液体ガラスで、本実施例ではそれに
砒素又はアンチモニーを多量に含有させておく
が、暫時1000℃位で熱処理すれば、有機質が蒸発
して、砒素又はアンチモニーを含んだSiO2膜と
なる。 Next, after removing the photoresist film, the fourth
As shown in the figure, the exposed portion of the silicon substrate 1 is etched with a mixture of caustic potash (KOH) and isopropyl alcohol heated to several tens of degrees Celsius.
The etching depth is approximately 2 μm. In this way, the side surfaces are anisotropically etched to reveal (111) planes, forming a ladder shape as shown in the figure.
Next, as shown in FIG. 5, spin-on glass 7 is applied using a spinner. Spin-on glass is an organic liquid glass, and in this example, it contains a large amount of arsenic or antimony, but if it is heat-treated at about 1000°C for a while, the organic matter evaporates and it becomes SiO 2 containing arsenic or antimony. It becomes a membrane.
次いで、稀弗酸でエツチングとすると、スピン
オングラスは底面に厚く、且つ傾斜のある側面に
はうすく被着しているので、側面のみエツチング
除去し、底面には厚さ1000〜2000Å程度残存させ
ることができる。そして、1200〜1250℃、30〜60
分間熱処理すれば第６図に示すようにｎ型埋没拡
散層８が形成される。この様な埋没拡散層はバイ
ポーラ形半導体素子のコレクタ抵抗を低くするた
め、必ず形成されているるものである。次いで、
スピンオングラス層７を弗酸でエツチング除去し
た後、第７図に示すように気相成長を行ない、成
長膜厚は2μｍ以上とする。反応ガスはジクロル
シラン（HiH2cl2）にフオスフイン（PH3）を混
合したガスを用いて、ｎ型層とするが、エツチン
グされたシリコン基板１上はエピタキシヤル単結
晶層９が成長し、Si3N4膜６上に被着したシリコ
ン層１０は多結晶となる。 Next, when etching with dilute hydrofluoric acid, the spin-on glass is thick on the bottom and thinly adheres to the sloped sides, so only the sides are etched away, leaving a thickness of about 1000 to 2000 Å on the bottom. Can be done. and 1200~1250℃, 30~60
After heat treatment for a minute, an n-type buried diffusion layer 8 is formed as shown in FIG. Such a buried diffusion layer is always formed in order to lower the collector resistance of a bipolar semiconductor element. Then,
After removing the spin-on glass layer 7 by etching with hydrofluoric acid, vapor phase growth is performed as shown in FIG. 7, and the thickness of the grown film is 2 μm or more. The reaction gas is a mixture of dichlorosilane (HiH 2 cl 2 ) and phosphine (PH 3 ) to form an n-type layer, but an epitaxial single crystal layer 9 grows on the etched silicon substrate 1, and the Si The silicon layer 10 deposited on the 3N4 film 6 becomes polycrystalline.
次いで第８図に示すように高湿高温度で熱処理
して、多結晶シリコン層１０を酸化せしめた後、
弗酸でエツチングする。この場合、熱処理すると
多結晶シリコン層１０の酸化は速く、単結晶層９
の酸化は遅いので、多結晶シリコン層１０を全部
酸化せしめても、単結晶層９の酸化量は少ない。
従つて、比較的平坦な表面がえられ、以下は公知
の製造方法によつてｎ型エピタキシヤル単結晶層
９にバイポーラ形半導体素子を形成することがで
きる。 Next, as shown in FIG. 8, the polycrystalline silicon layer 10 is oxidized by heat treatment at high humidity and high temperature.
Etch with hydrofluoric acid. In this case, the heat treatment oxidizes the polycrystalline silicon layer 10 quickly, and the single crystal layer 9
oxidation is slow, so even if the entire polycrystalline silicon layer 10 is oxidized, the amount of oxidation of the single crystal layer 9 is small.
Therefore, a relatively flat surface is obtained, and a bipolar semiconductor element can then be formed in the n-type epitaxial single crystal layer 9 by a known manufacturing method.
この様に、本発明はpn接合分離法の一種であ
るが、上記のごとくしてｎ型エピタキシヤル単結
晶層９からなる素子形成領域を形成すれば、アイ
ソレーシヨン帯の巾Ｌは素子形成領域の深さＤと
は無関係になつて、巾Ｌはフオトプロセスによつ
SiO2膜５をパターンニングすることが可能な最
小限度の巾にすることができる。したがつて、例
えばアイソレーシヨンの巾を1μｍあるいはそれ
以下にすることも可能であり、アイソレーシヨン
面積を極めて小さくして、ICの集積度を向上さ
せることができる。又、本発明の形成方法は従来
のpn接合分離法と比べて、ｎ型埋没拡散層８の
ためのフオトプロセスによるパターンニングを必
要としないから、それだけ工程が簡略化される利
点もある。 As described above, the present invention is a type of pn junction isolation method, but if the device formation region consisting of the n-type epitaxial single crystal layer 9 is formed as described above, the width L of the isolation band is The width L is independent of the depth D of the region and depends on the photo process.
The SiO 2 film 5 can be made to have the minimum width possible for patterning. Therefore, it is possible to reduce the width of the isolation to, for example, 1 μm or less, making it possible to extremely reduce the isolation area and improve the degree of integration of the IC. Furthermore, compared to the conventional pn junction isolation method, the forming method of the present invention does not require patterning by photo process for the n-type buried diffusion layer 8, and therefore has the advantage of simplifying the process accordingly.
以上の実施例による説明から判るように、本発
明はICが高集積化される製造方法で、特にバイ
ポーラ形高耐圧素子を含むICに有効であり、IC
の高速化、周波数特性など特性改善に著しく寄与
するものである。なお、上記実施列にあつてはｐ
型シリコン基板とする場合で説明したが、ｎ型シ
リコン基板とする場合も同様に適用できることは
言うまでもない。 As can be seen from the above description of the embodiments, the present invention is a manufacturing method for highly integrated ICs, and is particularly effective for ICs including bipolar high voltage elements.
This significantly contributes to improvements in characteristics such as speeding up and frequency characteristics. In addition, in the case of the above implementation sequence, p
Although the description has been made regarding the case where an n-type silicon substrate is used, it goes without saying that the present invention is similarly applicable to the case where an n-type silicon substrate is used.
第１図は従来のアイソレーシヨン帯領域を形成
した断面図、第２図ないし第８図は本発明の製造
工程順断面図である。図中、１はｐ型シリコン基
板、２，９はｎ型エピタキシヤル層、３はアイソ
レーシヨン帯領域、４，８はn+型埋没拡散層、
５はSiO2膜、６はSi3N4膜、７はスピンオングラ
ス（液体ガラス）、１０は多結晶シリコン層を示
している。
FIG. 1 is a cross-sectional view of a conventional isolation band region, and FIGS. 2 to 8 are cross-sectional views of the manufacturing process according to the present invention. In the figure, 1 is a p-type silicon substrate, 2 and 9 are n-type epitaxial layers, 3 is an isolation band region, 4 and 8 are n + type buried diffusion layers,
5 is a SiO 2 film, 6 is a Si 3 N 4 film, 7 is a spin-on glass (liquid glass), and 10 is a polycrystalline silicon layer.
Claims (1)
該保護膜をパターンニングして、素子形成領域を
窓あけする工程、次いで異方性エツチングによつ
て窓あけした露出部のシリコン基板をエツチング
して凹部を形成する工程、次いで反対導電型不純
物を含有する液状のガラス層を、該凹部の底面に
は厚く、それ以外の領域には薄く塗布する工程、
次いで熱処理を施して該ガラス層を硬化する工
程、次いでエツチングを施し、該薄く形成された
ガラス層を除去して該凹部の底面にガラス層を残
す工程、次いで高温熱処理を施し、該ガラス層中
の反対導電型不純物を拡散して埋没拡散層を形成
する工程、次いで、該ガラス層を除去した後、そ
の上面に反対導電型のエピタキシヤル層を積層成
長せしめて、該エピタキシヤル層を素子形成領域
とする工程を含むことを特徴とする半導体装置の
製造方法。1 Forming a protective film on a silicon substrate of one conductivity type,
A step of patterning the protective film to open a window in the element formation region, then a step of etching the exposed portion of the silicon substrate exposed through the window by anisotropic etching to form a recess, and then adding an impurity of the opposite conductivity type. a step of applying a liquid glass layer containing the liquid glass thickly to the bottom surface of the recess and thinly to the other areas;
Next, heat treatment is performed to harden the glass layer, etching is performed to remove the thinly formed glass layer to leave the glass layer on the bottom of the recess, and then high temperature heat treatment is performed to harden the glass layer. Step of diffusing impurities of the opposite conductivity type to form a buried diffusion layer; Next, after removing the glass layer, growing an epitaxial layer of the opposite conductivity type on the upper surface thereof, and forming the epitaxial layer into a device. 1. A method of manufacturing a semiconductor device, comprising a step of forming a region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4744781A JPS57162456A (en) | 1981-03-31 | 1981-03-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4744781A JPS57162456A (en) | 1981-03-31 | 1981-03-31 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57162456A JPS57162456A (en) | 1982-10-06 |
| JPH0328070B2 true JPH0328070B2 (en) | 1991-04-17 |
Family
ID=12775393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4744781A Granted JPS57162456A (en) | 1981-03-31 | 1981-03-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57162456A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5057590A (en) * | 1973-09-20 | 1975-05-20 | ||
| JPS51134082A (en) * | 1975-05-15 | 1976-11-20 | Iwatsu Electric Co Ltd | Method to manufacture the semiconductor unit |
| JPS5295985A (en) * | 1976-02-09 | 1977-08-12 | Hitachi Ltd | Manufacture of semiconductor unit |
| JPS55154746A (en) * | 1979-05-22 | 1980-12-02 | Semiconductor Res Found | Manufacture of semiconductor integrated circuit device |
-
1981
- 1981-03-31 JP JP4744781A patent/JPS57162456A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5057590A (en) * | 1973-09-20 | 1975-05-20 | ||
| JPS51134082A (en) * | 1975-05-15 | 1976-11-20 | Iwatsu Electric Co Ltd | Method to manufacture the semiconductor unit |
| JPS5295985A (en) * | 1976-02-09 | 1977-08-12 | Hitachi Ltd | Manufacture of semiconductor unit |
| JPS55154746A (en) * | 1979-05-22 | 1980-12-02 | Semiconductor Res Found | Manufacture of semiconductor integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57162456A (en) | 1982-10-06 |
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