JPH03280298A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To increase the capacity of a capacitor even if impressed voltage is small and to stably drive a sense amplifier by providing the semiconductor memory with a capacitor constituted of a MOS transistor (TR) itself. CONSTITUTION:When the sense amplifier 3 is not driven, charging switches 71, 72 are turned on and driving switches 81, 82 and restoring switches 91, 92 are turned off. Under this condition, the capacitor 3 is charged. Thereby, a word line is raised, data appear on bit lines 101, 102, the switches 81, 82 are turned on, and then the switches 71, 72, 91, 92 are turned off. Thus, the sense amplifier 3 is driven. Since a well area 50 in which the gate electrodes of a capacitor 4 are opposed to each other the inverse of a N type, an air lacking layer is not formed on the surface of the well area 50 and the capacity of the capacitor 4 can be held at a large stage.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a complementary sense amblifier (hereinafter referred to as "
Regarding a semiconductor memory device having a "amplifier"), more specifically, changes in ground potential and power supply potential that occur when a complementary sense amplifier is driven <Prior art> Semiconductor memory device that drives a large number of complementary sense amplifiers simultaneously In devices, common mode noise may occur in the surroundings due to fluctuations in the power supply potential and ground potential. In order to reduce such common mode noise, the present applicant has recently proposed a semiconductor memory device having a sense amplifier drive system as shown in FIG. 6 (Japanese Patent Application No. 332263/1982).
. The sense amplifier drive system of this semiconductor memory device includes a capacitor 34, a complementary sense amplifier 33, and a switch 31.
and a switch 32.

When the complementary sense amplifier 33 is not operated, the switches 31, 32 are controlled to switch the pull-up transistor drive lines 41, . While each of the pull-down transistor drive lines 42 is brought into a non-conductive (oven) state, the line 21 at the same potential as the power supply (hereinafter referred to as "power supply line") and the first terminal 35 of the capacitor 34 are brought into conduction; A line 22 having the same potential as the ground line (hereinafter referred to as "ground line") and the second terminal 36 of the capacitor 34 are brought into conduction to charge the capacitor 34. When driving the complementary sense amplifier 33, the switches 31 and 32 are controlled to connect the power supply line 21 and the pull-up transistor drive line 41. While the ground line 22 and the pull-down transistor drive line 42 are rendered non-conductive, the pull-up transistor drive line 41 and the first terminal 35 . The pull-down transistor drive line 42 and the second terminal 36 of the capacitor 34 are brought into conduction, respectively.
The first and second terminals 35°36 of the capacitor 34
It is driven by the potential difference between. In this way, the complementary sense amplifier 3 and the power supply line 11. By driving the ground line 12 while being electrically separated from each other, potential fluctuations in the power supply line 11 and the ground line 12 are prevented, and common mode noise is reduced.

The capacitor 34 is composed of a gate electrode (first) of a MOS transistor and a second gate electrode provided on the first gate electrode with an insulating film between the eyebrows interposed therebetween. Alternatively, as shown in FIG. 5, it is composed of a MOS transistor itself. This MOS transistor has N-type source regions 37 . It consists of a drain region 38 and a gate electrode 39 facing the substrate surface 40a between these regions 37, 38 with an oxide film 43 interposed therebetween.

<Problems to be Solved by the Invention> Incidentally, the capacitor 34 in the sense amplifier drive system requires a considerable capacity in order to stably drive a large number of complementary sense amplifiers at the same time.

Therefore, the first gate electrode and the second gate electrode of the MOS transistor
When configured with a gate electrode, the interlayer insulating film is formed thickly, resulting in a problem that the electrode area becomes enormous. Furthermore, in the case of constructing the transistor itself (MOS), the gate oxide film is formed thinly, so a considerable capacitance can be formed in a small area. It will depend on the surface condition of the substrate surface 40a) of the mold. That is, when the voltage applied between the first and second terminals 35 and 36 reaches a value of about the threshold value (usually 0.7 V) of the MOS l-transistor, the surface of the channel region becomes depleted and the capacitance becomes extremely small. For this reason,
There is a problem in that the amount of accumulated charge becomes extremely small, making it impossible to drive the sense amplifier stably.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device which is equipped with a capacitor composed of MOS transistors to drive a large number of complementary sense amplifiers, thereby reducing fluctuations in power supply potential and ground potential. Another object of the present invention is to provide a semiconductor memory device in which the capacitance of a capacitor can be increased and the amount of charge can be increased even when an applied voltage is small, and a sense amplifier can therefore be driven stably.

<Means for Solving the Problems> In order to achieve the above object, the present invention connects a capacitor between a pull-up transistor drive line connected to a power supply and a pull-down transistor drive line connected to ground, and In a semiconductor memory device that reduces fluctuations in power supply potential and ground potential that occur when a complementary sense amplifier is driven by a transistor drive line and a pull-down transistor drive line, the capacitor is formed on the surface of an N-type well region. It is characterized by comprising an N-type source region and a drain region connected to each other by wiring, and a gate electrode facing the surface of the well region between the source region and the drain region with an insulating film interposed therebetween.

Further, in the present invention, a capacitor is connected between a pull-up transistor drive line connected to a power supply and a pull-down transistor drive line connected to ground, and a complementary sense amplifier is constructed by the pull-up transistor drive line and the pull-down transistor drive line. In a semiconductor memory device designed to reduce fluctuations in power supply potential and ground potential that occur during driving, the capacitors are formed on the surface of an N-type well region, connected to each other by wiring, and at the same potential as the well region. It is characterized by consisting of a P-type source region and a drain region connected by wiring so that the gate electrode faces the surface of the well region between the source region and the drain region with an insulating film interposed therebetween.

Function> The capacitor is formed on the surface of an N-type well region, and includes an N-type source region and a drain region connected to each other by wiring, and a gate facing the well region surface between the source region and the drain region with an insulating film interposed therebetween. Since the well region facing the gate electrode is of N type, the voltage that causes an inversion layer to form on the surface of the well region (hereinafter referred to as "inversion voltage") is negative. Therefore, when the voltage applied to the gate electrode is zero or positive with respect to the surfaces of the source region, drain region, and well region, a depletion layer is not formed on the surface of the well region, and compared to the conventional case, a depletion layer is not formed on the surface of the well region. The capacitance of the capacitor is kept large. In other words, the capacitance is kept large not only when the applied voltage is large but also when it is small. Therefore, the amount of accumulated charge increases, and a large number of sense amplifiers can be stably driven.

Further, the capacitor is formed on the surface of the N-type well region, and the source region and the drain region are connected to each other by wiring and are connected to each other by wiring so as to have the same potential as the well region, and the source region, When the well region surface between the drain regions is composed of a gate electrode facing the surface of the well region with an insulating film interposed therebetween, the inversion voltage on the well region surface becomes negative, as in the case described above. Therefore, in exactly the same way, the capacitance is kept large not only when the applied voltage is large but also when it is small. Therefore, the amount of accumulated charge increases, and a large number of sense amplifiers can be stably driven. Note that this capacitor 4 has the same configuration as a P-channel MOS (MOS) transistor in a general complementary semiconductor device except for wiring. Therefore, it can be easily manufactured with only slight design changes.

<Example> Hereinafter, this invention will be explained in detail with reference to Examples.

FIGS. 1 and 2 each show a block configuration and a single-path configuration of a complementary sense amplifier drive system of a dynamic semiconductor memory device according to an embodiment. As shown in FIG. 1, this sense amplifier drive system includes a capacitor 4 having a first terminal 61 and a second terminal 62, and a sense amplifier 3 connected to a pull-up transistor drive line 51 and a pull-down transistor drive line 52. , a first switch l capable of electrically connecting the first terminal 61 of the capacitor 4 and the power line 11 or the pull-up transistor drive line 5I, and the second terminal 62 of the capacitor 4 and the ground line 12 or the pull-down transistor. A second switch 2 that can be electrically connected to the drive line 52 is provided.

As shown in FIG. 2, the first switch 1 includes a power line 11
and the first terminal 61 of the capacitor 4
Charging switch 7 consisting of a channel MOS) transistor
1, and a drive switch 72 made of a P-channel transistor connected between the first terminal 61 and the pull-up transistor drive line 51. on the other hand,
The second switch 2 includes a charging switch 72 made of an N-channel transistor connected between the ground line 12 and the second terminal 62 of the capacitor 4;
2 and the pull-down transistor drive line 52.
It is composed of 2.

Note that 91 and 92 are P-channel transistors, respectively.
This is a restore switch consisting of an N-channel transistor.

As shown in FIG. 3, the capacitor 4 is made of a MOS transistor and is formed in an N-type well region 50 provided on the surface of a P-type semiconductor substrate IO. This capacitor 4 includes a P+ type source region 67 and a drain region 68, an insulating film 13, a gate electrode 69, and an N+
Mold contact areas 65 and 66 are provided. The gate electrode 69 faces the source region 67, the drain region 68, and the well region surface 60a between these regions with the insulating film 13 in between. The gate electrode 69 is the first terminal 6
1 is connected by wiring. Further, the source region 67, the drain region 68, and the contact regions 65 and 66 are all connected to the second terminal 62 by wiring. Therefore, source region 67 and drain region 68 are at the same potential as well region 50 via contact regions 65 and 66.

This sense amplifier drive system operates as follows.

When the sense amplifier 3 is not operated, the charging signal line 17
1,172 to turn on the charging switches 71, 72, while driving signal lines 181.
182 and restore signal lines 191 and 192 to turn off both the drive switch 81.82 and the restore switch 91.92. In this state, the capacitor 3 is charged. Then, the word line (not shown) rises, and the data is transferred to the bit line 101°1.
02, the drive signal line 181.182 gives a signal to turn on the drive switch 81.82, while the charging signal line 171.172 and the restore signal line 191.192 turn it off. The charging switch 71.72 and the restoring switch 91.92 are both turned off. This drives the sense amplifier 3 mentioned above. At this time, the sense amplifier 3
Since the power supply line 11 and the ground line 12 are electrically separated by the charging switch 71.72 and the restore switch 91.92, the sense amplifier 3
Even if the power supply line 11 and the ground line 12 are driven, the potentials of the power supply line 11 and the ground line 12 are not affected by it.

Therefore, common mode noise can be reduced.

Here, since the well region 50 facing the gate electrode 69 of the capacitor 4 is of N- type, the well region surface 5
The inversion voltage of 0a is negative.

On the other hand, as shown in FIG. 2, the gate electrode 69 is connected to the first terminal 61 on the power line 11 side, and the source region 67, drain region 68 and well region surface 50a are connected to the second terminal on the ground line 12 side. The voltage applied to the gate electrode 69 is zero to positive with respect to the well region surface 50a. therefore,
In this case, no depletion layer is formed on the well region surface 50a, and the capacitance of the capacitor 4 is kept larger than in the conventional case. That is, the capacitance can be kept large not only when the applied voltage is large but also when it is small.

Therefore, the amount of accumulated charge can be increased, and as a result, a large number of sense amplifiers 3 can be stably driven. Therefore, fluctuations in the power supply potential and ground potential can be efficiently suppressed, and the effect of reducing common mode noise can be enhanced. Moreover, as shown in FIG. 3, this capacitor 4 has the same structure as a P-channel MOS transistor in a general complementary semiconductor device except for the wiring. Therefore, it can be easily manufactured by making slight design changes.

Further, instead of the capacitor 4, a capacitor 5 may be provided as shown in FIG. This capacitor 5 is
Like capacitor 4, it consists of a MOS transistor,
It is formed in the N-type well region 50 on the surface of the P-type semiconductor substrate 10. It also includes an N+ type source region 63 and drain region 64, an insulating film 13, and a gate electrode 69. The gate electrode 69 is connected to the first terminal 61 by wiring, while the source region 63 . drain region 6
4 are both connected to the second terminal 62 by wiring. In this capacitor 5, like the capacitor 4, the inversion voltage at the well region surface 50a is negative. therefore,
Just like the capacitor 4, the capacitance can be maintained large not only when the applied voltage is large but also when it is small. Therefore, the amount of accumulated charge can be increased, a large number of sense amplifiers 3 can be stably driven, and common mode noise can be effectively reduced. Moreover, the structure can be made simpler than that of the capacitor 4.

<Effects of the Invention> As is clear from the above, in the semiconductor memory device of the present invention, a sense amplifier driving system capacitor is formed on the surface of an N-type well region, and an N-type source region and a drain region are connected to each other by wiring. , consists of a gate electrode facing the surface of the well region between the source region and the drain region with an insulating film interposed therebetween, so that the capacitance of the capacitor can be kept large even when the applied voltage is small, thus increasing the amount of stored charge. It is possible to stably drive a large number of sense amplifiers.

Further, a sense amplifier drive system capacitor is formed on the surface of the N-type well region, and is connected to each other by wiring, and a P-type source region and a drain region which are connected to each other by wiring so as to have the same potential as the well region. The above source area,
When the well region surface between the drain regions is composed of gate electrodes facing each other with an insulating film interposed therebetween, a large number of sense amplifiers can be stably driven in the same way. Moreover, the above capacitor is a P-channel MO of a general complementary semiconductor device.
9) Can be easily manufactured by making slight design changes to the transistor.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a sense amplifier drive system of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the sense amplifier drive system, and FIG. 4 is a sectional view showing a capacitor in the sense amplifier drive system, FIG. 5 is a sectional view showing a capacitor in the sense amplifier drive system of a conventional semiconductor memory device, and FIG. 6 is a sectional view of a capacitor in the sense amplifier drive system of a conventional semiconductor memory device. It is a block diagram showing a drive system. 1...First switch, 2...Second switch, 3
... Complementary sense amplifier, 4, 5... Capacitor,
IO...P- type semiconductor substrate, 11... Power line,
12...Ground line, 50...N-type well, 5
DESCRIPTION OF SYMBOLS 1... Pull-up transistor drive line, 52... Pull-down transistor drive line, 61... First terminal,
62...Second terminal, 63.67...Source region, 64.68...Drain region, 65.66...Contact region, 69...Gate electrode, 71.72...For charging Switch, 81.82... Drive switch, 91.92... Restoration switch, 171 79.
,,immI=sa-m181.182...Drive line signal line, 191.192...Restore signal line.

Claims (2)

[Claims] (1) When a capacitor is connected between a pull-up transistor drive line connected to a power supply and a pull-down transistor drive line connected to ground, and a complementary sense amplifier is driven by the pull-up transistor drive line and pull-down transistor drive line. In a semiconductor memory device designed to reduce fluctuations in power supply potential and ground potential occurring in
1. A semiconductor memory device comprising an N-type source region and a drain region connected to each other by wiring, and a gate electrode facing a surface of a well region between the source region and the drain region with an insulating film interposed therebetween. (2) When a capacitor is connected between the pull-up transistor drive line connected to the power supply and the pull-down transistor drive line connected to the ground, and the complementary sense amplifier is driven by the pull-up transistor drive line and the pull-down transistor drive line. In a semiconductor memory device designed to reduce fluctuations in power supply potential and ground potential occurring in
A P-type source region and a drain region connected to each other by wiring and having the same potential as the well region, and facing the surface of the well region between the source region and the drain region with an insulating film interposed therebetween. A semiconductor memory device comprising a gate electrode.