JP2000349251A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a nonvolatile function by which polarization can be surely generated by applying to a ferroelectric substance capacity an electric field larger than the coercive electric field, the destruction of a gate insulation film be also prevented, and a high voltage is sufficiently applied to a gate electrode, even by electric charge which generate polarization. SOLUTION: This semiconductor device is composed of a ferroelectric capacitor 101, in which a ferroelectric is sandwiched between two electrodes and a field effect transistor 103 and is provided with a paraelectric capacitor 100, of which one electrode is connected with connection point (point indicated by a symbol Vg) between a gate electrode 102 of a field effect transistor 103 and the electrode of a ferroelectric capacity 101, while the gate electrode 102 of the field effect transistor 103 is connected with one electrode of the ferroelectric capacitor 101. A value of a paraelectric capacity C2 is set almost the same or larger than that of a ferroelectric capacitor C1 and is much larger than that of a gate capacitor C3 of the field effect transistor 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used as an active element having a nonvolatile function and having a structure in which a ferroelectric capacitor is connected to a gate electrode of a field effect transistor.

[0002]

2. Description of the Related Art An active element having a non-volatile function having a structure in which a ferroelectric capacitor and a gate electrode of a MIS field effect transistor (hereinafter, referred to as MISFET) are joined is disclosed in, for example, JP-A-9-205181. Some are described. FIG. 7 is a circuit diagram of the above-mentioned conventional example.
A structure in which the gate electrode (102) of the FET (103) and one electrode of the ferroelectric capacitor (101) are connected, and the gate capacitance value (C3) and the ferroelectric capacitor (101) are connected in series. You are. The feature is that the gate electrode area is larger than the electrode area of the ferroelectric capacitor.

In the above conventional example, the MISFET (103) of the two electrodes of the ferroelectric capacitor (101) is used.
When a voltage is applied between the electrode that is not connected to the gate electrode (102) and the source region, the drain region or the silicon substrate of the MISFET (103), the ratio of the ferroelectric capacitance to the gate capacitance is reversed. A proportional divided voltage is applied to each capacitor, and the ferroelectric is polarized. The threshold voltage of the MISFET changes as charges are attracted or repelled to the surface of the Si substrate depending on the polarization direction, and the storage state can be read by detecting a change in current between the source and the drain. After the polarization, the residual polarization remains even if the applied voltage V is removed, and the threshold voltage remains changed, so that a nonvolatile memory can be configured.

Since the ferroelectric has a large dielectric constant, the ferroelectric capacitance (C1) is much larger than the gate capacitance (C3) if the area is almost the same, and most of the applied voltage is the gate capacitance. , And the voltage applied to the ferroelectric decreases, so that sufficient polarization characteristics cannot be obtained. Further, if the voltage applied to the gate capacitance becomes too large, the gate insulating film may be broken. However, in the above conventional example, since the area of the gate electrode is made larger than the area of the ferroelectric capacitor, the capacitance difference becomes relatively small, and the voltage applied to the ferroelectric can be increased. Therefore, the polarization increases and the amount of change in the charge increases.

[0005]

As the area of the gate electrode becomes larger than the area of the ferroelectric capacitor, a larger voltage can be applied to the ferroelectric substance. However, the charge generated by the polarization spreads over a wider gate electrode. As a result, the charge density in the channel portion is reduced. This is nothing less than a small voltage applied to the gate electrode, and a change in the threshold voltage of the MISFET is also small, so that it is difficult to determine the storage.
In addition, there is a problem that reading errors due to noise are likely to occur. In addition, when the thickness of the ferroelectric capacitor, the electrode area, the thickness of the gate insulator, and the area of the gate electrode are set so that the maximum electric field applied to the ferroelectric is equal to or higher than the coercive electric field, the thickness relation is once. If the conditions are determined, it is difficult to change the setting, so that the gate area is adjusted with respect to the electrode area, and there is a problem that the degree of freedom in circuit design is reduced. When rewriting the memory, that is, when reversing the polarization, consider disconnecting the back gate of the MISFET from the power supply, preparing a negative power supply and applying a negative voltage to the ferroelectric electrode, or using It is necessary to prepare a high voltage source. In any case, there is a problem that the configuration becomes complicated when the storage element, the control circuit, and the power supply circuit are formed on the same substrate. Further, when junction separation is used, an F channel forming a channel of the same type as the minority carrier of the substrate is formed.
In ET, since it is impossible to separate the back gate electrode from the substrate potential, a memory cannot be formed by an N-channel FET on a P-type substrate and a P-channel FET on an N-type substrate. Complementary FET memories are necessary to easily configure a logic circuit with an FET memory, but for the above reasons, to form a complementary FET memory on the same substrate, a dielectric isolation or SOI substrate must be used. Since it must be used, there is a problem that the structure is complicated and expensive.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and it is possible to cause polarization by applying a sufficiently large electric field larger than a coercive electric field to a ferroelectric capacitor and to perform gate insulation. Prevent the destruction of the membrane, and
It is an object of the present invention to provide a semiconductor device which can apply a sufficiently large voltage to a gate electrode even with charge due to polarization and has a nonvolatile function with a simple structure.

[0007]

In order to achieve the above object, the present invention is configured as described in the appended claims. That is, according to the first aspect of the present invention, a paraelectric capacitor having one electrode connected to a connection point between the gate electrode of the field effect transistor and the electrode of the ferroelectric capacitor is provided. The value of the paraelectric capacitance is set to be substantially equal to or larger than the value of the ferroelectric capacitance, and sufficiently larger than the gate capacitance of the field-effect transistor. Note that “sufficiently large” means, for example, about 10 times or more, as described in detail later.

According to a third aspect of the present invention, assuming that the value of the ferroelectric capacitor is C1, the value of the paraelectric capacitor is C2, and the voltage at which the coercive electric field for polarizing the ferroelectric capacitor is Vp is Vp. V = Vp · (C1 +
C2) / means for applying a voltage of C2, and 2 V
The values of C1 and C2 are set so that C1 / (C1 + C2) is larger than the threshold voltage of the field effect transistor.

Since the voltage is applied to the paraelectric capacitor connected in series with the ferroelectric capacitor as described above, the gate electrode of the field effect transistor is not used for rewriting the memory. To generate a polarization by applying a sufficiently large electric field equal to or greater than the coercive electric field, and
Even if the area of the gate electrode is reduced, no abnormally high voltage is applied to the gate capacitance, and the gate insulating film does not break down. Since the area of the gate electrode can be reduced, a gate signal voltage larger than the threshold value can be applied even with charges due to polarization, so that a reading error due to noise hardly occurs. The claims 1 to 3 correspond to, for example, an embodiment shown in FIGS. 1 and 2 described later.

Further, in the invention according to claim 4,
V · (C1 + C2) / C2 is applied to the other electrode of the ferroelectric capacitor.
When a voltage of 0 is applied, a pulse voltage of a predetermined width is generated at a voltage of 0. When a voltage of 0 is applied to the electrode of the ferroelectric capacitor, a pulse voltage of V · (C1 + C2) / C2 is applied. A means for generating a pulse voltage having a width and generating a voltage of V · (C1 + C2) when no pulse voltage is generated, and applying these voltages to the other electrode of the paraelectric capacitor is provided. . This configuration corresponds to, for example, an embodiment shown in FIG.

Further, in the invention according to claim 5,
Ferroelectric capacitors and paraelectric capacitors have the same capacitance value,
When a voltage of 2 V is applied to the other electrode of the ferroelectric capacitor, a voltage of V is applied to the other electrode of the paraelectric capacitor, and a voltage of -V is applied to the electrode of the ferroelectric capacitor. When the operation is performed, a means for applying a voltage of 0 to the other electrode of the paraelectric capacitor is provided. This configuration corresponds to, for example, an embodiment shown in FIG.

Further, in the invention according to claim 6,
Ferroelectric capacitors and paraelectric capacitors have the same capacitance value,
In addition, a voltage of 3 V or-is applied to the other electrode of the ferroelectric capacitor.
A voltage V is applied, and the other electrode of the paraelectric capacitor is provided with means for constantly applying the voltage V.
This configuration corresponds to, for example, an embodiment shown in FIG.

[0013]

According to the present invention, since a large voltage for applying a coercive electric field to the ferroelectric capacitor can be applied, the ferroelectric capacitor can be sufficiently polarized. Further, since a gate signal voltage higher than the threshold value is applied to the gate electrode of the field effect transistor, a read error due to noise is less likely to occur. Also, since the gate electrode of the field-effect transistor is not used for rewriting the memory, an abnormally high voltage is not applied to the gate capacitance even if the gate electrode is reduced, and the gate oxide film may cause dielectric breakdown. There is no. Further, since the gate capacitance value can be set without being affected by the ferroelectric capacitance value, the degree of freedom in design does not decrease.
Further, the voltage applied at the time of memory rewriting may be a single power supply of + V, 0, and a high voltage or a negative voltage is not used, so that the circuit configuration is simple. In addition, when a voltage is applied to the ferroelectric for rewriting the memory, a voltage is applied between the ferroelectric capacitor electrode and the paraelectric capacitor electrode, so that the back gate voltage of the field effect transistor is manipulated. It is not necessary to apply a pulse of the opposite voltage to the electrode of the paraelectric capacitor only when the voltage applied to the electrode of the ferroelectric capacitor changes. Complexity can be avoided. In addition, since the electrode for applying a voltage for polarizing the ferroelectric capacitor can be formed separately from the back gate electrode of the field effect transistor, the complementary field effect transistor memory can be formed on the same substrate even when junction separation is used. Can be configured. That is, since it is not necessary to use a dielectric isolation or an SOI substrate, a logic circuit with a field-effect transistor memory can be formed at low cost.

According to a fifth aspect of the present invention, in addition to the above-described effects, a signal voltage is continuously applied to the gate of the field effect transistor even when data is rewritten. Therefore, the operation of the field effect transistor is not hindered, and the operation can be performed without being conscious of rewriting the memory.

According to the sixth aspect, in addition to the effect of the fifth aspect, since the configuration is such that a constant voltage is applied to V2, a mechanism for switching the voltage of V2 is unnecessary, and the configuration is simple. The effect is obtained.

[0016]

FIG. 1 is a circuit diagram showing a basic configuration of the present invention. The circuit of FIG. 1 includes a ferroelectric capacitor (101) having a ferroelectric material sandwiched between two electrodes, a field effect transistor (103), and a field effect transistor (10).
3) Gate electrode (102) and ferroelectric capacitor (101)
And a paraelectric capacitor (100) having one electrode connected to a connection point (point Vg) with the electrode.

The capacitance value (C2) of the paraelectric capacitance (100)
Is equal to or greater than (equal to or slightly larger than) the capacitance value (C1) of the ferroelectric capacitor (101), and is sufficiently larger than the capacitance value (C3) of the gate electrode of the field effect transistor (103) (for example, about 10 times). Above).

In the above circuit, the paraelectric capacitor (10
0) is grounded and a voltage V is applied to the other electrode (104) of the ferroelectric capacitor (101), the voltage V becomes equal to the ferroelectric capacitor (101) and the paraelectric capacitor (101). 100) is applied to the series circuit. Initially, assuming that the ferroelectric is not polarized and the paraelectric capacitor (100) has no charge, most of the applied voltage is applied to the ferroelectric capacitor (101) and the ferroelectric begins to polarize . The charges generated by the polarization are accumulated in the electrodes of the paraelectric capacitor (100), and the partial pressure of the paraelectric capacitor (100) gradually increases. Eventually, when the divided voltage becomes inversely proportional to the ratio of the respective capacitance values of the ferroelectric capacitor (101) and the paraelectric capacitor (100), an equilibrium state is established, and the polarization of the ferroelectric ends.

If the capacitance of the ferroelectric capacitor is (C1) and the capacitance of the paraelectric capacitor is (C2), the ferroelectric capacitor (1
01), a voltage of V · C1 / (C1 + C2) is applied to the paraelectric capacitor (100). If V is set so that the electric field due to the former voltage V · C2 / (C1 + C2) is higher than the coercive electric field, the polarization retention of the ferroelectric capacitor (101) is good, and the polarization decreases even when the applied voltage is removed. Few. For example, if the voltage that gives the coercive electric field is Vp = V · C2 / (C1 + C2), the applied voltage can be expressed as V = Vp · (C1 + C2) / C2. Assuming that the values of C1 and C2 are equal for simplicity, the partial pressure applied to the ferroelectric capacitor (101) is V / 2, and V may be set so that the electric field due to this becomes equal to or higher than the coercive electric field. Further, since the voltage applied to the paraelectric capacitor (100) is also about V / 2, there is no possibility that the gate insulating film will cause dielectric breakdown.

As described above, since a large voltage for applying a coercive electric field to the ferroelectric capacitor (101) can be applied, the ferroelectric capacitor (101) can be sufficiently polarized. The charge generated by this polarization is distributed to the paraelectric capacitance (100) and the gate capacitance of the field-effect transistor. The gate capacitance of the field-effect transistor is much smaller than the paraelectric capacitance (100) ( (For example, 1/10 or less), most of the charges are stored in the paraelectric capacitor (100). Depending on the direction of polarization, the paraelectric capacitance (100)
Is + V · C1 / (C1 + C2) or −V · C1 / (C1 + C2). Usually, the voltage of the electrode (105) at the other end of the paraelectric capacitor (100) is + V · C1 / (C1 + C2).
Since C1 / (C1 + C2), the voltage applied to the gate electrode (102) of the field effect transistor is + 2V ·
C1 / (C1 + C2) or 0. For this reason, a gate signal voltage larger than the threshold is applied to the gate electrode (102) of the field effect transistor, so that a reading error due to noise hardly occurs.

Next, the electrode (1) of the ferroelectric capacitor (101) is
04) is grounded and the electrode (10) of the paraelectric capacitor (100) is grounded.
When a voltage V is applied to 5), an opposite voltage is applied to the ferroelectric capacitor (101), so that the ferroelectric capacitor (101) undergoes reverse polarization. For the reasons described above, the voltages applied to the ferroelectric capacitor (101) and the paraelectric capacitor (100) have the same value but the opposite directions. In this way, the memory can be rewritten.

The relationship between the paraelectric capacitance (C2) and the gate capacitance (C3) is as follows. That is, as described above, the charge generated by the polarization is distributed to the paraelectric capacitance and the gate capacitance, so that the gate capacitance (C
The generated voltage fluctuates by the amount of the electric charge stored in 3). Therefore, the larger the ratio between the paraelectric capacitance value (C2) and the gate capacitance value (C3) is, the smaller the voltage fluctuation becomes.
To increase this ratio, it is necessary to increase the area of the paraelectric capacitor. For example, if (C3) is about 1/10 of (C2), the change in the generated voltage is also about 1/10. If the change in the voltage is about 1/10, it is considered that the influence on the others can be ignored. Further, a capacity ratio of 10 means that an insulating film (for example, Si
When both are formed by O ₂ ), the area of the paraelectric capacitor may be ten times as large as that of the gate electrode, and such an extent can be sufficiently realized. Therefore, it is desirable that the ratio between the paraelectric capacitance and the gate capacitance is large, but practically it is desirable that the ratio be about 10 times or more. If a material having a large dielectric constant is used as a dielectric forming the paraelectric capacitor, the area ratio can be further reduced.

The sizes of the paraelectric capacitor (100) and the ferroelectric capacitor (101) are set so that a sufficient voltage equal to or higher than the coercive electric field is applied to the ferroelectric capacitor (101). It is desirable that the paraelectric capacitance value (C2) is substantially equal to or larger than the ferroelectric capacitance value (C1).

Next, materials of the ferroelectric capacitor (101) and the paraelectric capacitor (100) will be described. The Bi-based layered compound (SrBi ₂ Ta ₂ O ₉ , Bi ₄ Ti ₃ O ₁₂ ) ferroelectric has a relative permittivity of about 200, and the relative permittivity of the Si oxide film is 3.9. 1000mm thick ferroelectric film, Si
Comparing the capacitance in the same area with the thickness of the oxide film being 100 °, the ferroelectric material is five times larger than the Si oxide film. That is, when the paraelectric capacitor (100) is constituted by the Si oxide film, the ferroelectric capacitor (101)
If the area is about five times as large as the above, the capacitance value becomes almost equal. This is sufficiently large in terms of feasibility. Also, instead of the Si oxide film, a high dielectric film (CeO, SrTiO ₃ , ZrO ₂ ,
When Y ₂ O ₃ or the like is used, the area of the paraelectric capacitor (100) can be reduced. Further, BST (BaxSr ₁ -xTi) is used as a high dielectric film forming a paraelectric capacitor.
If a material having a high relative dielectric constant (= 300) such as O ₃ is used, P having a higher relative dielectric constant as a ferroelectric material is used.
ZT (dielectric constant = 1000) can also be used.

As described above, according to the circuit shown in FIG. 1, the paraelectric capacitor (1) connected in series with the ferroelectric capacitor (101).
Since a voltage is applied to the ferroelectric capacitor (101), polarization is caused by applying a sufficiently large electric field larger than the coercive electric field to the ferroelectric capacitor (101) because the gate electrode of the field effect transistor is not used for rewriting the memory. Can do and
Even if the area of the gate electrode is reduced, no abnormally high voltage is applied to the gate capacitance, and the gate insulating film does not break down. Since the area of the gate electrode can be reduced, a gate signal voltage larger than the threshold value can be applied even with charges due to polarization, so that a reading error due to noise hardly occurs.

The voltage applied at the time of rewriting the memory may be a single power supply of V and 0 which is about the power supply voltage, and neither a high voltage nor a negative voltage is required.

Further, since the gate capacitance value of the field effect transistor can be set without being affected by the value of the ferroelectric capacitance,
The degree of freedom in design does not decrease.

Further, since an electrode to which a voltage for polarizing the ferroelectric capacitor is applied can be formed separately from the back gate electrode of the field effect transistor, ordinary junction separation can be performed without using an expensive SOI substrate. Since a memory can be formed by forming N-channel and P-channel complementary field-effect transistors on the same substrate, a logic circuit with a field-effect transistor memory can be simply and inexpensively formed. .

FIGS. 2A and 2B show a first embodiment of the present invention. FIG. 2A is a plan view and FIG. 2B is a sectional view. In FIG. 2, (1) is a Si substrate, a thick LOCOS oxide film (2) is formed on one surface, and a thin gate oxide film (3) is formed at two places between the LOCOS oxide films (2). ing. Below each gate oxide film (3) is a well region (4) of a diffusion layer with a low impurity concentration. On the surface of one well region (4), an electrode (5) of a dense diffusion layer made of impurities of a different type from that of the well region is formed. Further, a Poly-Si film (6) is continuously formed on the two gate oxide films (3) over the LOCOS oxide film (2). The Po1y-Si film (6) on one gate oxide film (3) is formed to be elongated,
It constitutes the gate electrode of the transistor. Electrode (5)
The upper Po1y-Si film (6) is formed so as to widely cover the gate oxide film (3). (7) is an interlayer insulating film which covers the LOCOS oxide film (2) and the Po1y-Si film (6), and fills the steps to flatten the surface. (8) is a vertical wiring, which electrically connects the Po1y-Si film (6) or the electrode (5) of the diffusion layer to the metal wiring (9) on the interlayer insulating film (7). Metal wire (9) is a laminate film such as, for example, Pt / IrO _2, the ferroelectric thin film thereon (10) is formed. An upper electrode (11) of Pt or the like is formed on the ferroelectric thin film (10).
(12) is a second interlayer insulating film which fills a step and flattens the surface. (13) is a metal wiring on the surface, which is electrically connected to the upper electrode (11) or the metal wiring (9) from the surface.

Next, a method of manufacturing the semiconductor device shown in FIG. 2 will be described. A well region (4) is formed by diffusion on one surface of a silicon semiconductor substrate (1), and a thick silicon oxide film (LOCOS) (2) is formed on the same surface while leaving a transistor region and a capacitor region. Impurity ions such as P and B are ion-implanted in the capacitor region to form an electrode (5) with a dense diffusion layer (this will be the lower electrode of the paraelectric capacitor (100)). A thin silicon oxide film (3) serving as a gate insulating film is formed on the surfaces of the transistor region and the capacitor region by thermal oxidation.

Next, a Poly-Si film (6) is formed,
The gate electrode and the upper electrode of the paraelectric capacitor are patterned by photolithography. Next, impurities such as P and B are ion-implanted into a transistor region other than the gate using the gate electrode as a mask to form a source region and a drain region of the field-effect transistor. A first interlayer insulating film (7) such as PSB is formed thereon to planarize the surface.

Next, Pol etching is performed by trench etching.
A contact hole to the y-Si electrode (6), an electrode (5) serving as a lower electrode of the paraelectric capacitor, and a source / drain region is opened, and the contact hole is formed into Po1y-S
The vertical wiring (8) is formed by back filling with i or metal.

Next, a Pt / IrO ₂ film is formed on the entire surface by sputtering deposition, a ferroelectric thin film (10) is deposited by a sol-gel method or the like, and sintered at 700 to 800 ° C. A Pt film is deposited thereon by sputtering, and the ferroelectric thin film and the Pt film thereon are simultaneously etched by ion milling to obtain a ferroelectric capacitor and its upper electrode (1).
Form 1).

Next, the Pt / IrO ₂ film is patterned so as to cover the upper part of the vertical wiring (8), thereby forming the lower electrode of the ferroelectric capacitor and the metal wiring (9). Next, PS
A second interlayer insulating film (12) of G or the like is formed to planarize the surface, and a contact hole is opened to the upper electrode (11) of the ferroelectric capacitor and the metal wiring (9).

Next, a metal film of aluminum or the like is sputtered on the surface and patterned to form wirings connected to the upper electrode (11) of the ferroelectric capacitor, the lower electrode of the paraelectric capacitor, and the source / drain electrodes. 13) is formed.

Next, the operation will be described with reference to the operation waveform diagram shown in FIG. 3 and FIG. However, for simplicity, the effect of depolarization due to polarization retention and the effect of gate capacitance will be ignored. One electrode of the ferroelectric capacitor (101) and the gate electrode (102) of the field effect transistor (103)
Vg is the voltage at the point where the capacitor is connected to one electrode of the paraelectric capacitor (100), V1 is the voltage applied to the other electrode (104) of the ferroelectric capacitor (101), and V1 is the voltage applied to the other electrode of the ferroelectric capacitor (101). The voltage applied to the other electrode (105) of (100) is V
Let it be 2. As the voltage V1 applied to the electrode (104),
Voltage signals of 0 and + V are applied with the same waveform as the signal applied to the gate electrode (102). A voltage of V · C1 / (C1 + C2) is normally applied to the electrode (105) as V2. When the voltage of V1 changes from 0 to + V (time t ₁ ), the value of V2 is 0 and a constant width. When a pulse voltage of τ is applied and the voltage of V1 changes from + V to 0 (time point t ₃ ), a pulse voltage of a constant width τ of + V is applied as V2. V1 = + V, when V2 = 0 (time _{t 1 ~t 2), V1-} V2 is + V, and the applied to this voltage ferroelectric capacitor (101) and the paraelectric capacitor (100), paraelectric The electrode of the capacitor (100) and the ferroelectric capacitor (1
01) and the voltage at the point (Vg) where the electrode is connected is V · C1
/ (C1 + C2).

Next, as V2, V · C1 / (C1 + C
A voltage of 2) and (time t ₂ ~t _3), the voltage at the point Vg becomes 2V · C1 / (C1 + C2 ) degree. As a result, the voltage applied to the ferroelectric capacitor (101) decreases, but the polarization remains, so that a charge corresponding to this residual polarization remains at the electrode of the paraelectric capacitor (100), and the voltage at the point Vg becomes Again, it is maintained at about 2V · C1 / (C1 + C2). The voltage at the point Vg is the gate voltage of the field-effect transistor (103). If 2V · C1 / (C1 + C2) is higher than the threshold voltage of the field-effect transistor, the field-effect transistor becomes a high input.

[0038] Conversely, when V1 = 0, V2 = + V ( time t ₃ ~t ₄₎ is, V1-V2 is -V, and the opposite voltage is applied to the ferroelectric capacitor (101), strong The dielectric capacitance (101) causes reverse polarization. Considering the same as above, the voltage at point Vg is -V.C1 / (C1 + C2) with respect to V2.
Becomes

Next, as V2, V · C1 / (C1 + C
And a voltage of 2) (time t ₄ ~), the voltage at point Vg becomes approximately 0, hardly no longer applied a voltage to the ferroelectric capacitor (101), the residual polarization remains. Then, a charge corresponding to the remanent polarization remains on the electrode of the paraelectric capacitor (100), so that the voltage at the point Vg is also maintained at about 0.

Since the voltage at the point Vg is the gate voltage of the field effect transistor, the field effect transistor has a low input.

As described above, when V1 = + V, Vg = +
2V · C1 / (C1 + C2), and when V1 = 0, V
g = 0, and each signal is held. C1 for simplicity
= C2, when V1 = + V, Vg = + V, V1 =
When it is 0, Vg = 0.

Next, FIGS. 4A and 4B are views showing a second embodiment of the present invention, wherein FIG. 4A is a plan view and FIG. 4B is a sectional view. In FIG. 4, (1) is a Si substrate on which a thick LOCOS oxide film (2) is formed on one surface. Also,
A thin gate oxide film (3) is formed on the surface of the Si substrate (1), and below the gate oxide film (3) is a well region (4) of a diffusion layer with a low impurity concentration. On the gate oxide film (3), a Po1y-Si film (6) is formed to be elongated, and constitutes a gate electrode of a transistor. (7) is an interlayer insulating film which covers the LOCOS oxide film (2) and the Po1y-Si film (6), and fills the steps to flatten the surface. (8) is a vertical wiring, which electrically connects the metal wiring (9) on the interlayer insulating film (7) and the Poly-Si film (6). The metal wiring (9) is a laminated film of, for example, Pt / IrO ₂ , on which a ferroelectric thin film (10) and a paraelectric thin film (14) are formed. Ferroelectric thin film (1
0) and an upper electrode (11) of Pt or the like are formed on the paraelectric thin film (14). (12) is a second interlayer insulating film which fills a step and flattens the surface. (1
3) is a metal wiring on the surface, which is electrically connected to the upper electrode (11) from the surface.

In the second embodiment shown in FIG. 4, by forming the paraelectric thin film (14) with a high dielectric film, the paraelectric capacitance can be reduced. Further, since the material of the ferroelectric film having a high relative dielectric constant can be used, an effect that the application range of the ferroelectric material is widened is obtained.

Next, a third embodiment of the present invention will be described. The structure is the same as that of the first embodiment shown in FIG. 2, and it is assumed that the values of the ferroelectric capacitor (101) and the paraelectric capacitor (100) are substantially the same.

The operation will now be described with reference to the operation waveform diagram shown in FIG. As the voltage V1 applied to the electrode (104), a voltage signal of + V and -V / 2 with the same waveform as the signal applied to the gate electrode of the field effect transistor is applied. As the voltage V2 applied to the electrode (105), an inverted signal of V1 is applied at a voltage of 0 and + V / 2. That is, when the voltage of V1 is + V, the voltage of V2 is 0, and when the voltage of V1 is -V / 2, V2 is + V / 2.
Is applied.

When V1 = + V and V2 = 0 (from time t ₁ to time t ₁ )
t ₂ ), V1−V2 becomes + V, and this voltage is applied to the ferroelectric capacitor (101) and the paraelectric capacitor (100). Ferroelectric capacitance (101) and paraelectric capacitance (100)
Are approximately the same, the voltage at the point Vg becomes about V / 2 when the ferroelectric capacitor (101) is polarized. Since the voltage at the point Vg is the gate voltage of the field-effect transistor, the field-effect transistor has a high input.

[0047] Next V1 = -V / 2, V2 = + when V / 2 (time t ₂ ~t _3), opposite voltage is applied to V1-V2 is -V, and the ferroelectric capacitor (101) As a result, the ferroelectric capacitor (101) causes reverse polarization. The voltage at point Vg is V
It is 0 because it is approximately the midpoint between 1 and V2. Since the voltage at the point Vg is the gate voltage of the field effect transistor, the field effect transistor has a low input. Therefore, the same signal as the input signal is continuously applied to the gate of the field effect transistor even when the memory is rewritten. That is,
The voltage V1 applied to the electrode (104) and the gate voltage Vg of the field-effect transistor are signals having the same waveform at the high input and the low input.

As described above, according to the third embodiment, since -V / 2 and + V are applied as V1, a signal voltage is applied to the gate of the field effect transistor even when data is rewritten. Continue to be applied. Therefore, the operation of the field effect transistor is not hindered, and the operation can be performed without being conscious of rewriting the memory.

Next, a fourth embodiment of the present invention will be described. The structure is the same as that of the first embodiment shown in FIG. 2, and it is assumed that the values of the ferroelectric capacitor (101) and the paraelectric capacitor (100) are substantially the same.

The operation will be described below with reference to the operation waveform diagram shown in FIG. As the voltage V1 applied to the electrode (104), voltage signals of +3 V / 2 and -V / 2 with the same waveform as the signal waveform applied to the gate electrode of the field effect transistor are applied. Also, the voltage V applied to the electrode (105)
As for 2, a constant voltage of + V / 2 is applied.

When V1 = + 3V / 2 (time t ₁ to
t ₂ ), V1−V2 becomes + V, and this voltage is applied to the ferroelectric capacitor (101) and the paraelectric capacitor (100). Ferroelectric capacitance (101) and paraelectric capacitance (100)
Are about the same, when the ferroelectric capacitor (101) is polarized, a divided voltage of + V / 2 is applied to the paraelectric capacitor (100). Since the voltage of V2 is + V / 2, the voltage of the point Vg becomes + V. Since the voltage at the point Vg is the gate voltage of the field-effect transistor, the field-effect transistor has a high input.

[0052] Next V1 = -V / 2, V2 = + when V / 2 (time t ₂ ~t _3), opposite voltage is applied to V1-V2 is -V, and the ferroelectric capacitor (101) As a result, the ferroelectric capacitor (101) causes reverse polarization. The voltage at point Vg is V
It is 0 because it is approximately the midpoint between 1 and V2. Since the voltage at the point Vg is the gate voltage of the field effect transistor, the field effect transistor has a low input. As described above,
As for the voltage V1 applied to the electrode (104) and the gate voltage Vg of the field effect transistor, the same signal is input between the High input and the Low input.

In FIG. 6, the whole voltage is doubled in terms of expression, and 3V or -V is applied as V1.
The same applies to 2 for applying V.

According to the fourth embodiment, in addition to the effect of the third embodiment, since the configuration is such that a constant voltage is applied as V2, a switching mechanism for the voltage of V2 is unnecessary, and
The effect that the configuration is simple is obtained.

In the above description, one active element having a non-volatile function has been described. However, when a non-volatile memory is to be constructed practically, a plurality of elements are combined in an array to form a bit line. It is natural to write and read via a word line. Although a description of specific examples of the control circuits for the voltages V1 and V2 is omitted, the circuit for generating and switching the voltage in the relationship between V1 and V2 as described above can be easily configured by ordinary technology. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram showing a first embodiment of the present invention, in which (a)
Is a plan view, and (b) is a sectional view.

FIG. 3 is an operation waveform diagram according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a second embodiment of the present invention, in which (a)
Is a plan view, and (b) is a sectional view.

FIG. 5 is an operation waveform diagram according to a third embodiment of the present invention.

FIG. 6 is an operation waveform diagram according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram of a conventional example.

[Explanation of symbols]

1. Semiconductor substrate 2. LOCOS
Oxide film 3 ... Gate oxide film 4 ... Well region 5 ... Dense diffusion layer (lower electrode of paraelectric capacitor) 6 ... Po1y-Si film (upper electrode of gate and paraelectric capacitor) 7 ... First interlayer insulating film Reference Signs List 8 vertical wiring 9 Pt / IrO ₂ laminated film (ferroelectric capacitor lower electrode and wiring) 10 ferroelectric thin film 11 Pt electrode (upper electrode of ferroelectric capacitor) 12 second interlayer insulating film 13 ... metal wiring 14 ... paraelectric thin film 100 ... paraelectric capacitor 101 ... ferroelectric capacitor 102 ... gate electrode 103 ... field effect transistor 104 ... one electrode of ferroelectric capacitor 105 ... one electrode of paraelectric capacitor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/792

Claims (6)

[Claims] 1. A ferroelectric capacitor having a ferroelectric material sandwiched between two electrodes and a field-effect transistor, wherein a gate electrode of the field-effect transistor and one electrode of the ferroelectric capacitor are provided. And a paraelectric capacitor having one electrode connected to a connection point between a gate electrode of the field effect transistor and an electrode of the ferroelectric capacitor. 2. The method according to claim 1, wherein the value of the paraelectric capacitance is substantially equal to or larger than the value of the ferroelectric capacitance, and is sufficiently larger than the gate capacitance of the field effect transistor. 13. The semiconductor device according to claim 1. 3. The ferroelectric capacitor and the paraelectric capacitor have a value of C1, the paraelectric capacitor has a value of C2, and the ferroelectric capacitor has a coercive electric field which is polarized. V = Vp · (C1 + C2) in series circuit with paraelectric capacitor
/ C2, and 2V · C1
3. The semiconductor device according to claim 1, wherein the values of C1 and C2 are set so that / (C1 + C2) becomes larger than the threshold voltage of the field-effect transistor. 4. The method according to claim 1, wherein the other electrode of said ferroelectric capacitor has V. (C
When a voltage of (1 + C2) / C2 is applied, a pulse voltage of a predetermined width is generated with a voltage of 0, and when a voltage of 0 is applied to the electrode of the ferroelectric capacitor, V · (C1 + C2)
A means for generating a pulse voltage of a predetermined width with a voltage of / C2, and when not generating a pulse voltage, generating a voltage of V · (C1 + C2) and applying those voltages to the other electrode of the paraelectric capacitor. The semiconductor device according to claim 3, further comprising: 5. The ferroelectric capacitor and the paraelectric capacitor have the same capacitance value, and when a voltage of 2 V is applied to the other electrode of the ferroelectric capacitor, the paraelectric capacitor has a capacitance value equal to that of the ferroelectric capacitor. A means for applying a voltage of V to the other electrode of the capacitor and applying a voltage of 0 to the other electrode of the paraelectric capacitor when a voltage of -V is applied to the electrode of the ferroelectric capacitor. The semiconductor device according to claim 3, further comprising: 6. The ferroelectric capacitor and the paraelectric capacitor have the same capacitance value, and a voltage of 3 V or a voltage of -V is applied to the other electrode of the ferroelectric capacitor. 4. The semiconductor device according to claim 3, wherein a means for constantly applying a voltage of V is provided to the other electrode of the dielectric capacitor.