JP2692610B2 - Semiconductor non-volatile memory cell and operating method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a memory cell of a semiconductor nonvolatile memory device using a ferroelectric film.

[0002]

2. Description of the Related Art RO is used as a nonvolatile semiconductor memory element.
There are M, PROM, EPROM, EEPROM, etc. In particular, the EEPROM is capable of electrically rewriting stored information, and its application development as a flash EEPROM is being extensively promoted.

In this EEPROM, a floating gate type transistor is used, and stored information charges are stored in a floating gate electrode which is a first layer gate electrode of a two layer gate electrode structure. Here, the second-layer gate electrode is called a control gate electrode and is used for controlling rewriting of information charges.

On the other hand, as a storage method completely different from the above-mentioned nonvolatile storage element, a method utilizing spontaneous polarization of a ferroelectric substance is considered. Then, three types of structures have been studied in the method utilizing the ferroelectric. One of them is a capacitor structure, and the other one is MFS (Metal F
erroelectric Semiconductor
r) -FET (Field Effect Trans)
istor) structure, and the third is MFMIS in which this capacitor structure and MFS-FET structure are integrated.
(Metal Ferroelectric Meta
l Insulator Semiconductor
r) structure.

The capacitor structure has a structure in which a ferroelectric thin film is sandwiched between electrodes, and information is read out by detecting the presence or absence of a reversal current due to polarization reversal of the spontaneous polarization of the ferroelectric. In the MFS-FET structure, a gate insulating film of a MIS-type FET is formed of a ferroelectric thin film, and induced on the semiconductor surface so as to compensate the spontaneous polarization according to the direction and size of the spontaneous polarization of the ferroelectric. The information is read out by utilizing the fact that the electric conductivity of the semiconductor surface changes due to the generated electric charges. The MFMIS has the structure of the floating gate type transistor described above, and the insulating film between the floating gate electrode and the control gate electrode is formed of a ferroelectric thin film. The reading of the stored information in this case is performed in the same manner as in the case of the above-mentioned MFS-FET structure.

Various types have been proposed as memory cells using the nonvolatile memory element having such a structure. Capacitor structure is 1 transistor and 1 in normal DRAM
It is used by replacing with one capacitor of a memory cell of a capacitor. Further, the MFS-FET structure and the MFMIS structure are similar to the memory cell of the flash EEPROM, and it is said that one transistor is used for the highest integration.

[0007]

The above-mentioned nonvolatile memory element or the memory cell using these elements has the following problems, respectively.

EPROM utilizing electron tunneling effect
In the system, a large electric field is required to inject charges from the silicon substrate into the gate electrode. Furthermore, charge traps occur in the silicon oxide film or at the interface between the silicon oxide film and the silicon substrate, and the number of times of rewriting is limited.

In a capacitor structure utilizing the spontaneous polarization of a ferroelectric substance, the number of rewrites is significantly increased to about 10 ¹⁰ times as compared with about 10 ^{6 in} the case of the EPROM system described above, but the present DRAM It is still insufficient to realize the same function as. When this capacitor structure is applied to the above-mentioned capacitor of the normal DRAM memory cell, the information stored during the information read operation must be destroyed. Therefore, the same information must be written again after reading the information. For this reason, there is a drawback that the number of times of rewriting necessary information increases.

In the MFS-FET structure, in order to directly form the ferroelectric thin film on the active region of the silicon substrate surface,
It is difficult to control the interface state of the silicon substrate surface,
It has a drawback that the nonvolatile memory element becomes unstable.

In the MFMIS structure, a voltage is applied between the control gate electrode and the semiconductor substrate to spontaneously polarize the ferroelectric thin film. However, between the control gate electrode and the semiconductor substrate, there is a first capacitor having the control gate electrode as one electrode, the floating gate electrode as the opposite electrode, and the ferroelectric thin film as the capacitive dielectric film, and the floating gate electrode. Is formed as an electrode, the semiconductor substrate is a counter electrode, and the second capacitor having a gate insulating film as a capacitive dielectric film is connected in series. Therefore, during the information writing operation, the applied voltage for the spontaneous polarization described above increases. Here, in order to increase the voltage applied to the first capacitor, the capacitance value of the second capacitor must be increased. But,
Normally, the dielectric constant of a ferroelectric thin film is much higher than the dielectric constant of an insulating film such as a silicon oxide film used as a gate insulating film. For this reason, it is necessary to make the gate insulating film extremely thin or to increase the area of the second capacitor, which makes it difficult to realize the nonvolatile memory device.

Furthermore, when a memory cell is formed by one transistor of this MFMIS structure, it is essential to apply a predetermined voltage to the control gate electrode of the MFMIS in the information reading operation as in the information writing operation. become. This cannot be avoided in order to uniquely select a desired memory cell. For this reason, the number of times the voltage is applied to the ferroelectric thin film increases, and the problem of deterioration of the ferroelectric characteristics due to repeated polarization or polarization inversion easily occurs.

An object of the present invention is to solve the above problems and to increase the number of times information charges are rewritten, lower the operating voltage, and extend the life of the ferroelectric material.

[0014]

According to the present invention, there is provided:
A first MIS type FET formed on a semiconductor substrate, and a ferroelectric thin film is formed on one electrode connected to the gate electrode of the first MIS type FET, and an opposing electrode is formed on the ferroelectric thin film. A ferroelectric element having a formed capacitor structure,
A second one in which one of the source / drain regions is connected to the one electrode, the other of the source / drain regions is connected to the first bit line, and the gate electrode is connected to the first word line. MISFET, the source region and the drain region are respectively connected to the drain region and the second bit line of the first MISFET, and the gate electrode is the second.
In a third MIS type FET connected word line is configured nonvolatile memory cell, opposite conductivity of the ferroelectric element
The poles are connected to a common wiring whose potential changes. And
The first bit line and the common wiring are paired to form a pair.
It comes to be arranged in the mosel cell part.

Here, the first MIS type F is preferable.
That is, the threshold voltage of ET is set to 0V.

More preferably, the second MIS type FE
T is provided in the silicon thin film on the insulating film formed on the surface of the semiconductor substrate.

In the operation of writing information stored in the semiconductor nonvolatile memory cell, the second MIS-type FET is turned on and a voltage is applied between the first bit line and the counter electrode of the ferroelectric element. Is applied, and then the one electrode of the ferroelectric element is set to 0 V, and then the second MIS-type FET is turned off.

In the read operation of the stored information, 0 V is applied to the counter electrode of the ferroelectric element, the third transistor is turned on, and the potential of the second bit line is amplified. Detected.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram for explaining the configuration of a memory cell of the present invention, and FIGS. 2 and 3 are time charts of clock signals during a write / read operation of memory cell information. Further, FIG. 4 is a diagram for showing the stored information reading operation in the present invention.

As shown in FIG. 1, one memory cell is composed of a write transistor W ₁₁ , a ferroelectric element C ₁₁ , a detection transistor S ₁₁ and a read transistor R ₁₁ . Here, the ferroelectric element C ₁₁ has a capacitor structure and has a structure in which a ferroelectric thin film is formed between two electrodes. Hereinafter, these two electrodes will be referred to as an upper electrode and a lower electrode. .

In such a memory cell configuration, the gate electrode of the write transistor W ₁₁ is connected to the write word line WW1, and the drain electrode and the source electrode of this write transistor W ₁₁ are the write bit line BW1 and the detection transistor S11, respectively. Gate electrode and the lower electrode of the ferroelectric pair element C11 via a node N11. Further, the upper electrode of the ferroelectric element C ₁₁ described above is connected to the common plate CP1. The gate electrode of the read transistor R ₁₁ is connected to the read word line WR1, the drain electrode of the read transistor R ₁₁ is connected to the read bit line BR1, and the source electrode is connected to the drain electrode of the detection transistor S ₁₁ described above. . The source electrode of the detection transistor S ₁₁ is grounded.

The memory cells configured as described above are repeatedly arranged a predetermined number of times as shown in FIG. FIG. 1 shows a case where memory cells for 4 bits are arranged. Here, the write transistor W
_The electrodes of ₂₁ , W ₁₂ , W ₂₂ , the ferroelectric elements C ₂₁ , C ₁₂ , C ₂₂ , the detection transistors S ₂₁ , S ₁₂ , S ₂₂ and the read transistors R ₂₁ , R ₁₂ , R ₂₂ are the same as those described above. Connections are made in the same way as for the corresponding elements of the memory cell.

Next, a method of writing information into the memory cell shown in FIG. 1 will be described. FIG. 2 is a time chart of the clock signal in the case of the information writing operation. Here, the transistor in FIG. 1 is composed of an n-channel MOS transistor, and the circuit is operated in positive logic.

In the case of the write operation, _first, at time t ₁ , a positive voltage is applied to the write word line WW1 to write the write transistor W.
Make ₁₁ conductive. After this, information is written in the ferroelectric element C ₁₁ . When writing the logic "1" of information, as shown in FIG. 2, a positive voltage is applied to the write bit line BW1 at t ₂ and becomes 0V at t ₃ . During this time, the common plate CP1 is fixed at 0V. By doing so, spontaneous polarization is formed in the ferroelectric element C ₁₁ from the lower electrode toward the upper electrode. Then, after forming the spontaneous polarization, the node N ₁₁ is set to 0V, the above-mentioned write word line WW1 is set to 0V at t ₄ , and the write transistor W ₁₁ is made non-conductive. Similarly, when writing the logic "0" of information, a positive voltage is applied to the write word line WW1 at t ₅ as shown in FIG. Write bit line BW1 this time is to 0V, and a positive voltage is applied to the common plate CP1 o'clock t _6. By doing so, spontaneous polarization is formed in the ferroelectric element C ₁₁ from the upper electrode toward the lower electrode. After forming the spontaneous polarization, the node N ₁₁ is set to 0V at t ₇ , and then the write word line WW1 is set to 0V at t _{8 to} bring the write transistor W ₁₁ into the non-conducting state.

As described above, one memory cell described above is uniquely selected, and nonvolatile information is written and held in the ferroelectric element C ₁₁ as spontaneous polarization. In such a write operation, the read word line WR1 is fixed at 0V.

Next, a method of reading information from the memory cell shown in FIG. 1 will be described. FIG. 3 is a time chart of the clock signal in the case of the information reading operation.

In the case of the read operation, the write word line WW1 is set to 0V as shown in FIG.
Make ₁₁ non-conductive. In this way, the write bit line BW1 is set to 0V and the common plate CP1 is set to 0V. In this state, the read bit line BR1 is precharged to a certain positive potential. a positive voltage is applied to t ₉ at read word line WR1. As a result, the read transistor R ₁₁ becomes conductive. When the information "1" is written in the node N ₁₁ , the read bit line BR
1 is boosted to the positive voltage setting potential at t ₁₀ , and information “0”
In the case of, it becomes 0V. Here, the read bit line BR
A sense amplifier is connected to 1 (not shown), and the sense amplifier senses and amplifies the potential of the read bit line BR1 corresponding to the OFF state and the ON state of the detection transistor S ₁₁ . Here, the detection transistor S
_The OFF state of ₁₁ means a state where a current whose gate voltage is equal to or lower than the threshold voltage flows, and the ON state means a state where a current of a gate voltage exceeding the threshold voltage flows.

The operation of the non-volatile memory cell of the present invention has been described above in the case where the write operation and the read operation are performed separately, but in the non-volatile memory cell of the present invention, an information writing transistor and an information reading transistor are used. It should be noted that the information writing operation and the information reading operation can be performed at the same time because of different configurations.

Next, the characteristics of the ferroelectric element C ₁₁ and the detection transistor S ₁₁ during the writing / reading operation of stored information will be described. FIG. 4 shows the characteristics of a floating gate type transistor in which the upper electrode of the ferroelectric element C ₁₁ is a control gate electrode and the lower electrode (gate electrode of the detection transistor S ₁₁ ) is a floating gate electrode. Here, this characteristic is the detection transistor S
The relationship between the drain current of _{11 and} the voltage applied to the control gate electrode, that is, the control gate voltage. As shown in FIG. 4, information "1"
Is stored, the control gate voltage shifts to the positive voltage side in the above-mentioned curve showing the relationship between the drain current and the control gate voltage. This is because the spontaneous polarization formed on the ferroelectric element C ₁₁ is formed from the floating gate electrode toward the control gate electrode.
This is because positive charges are induced in the channel region of the detection transistor S ₁₁ .

On the other hand, when the information "0" is stored, the control gate voltage shifts to the negative voltage side in the above-mentioned curve showing the relationship between the drain current and the control gate voltage. This is because in this case, the spontaneous polarization formed in the ferroelectric element C ₁₁ is formed in the direction from the control gate electrode to the floating gate electrode, and negative charges, that is, electrons are induced in the channel region of the detection transistor S _11. Because it will be.

In this way, the information "1" or "0" is written and the characteristics of the floating gate type transistor are changed. However, the characteristics of the floating gate type transistor in the state where no information is written are as follows. , Are set so as to form the broken line curve shown in FIG.
That is, the threshold voltage of the floating gate type transistor is set to 0V or in the vicinity thereof. To this end, the threshold voltage of the detection transistor described above is 0.
It should be set to V. This is because the ferroelectric thin film has a very high dielectric constant, and the capacitance value of the ferroelectric element C ₁₁ is much larger than the capacitance value indicated by the gate insulating film of the detection transistor S ₁₁ .

The information stored in this manner is read by making the read transistor R ₁₁ conductive as described with reference to FIG. 3 and detecting the change in the floating gate type transistor characteristics as described above. here,
As shown in FIG. 4, the control gate voltage (corresponding to the voltage of CP1 shown in FIG. 3) is set to 0V. As described above, when the information “1” is stored, the drain current at the control gate voltage of 0 V, that is, the drain current at the point A in FIG. 4, is set, and the detection transistor S ₁₁ is turned off. On the other hand, when the information “0” is stored, the drain current at the point B in FIG. 4 begins to flow through the detection transistor, and the detection transistor S ₁₁ is in the ON state, in the same way as described above. become.

Information is read by utilizing the change in the characteristics of the floating gate type transistor as described above.

Next, the structure of the memory cell of the present invention manufactured will be described with reference to FIG. FIG. 5 is a sectional view of one memory cell of the present invention. A substrate insulating film 2 having a thickness of about 500 nm is formed on the surface of the silicon substrate 1. A single crystal first silicon thin film 3 is formed on the substrate insulating film 2. Here, the film thickness of the first silicon thin film 3 is set to about 20 nm. Such SOI (S
A memory cell is formed on the iicon on Insulator layer.

That is, the gate insulating film 4 for the detection transistor is formed on the first silicon thin film 3. The detection transistor gate insulating film 4 is a silicon oxide film having a thickness of about 10 nm. Further, the first silicon thin film 3 is provided with a detection diffusion layer 5 which becomes a drain region of the detection transistor and a ground diffusion layer 6 which becomes a source region. Then, a second silicon thin film 8 is formed on the detection transistor gate insulating film 4 and the first interlayer insulating film 7. Here, the second silicon thin film 8 is a polysilicon thin film having a thickness of about 20 nm. The second silicon thin film 8 is doped with arsenic impurities to form the floating gate electrode 9. Here, iridium oxide or ruthenium oxide may be formed on the surface of the floating gate electrode 9. Next, the ferroelectric thin film 10 is formed on the floating gate electrode 9. The ferroelectric thin film 10 is composed of lead zirconate titanate (PZT) having a thickness of about 100 nm. The control gate electrode 11 is formed on the ferroelectric thin film 10. In this way, in the above-mentioned ferroelectric element, the lower electrode is set to the floating gate electrode 9
The upper electrode is composed of the control gate electrode 11, and the ferroelectric thin film is composed of PZT. Here, as the ferroelectric thin film, a Pb-based oxide such as lead titanate or a Bi-based oxide ferroelectric such as bismuth titanate may be used.

The write transistor is the second silicon thin film 8
Formed on top. Gate insulating film for write transistor 1
2 is a silicon oxide film having a thickness of about 10 nm.
The write transistor gate electrode 13 is formed on the write transistor gate insulating film 12. The write transistor gate electrode 13 is formed of tungsten polycide. A write diffusion layer 14 is formed on the second silicon thin film 8, and the diffusion layer is electrically connected to the write wiring 16 formed on the second interlayer insulating film 15 through a contact hole.

Further, the gate insulating film 1 for the read transistor
A silicon oxide film 7 is formed on the first silicon thin film 3. Here, the film thickness of this silicon oxide film is set to about 10 nm. Then, the read transistor gate electrode 18 is formed on the silicon oxide film. Further, a read diffusion layer 19 is formed on the first silicon thin film 3, and this diffusion layer is electrically connected to the read wiring 20. In this way, the source / drain regions of the read transistor are composed of the detection diffusion layer 5 and the read diffusion layer 19. Although the structure of the memory cell of the present invention is completed as described above, even if the gate insulating film of the detection transistor, the write transistor and the read transistor described above is formed of an insulating film including a silicon nitride film or the like in addition to the silicon oxide film. I will touch on good things.

Next, such a memory cell structure will be described below in association with the memory cell array described in FIG.

The write wiring 16 is a write bit line BW.
1 and BW2, the write transistor gate electrode 13 is connected to the write word lines WW1 and WW2.
The control gate electrode 11 is a common plate CP.
Connected to 1. Further, the read transistor gate electrode 18 is connected to the read word lines WR1 and WR2.
The read wiring 20 corresponds to the read bit lines BR1 and BR2.

Next, the shift amount of the control gate voltage explained in FIG. 4 obtained in the case of the memory cell structure shown in FIG. 5 will be described. This voltage shift amount ΔV _p is given by the following equation.

[0041]

Here, P _r is the value of the spontaneous polarization of the ferroelectric thin film 10, and ε 0, ε f, and ε p are the permittivity of vacuum, the relative permittivity of the ferroelectric thin film 10, and the gate insulating film for the detection transistor, respectively. 4 represents the relative dielectric constant of 4. Further, df and dp represent the thicknesses of the ferroelectric thin film 10 and the detection transistor gate insulating film 4, respectively.

Here, the spontaneous polarization value P _r of PZT is set to 10 μm.
C / cm ² , relative permittivity εf is 500, and relative permittivity of the gate insulating film 4 for the detection transistor is 4. Also, PZ
When ΔV _p is calculated with the thickness of T being 100 nm and the thickness of the detection transistor gate insulating film 4 being 10 nm, this value is about 2V. This value is sufficient for the information read operation. Here, the film thickness of the above PZT is 50
When it is set to about nm, ΔV _p is about 1 V, and it can be understood that it can be sufficiently used under such conditions.

As described above, the detection transistor is set to SO.
When formed on I, the drain current increases sharply with respect to the gate voltage in the subthreshold characteristic of this transistor. For this reason, the current difference between the OFF state and the ON state of the detection transistor becomes large.
The information "1" and the information "0" indicated by the floating gate type transistor characteristic of (3) can be easily determined.

[0045]

As described above, according to the present invention, the memory cell has the MIS type FET formed on the semiconductor substrate.
And a ferroelectric element having a capacitor structure in which a ferroelectric thin film is formed on a lower electrode connected to the gate electrode of this MIS type FET and an upper electrode is formed on the ferroelectric thin film, and one source A MIS transistor having a drain region connected to the lower electrode and the other source / drain region connected to an information writing line, and a MIS having a source region and a drain region connected to the drain region and the information reading line of the MIS type FET, respectively. It is composed of a transistor.

As described above, since information storage of the memory cell of the present invention is performed by spontaneous polarization of the ferroelectric substance, the above-mentioned EPR is performed.
The number of times of rewriting information is significantly increased to 10 ¹⁰ to 10 ¹² times as compared with the memory cell using the OM type nonvolatile memory element.

Further, writing of stored information to the memory cell of the present invention is different from the above-mentioned conventional memory cell of the MFMIS structure, in that a voltage is directly applied between the lower electrode and the upper electrode of the ferroelectric element of the capacitor structure. Is applied, it is easy to reduce the write voltage. For example, the write operation at about 2V becomes possible.

Further, in reading the stored information of the memory cell, there is no destruction of information as in the case of the normal DRAM type memory cell as described above, and it is not necessary to rewrite information. In addition, since no voltage is applied to the ferroelectric film when reading information as in the memory cell having one MFMIS structure described above, polarization reversal fatigue or polarization fatigue of this ferroelectric film is significantly reduced. Therefore, the number of times of writing / reading of the memory cell can be increased, and the life of the memory cell can be extended.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a configuration of a memory cell of the present invention.

FIG. 2 is a time chart explaining a write operation of memory cell information of the present invention.

FIG. 3 is a time chart explaining a read operation of memory cell information of the present invention.

FIG. 4 is a diagram showing transistor characteristics for explaining the operation of the memory cell of the present invention.

FIG. 5 is a cross-sectional view illustrating the structure of the memory cell of the present invention.

[Explanation of symbols]

W ₁₁ , W ₁₂ , W ₂₁ , W ₂₂ Write transistor C ₁₁ , C ₁₂ , C ₂₁ , C ₂₂ Ferroelectric element S ₁₁ , S ₁₂ , S ₂₁ , S ₂₂ Detection transistor R ₁₁ , R ₁₂ , R ₂₁ , R ₂₂ read transistor WW1, WW2 write word line BW1, BW2 write bit line N ₁₁ , N ₁₂ , N ₂₁ , N ₂₂ node CP1, CP2 common plate WR1, WR2 read word line BR1, BR2 read bit line 1 silicon substrate 2 substrate Insulating film 3 First silicon thin film 4 Detection transistor gate insulating film 5 Detection diffusion layer 6 Grounding diffusion layer 7 First interlayer insulating film 8 Second silicon thin film 9 Floating gate electrode 10 Ferroelectric thin film 11 Control gate electrode 12 Writing Transistor gate insulating film 13 Write transistor gate electrode 14 Write diffusion layer 15 Second layer Enmaku 16 write wiring 17 read transistor gate insulating film 18 read transistor gate electrode 19 reads diffusion layer 20 reading wirings

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/792

Claims (6)

(57) [Claims] 1. A first MIS formed on a semiconductor substrate.
Type FET, and a ferroelectric element having a capacitor structure in which a ferroelectric thin film is formed on one electrode connected to the gate electrode of the first MIS type FET, and a counter electrode is formed on the ferroelectric thin film. , One of the source / drain regions is connected to the one electrode, the other of the source / drain regions is connected to the first bit line, and the gate electrode is connected to the first word line. 2 MIS type FET,
The source region and the drain region are respectively the first MIS.
Type FET and a third MIS type FET connected to the second bit line and having a gate electrode connected to the second word line, and the counter electrode of the ferroelectric element is electrically charged.
A semiconductor non-volatile memory cell, characterized in that it is connected to a common wiring which changes its position . 2. The first bit line and the common wiring are
2. The semiconductor nonvolatile memory cell according to claim 1, wherein the semiconductor nonvolatile memory cells are arranged in pairs in the memory cell portion . 3. The threshold voltage of the first MIS-type FET
The semiconductor nonvolatile memory cell according to claim 1 or 2, wherein the voltage is 0V . 4. The second MIS type FET is the semiconductor.
Provided on the silicon thin film on the insulating film formed on the surface of the substrate
Claim 1, claim 2 or characterized in that
The semiconductor nonvolatile memory cell according to claim 3. 5. In the operation of writing stored information, the first
When the second MIS-type FET is turned on, the first bit
Voltage is applied between the contact line and the opposite electrode of the ferroelectric element.
Then, the one electrode of the ferroelectric element is set to 0V.
After that, the second MIS-type FET is turned off.
The method for operating a semiconductor nonvolatile memory cell according to claim 1 or 2, characterized in that : 6. In the operation of reading stored information, the
0 V is applied to the counter electrode of the dielectric element,
The MIS-type FET is turned on, and the second bit
The electric potential of the line is detected, or
The method of operating a semiconductor nonvolatile memory cell according to claim 2.