JPH03278629A - Immediate synchronizing system for synchronizing signal - Google Patents

Immediate synchronizing system for synchronizing signal

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Publication number
JPH03278629A
JPH03278629A JP7671990A JP7671990A JPH03278629A JP H03278629 A JPH03278629 A JP H03278629A JP 7671990 A JP7671990 A JP 7671990A JP 7671990 A JP7671990 A JP 7671990A JP H03278629 A JPH03278629 A JP H03278629A
Authority
JP
Japan
Prior art keywords
station
time
difference
synchronizing signal
synchronization signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7671990A
Other languages
Japanese (ja)
Other versions
JP3021525B2 (en
Inventor
Shigeru Usuki
臼杵 繁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2076719A priority Critical patent/JP3021525B2/en
Publication of JPH03278629A publication Critical patent/JPH03278629A/en
Application granted granted Critical
Publication of JP3021525B2 publication Critical patent/JP3021525B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To obtain synchronization state immediately by obtaining a time difference between synchronizing signals of a host station and its own station individually at the host station and its own station and controlling a synchronizing signal of its own station based on both the time differences. CONSTITUTION:A power supply application detection circuit 7 detects power application of its own station, an absolute value difference detection circuit (ADV) 8 obtains a mean value F of the absolute value of the difference between the time difference C of a synchronizing signal A of its own station and a synchronizing signal B from a host station and a time difference D obtained similarly at the host station. A control direction detection circuit (CGC) 9 decides the time direction controlling the synchronizing signal A of its own station through the comparison between both the time differences C, D to decide a control variable with a mean absolute value difference F1/F2 from the AVD 8 and sends an output G representing them to a pulse generating circuit(PGC) 10. The PGC 10 sends a control pulse H at a point of time in response to the output G of the CDD 9 to reset a frequency divider circuit 3 thereby restarting the frequency division. Thus, the synchronizing signal of its own station is synchronous with the synchronizing signal of the host station in response to the application of power.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、データの送受信を行なう上位局からの同期信
号に応じ、自局の同期信号を即時に同期させる方式に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for immediately synchronizing the synchronization signal of a local station in response to a synchronization signal from an upper station that transmits and receives data.

〔従来の技術〕[Conventional technology]

第3図に従来例のブロック図を示すとおシ、上位局と対
向する下位の自局においては、発条器(以下、08C)
1によシ発生した信号を自動位相制御回路(以下、AP
C)2へ与え、ここにおいて位相調整を行なつ九うえ分
周回路(以下、DIV)3により分周し、自局の同期信
号(以下、LSY)人として送出する一力、これを時間
計測回路(以下、TMC)4へ与えると共に、受信部(
以下、REC)5  により受信した上位局からの同期
信号(以下、R8Y)B 4TMC4へ与え、ここにお
いてLSY・AとR8Y−Bとの時間差Cを求め、これ
を比較回路(以下、CMP)6へ与えるものとなってい
る。
Fig. 3 shows a block diagram of the conventional example. In the lower station facing the upper station, the oscillator (hereinafter referred to as 08C)
The signal generated by 1 is passed through an automatic phase control circuit (hereinafter referred to as AP).
C) 2, the frequency is divided by the frequency divider circuit (hereinafter referred to as DIV) 3 that performs phase adjustment, and the synchronization signal of the own station (hereinafter referred to as LSY) is sent out as a signal, which is used for time measurement. It is supplied to the circuit (hereinafter referred to as TMC) 4 and also to the receiving section (
Hereinafter, the synchronization signal (hereinafter referred to as R8Y) B from the upper station received by the REC) 5 is given to the 4TMC4, where the time difference C between LSY・A and R8Y-B is determined, and this is calculated by the comparison circuit (hereinafter referred to as CMP) 6. It is meant to be given to

また、図上省略した上位局においては、上位局の同期信
号と、受信したLSY−Aとの時間差を同様に求めたう
え、これを示す信号を下位局へ送信するものとなってお
り、この時間差りをRFe5により受信し、上位局から
の時間差りとTMC4により求めた時間差CとをCMP
6において比較し、この結果によシ人PC2の位相調整
状況を制御し、C=Dとなる方向へLSY−Aの位相を
変化させ、これにより上位局の同期信号に対しLSY−
Aを同期させるものとなっている。
In addition, the upper station, which is omitted in the diagram, similarly calculates the time difference between the synchronization signal of the upper station and the received LSY-A, and then sends a signal indicating this to the lower station. The time difference is received by RFe5, and the time difference from the upper station and the time difference C obtained by TMC4 are processed by CMP.
6, and as a result, the phase adjustment status of the PC 2 is controlled, and the phase of LSY-A is changed in the direction that C=D.
This is to synchronize A.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、自局の電源投入時には、L8Y−Aが上位局の
同期信号に対し全くの非同期状態となっており、上位局
の同期信号に対しLSY−Aが同期状態となるまでには
、自局と上位局との間の伝送遅延時間、および、各回路
4〜6による位相制御範囲、制御周期等により定まる同
期引込時間を要し、これが比較的長時間となるため即時
に同期状態が成立せず、直ちにデータの送受信を開始で
きない欠点を生じている。
However, when the power of the own station is turned on, L8Y-A is completely asynchronous to the synchronization signal of the upper station, and by the time LSY-A becomes synchronized with the synchronization signal of the upper station, the own station The synchronization pull-in time is determined by the transmission delay time between the terminal and the upper station, the phase control range and control cycle of each circuit 4 to 6, and this takes a relatively long time, so the synchronization state cannot be established immediately. First, there is a drawback that data transmission and reception cannot be started immediately.

〔課題を解決するための手段〕[Means to solve the problem]

前述の課題を解決するため、本発明はつぎの手段により
構成するものとなっている。
In order to solve the above-mentioned problems, the present invention is configured by the following means.

すなわち、上位局からの同期信号Bと自局の同期信号A
との時間差Cおよび上位局において求めた上位局の同期
信号と自局の同期信号との時間差D′fr入力とし、両
時間差C,D間の差の絶対値を求めたうえこれの平均を
求める絶対値差検出回路と、両時間差C,Dの比較によ
り自局の同期信号人を制御する時間的方向を求める制御
方向検出回路と、これの出力および絶対値の平均に応じ
て自局の同期信号を発生する時点を制御する制御パルス
の送出を行なうパルス発生回路と、これら各回路の動作
を自局の電源投入に応じて開始させる電源投入検出回路
とを備えたものである。
In other words, the synchronization signal B from the upper station and the synchronization signal A of the own station
Input the time difference C and the time difference D'fr between the synchronization signal of the higher station and the synchronization signal of the own station determined at the upper station, calculate the absolute value of the difference between both time differences C and D, and then calculate the average of these. An absolute value difference detection circuit, a control direction detection circuit that determines the time direction for controlling the synchronization signal of the own station by comparing the two time differences C and D, and synchronization of the own station according to the output of this and the average of the absolute values. It is equipped with a pulse generation circuit that sends out control pulses that control the timing of signal generation, and a power-on detection circuit that starts the operation of each of these circuits in response to power-on of its own station.

C作用〕 したがって、電源投入に応じて各回路が動作状態となり
、自局の同期信号人と上位局からの同期信号Bとの時間
差C1および、上位局において同様に求めた時間差りに
したがい、自局の同期信号Aを制御する時間的方向が定
まると共に、両時間差C,DO差の平均絶対値によシ制
御量が定まり、これらによシ同期信号人の発生時点が制
御されるため、上位局の同期信号に対し同期信号Aが即
時に同期状態となる。
Effect C] Therefore, each circuit becomes operational when the power is turned on, and the circuit automatically operates according to the time difference C1 between the synchronizing signal of the own station and the synchronizing signal B from the upper station, and the time difference similarly determined at the upper station. The time direction for controlling the synchronization signal A of the station is determined, and the control amount is determined by the average absolute value of the time difference C and DO difference, and these control the time point at which the synchronization signal person is generated. The synchronization signal A immediately becomes synchronized with the synchronization signal of the station.

〔実施例〕〔Example〕

以下、実施例を示す第1図および第2図によって本発明
の詳細な説明する。
Hereinafter, the present invention will be explained in detail with reference to FIGS. 1 and 2 showing embodiments.

第1図はブロック図、第2図は制御状況のタイミングチ
ャートであり、第1図においては、第3図に示すものの
ほか、電源投入検出回路(以下、POD)7、絶対値差
検出回路(以下、AVD)11、制御方向検出回路(以
下、CDD)9、および、パルス発生回路(以下、PG
C)10 が備えてあり、AVD8は、TMC4からの
り、5Y−AとR8Y−Bとの時間差C1および、上位
局において求めた上位局の同期信号と受信したLSY−
Aとの時間差りを入力とし、この両時間差CとDとの差
の絶対値IC−DIを求めると共に、これの平均値を求
めるものとなっている。
FIG. 1 is a block diagram, and FIG. 2 is a timing chart of the control situation. In addition to what is shown in FIG. 3, FIG. AVD (hereinafter referred to as AVD) 11, control direction detection circuit (hereinafter referred to as CDD) 9, and pulse generation circuit (hereinafter referred to as PG)
C) 10 is provided, and the AVD8 receives the information from the TMC4, the time difference C1 between 5Y-A and R8Y-B, the synchronization signal of the upper station obtained at the upper station, and the received LSY-
The time difference with A is input, and the absolute value IC-DI of the difference between the two time differences C and D is determined, and the average value thereof is determined.

ま7’j、POD7は自局の電源投入を検出し、これの
検出出力EによりAVD litを動作状態とするため
、これにしたがってCDD9およびPGCloも動作を
開始する状態となる。
7'j, POD7 detects the power-on of its own station, and puts the AVD lit into an operating state based on its detection output E, so that CDD9 and PGClo also start operating accordingly.

したがって、CDD9は、両時間差C,Dの比較を行な
い、C<DであればLSY−Aの発生時点を早くし、C
>DのときはL8Y−Aの発生時点を遅くすべきと判断
し、これによりLSY−Aの時間的制御方向を定めると
共に、AVD8からの平均絶対値差Fを1/2とする演
算を行ない、これにより制御量を定め、これらを示す出
力GをPGCloへ送出する。
Therefore, CDD9 compares the two time differences C and D, and if C<D, the generation point of LSY-A is brought forward, and C
>D, it is determined that the generation point of L8Y-A should be delayed, thereby determining the temporal control direction of LSY-A, and performing a calculation to reduce the average absolute value difference F from AVD8 to 1/2. , thereby determining the control amount and sending an output G indicating these to PGClo.

するとPGolGは、I、SY・人の現発生時点を基準
とし、CDD9からの時間的制御方向かつ制御量に応じ
た時点の制御パルスHを送出し、これKよりカウンタ等
を用いたDIV3のリセットを行なう。
Then, PGolG sends out a control pulse H from CDD 9 in the temporal control direction and at a time corresponding to the control amount, based on the current occurrence point of I, SY, and person, and uses this K to reset DIV3 using a counter etc. Do the following.

このため、DIV3は、制御パルスHにしたがい分周動
作を再開するものとなシ、これによfi LSY・Aが
上位局の同期信号と完全に同期状態となる。
Therefore, DIV3 restarts the frequency division operation in accordance with the control pulse H, and as a result, fi LSY·A becomes completely synchronized with the synchronization signal of the upper station.

すなわち、第2図囚に時間差C,DがCくDの場合を示
すとお夛、上位局Uの同期信号が発生時点21となって
いれば、これが伝送路を介する遅延により自局りにおい
ては受信時点22となるのに対し、自局LQL8Y−A
は発生時点23となっているため、R8Y −BとI、
5Y−Aとの時間差Cは時点22と23との間隔を示す
ものとなる。
In other words, if the time difference C and D is C x D in Figure 2, if the synchronization signal from the upper station U is generated at time 21, this will be delayed at the own station due to the delay via the transmission path. At reception time 22, own station LQL8Y-A
Since the occurrence time is 23, R8Y-B and I,
The time difference C from 5Y-A indicates the interval between time points 22 and 23.

また、自局りのLSY−Aの発生時点23が、伝送路の
遅延を介する上位局Uにおいては受信時点24となるた
め、これらの時間差りは、時点24と21との間隔とな
り、これが上位局Uにおいて求められたうえ下位局りへ
送信されるものとなる。
In addition, since the generation point 23 of LSY-A at the local station becomes the reception point 24 at the upper station U via the transmission path delay, the time difference between these is the interval between points 24 and 21, which is the It is obtained at station U and then transmitted to the lower station.

したがって、時間差CとDとの平均絶対値差C−DIを
求め、これの1/2を更に求め、とのIc−Dl/2を
制御量とし、かつ、LSY−Aの発生時点23を矢印の
とおり早くする方向へ制御し、これを発生時点25とす
ることによシ、発生時点21と25とが一致すると共に
、各受信時点22と26も一致し、LSY−Aが完全に
同期する。
Therefore, calculate the average absolute value difference C-DI between the time differences C and D, further calculate 1/2 of this, set Ic-Dl/2 as the control amount, and point the point in time 23 at which LSY-A occurs with the arrow By controlling this in the direction of speeding up the signal and setting this as the generation point 25, the generation points 21 and 25 match, and the respective reception points 22 and 26 also match, so that LSY-A is completely synchronized. .

以上に対し、申)は時間差C,DがC)Dの場合であり
、自局りの発生時点23が上位局Uの発生時点21よシ
も早く表っているため、同様に制御量1cmD1/2を
求めると共に、矢印によシ示すとおり発生時点23を遅
くなる方向へ制御し、これを発生時点25とすることに
より完全な同期状態となる。
In contrast to the above, Mon) is a case where the time difference C, D is C) D, and the occurrence time 23 of the local station appears earlier than the occurrence time 21 of the upper station U, so similarly, the control amount 1 cmD1 /2 is determined, and by controlling the occurrence point 23 to become later as shown by the arrow, and making this the occurrence point 25, a complete synchronization state is achieved.

〔発明の効果〕〔Effect of the invention〕

以上の説明により明らかなとおり本発明によれば、上位
局と自局との各同期信号相互間の時間差を上位局および
自局において各個に求め、両時間差の比較によシ自局の
同期信号を制御する時間的方向を定めると共に、この時
間的方向かつ両時間差の差の平均絶対値に応じて自局の
同期信号を発失する時点の制御を行ない、この制御を自
局の電源投入に応じて開始させるものとしたことにより
、自局の同期信号が電源投入に即応して上位局の同期信
号と直ちに同期状態となるため、即時にデータの送受信
が自在となシ、上位局と対向する各局の同期信号を上位
局の同期信号と同期させる方式において顕著な効果が得
られる。
As is clear from the above explanation, according to the present invention, the time difference between the synchronization signals of the upper station and the own station is determined individually in the upper station and the own station, and the synchronization signal of the own station is determined by comparing the two time differences. In addition to determining the time direction for controlling the time difference, the time point at which the synchronization signal of the local station is emitted or lost is controlled according to this temporal direction and the average absolute value of the difference between the two time differences, and this control is applied to the power-on of the local station. As a result, the synchronization signal of the local station immediately becomes synchronized with the synchronization signal of the higher-level station in response to power-on, so data can be sent and received immediately. A remarkable effect can be obtained in a method in which the synchronization signal of each station is synchronized with the synchronization signal of the upper station.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は本発明の実施例を示し、第1図は
ブロック図、第2図は制御状況のタイミングチャート、
第3図は従来例のブロック図である。 1・・・・発振器、2・・・・自動位相制御回路、3・
・・・分周回路、4・・・・時間計測回路、5・・・・
受信部、7・・・・電源投入検出回路、8・・・・絶対
値差検出回路、9・・・・制御方向検出回路、10・・
・・パルス発生回路、A・・・・自局の同期信号、B・
・・・上位局からの同期信号。
1 and 2 show an embodiment of the present invention, FIG. 1 is a block diagram, FIG. 2 is a timing chart of the control situation,
FIG. 3 is a block diagram of a conventional example. 1... Oscillator, 2... Automatic phase control circuit, 3...
... Frequency dividing circuit, 4... Time measurement circuit, 5...
Receiving section, 7...Power-on detection circuit, 8...Absolute value difference detection circuit, 9...Control direction detection circuit, 10...
・・Pulse generation circuit, A・・Synchronization signal of own station, B・
...Synchronization signal from the upper station.

Claims (1)

【特許請求の範囲】[Claims] 上位局の同期信号に対して自局の同期信号を同期させる
方式において、前記上位局からの同期信号と前記自局の
同期信号との時間差および前記上位局において求めた該
上位局の同期信号と前記自局からの同期信号との時間差
を入力とし該両時間差間の差の絶対値を求めたうえ該絶
対値の平均を求める絶対値差検出回路と、前記両時間差
の比較により前記自局の同期信号を制御する時間的方向
を求める制御方向検出回路と、該検出回路の出力および
前記絶対値の平均に応じて前記自局の同期信号を発生す
る時点を制御する制御パルスの送出を行なうパルス発生
回路と、前記各回路の動作を自局の電源投入に応じて開
始させる電源投入検出回路とを備えたことを特徴とする
同期信号の即時同期方式。
In a method of synchronizing a synchronization signal of a local station with a synchronization signal of an upper station, an absolute value difference detection circuit which inputs the time difference with the synchronization signal from the own station, calculates the absolute value of the difference between the two time differences, and calculates the average of the absolute values; a control direction detection circuit for determining a temporal direction for controlling a synchronization signal; and a pulse for sending out a control pulse for controlling the time point at which the synchronization signal of the own station is generated according to the output of the detection circuit and the average of the absolute values. 1. An instant synchronization method for synchronization signals, comprising: a generation circuit; and a power-on detection circuit that starts the operation of each of the circuits in response to power-on of its own station.
JP2076719A 1990-03-28 1990-03-28 Synchronous signal immediate synchronization method Expired - Lifetime JP3021525B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2076719A JP3021525B2 (en) 1990-03-28 1990-03-28 Synchronous signal immediate synchronization method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2076719A JP3021525B2 (en) 1990-03-28 1990-03-28 Synchronous signal immediate synchronization method

Publications (2)

Publication Number Publication Date
JPH03278629A true JPH03278629A (en) 1991-12-10
JP3021525B2 JP3021525B2 (en) 2000-03-15

Family

ID=13613371

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2076719A Expired - Lifetime JP3021525B2 (en) 1990-03-28 1990-03-28 Synchronous signal immediate synchronization method

Country Status (1)

Country Link
JP (1) JP3021525B2 (en)

Also Published As

Publication number Publication date
JP3021525B2 (en) 2000-03-15

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