JPS63152224A - Automatic clock synchronizing system - Google Patents

Abstract

PURPOSE:To automatically adjust the phase shift between clocks by controlling the frequency division mode of a frequency division circuit in response to the phase comparison result, and making other frequency division clock synchronize in phase to one frequency-division clock of plural frequency division clocks. CONSTITUTION:Plural clock oscillators 1, 2, plural frequency division circuits 3, 4 provided respectively to the clock oscillators 1, 2 and a phase comparator circuit 5 discriminating the phase difference of the frequency division clocks A, B by the frequency division circuits 3, 4 are provided. Thus, the phase shift between the plural blocks A, B is detected automatically at a prescribed interval and its information is supplied to the frequency divider circuits 3, 4 fetching the output from the oscillators 1, 2 and the period of other clock is adjusted automatically so as to contain the clock most advanced in the plural clocks A, B or the clock most delayed within the permissible error range.

Description

TECHNICAL FIELD The present invention relates to an automatic clock synchronization system, and more particularly to an automatic synchronization system between a plurality of clocks.

In a conventional information processing device, various data processing operations are performed using a plurality of clocks generated by a plurality of oscillators, and these plurality of clocks are required to be phase-synchronized with each other. Therefore, although these multiple clocks are synchronized in phase with each other at a certain point in time, it is inevitable that the clocks will become out of phase with each other over time within the error range allowed for each oscillator. be. As a method for adjusting this phase synchronization shift, an adjuster visually confirms the synchronization shift and corrects it using a correction switch or the like.

As described above, in the conventional art, manual adjustment is performed visually to adjust the phase synchronization deviation between the clocks, which has the disadvantage that the adjustment is very complicated and has an adjustment error.

OBJECT OF THE INVENTION The present invention has been made to solve the drawbacks of such conventional systems, and its purpose is to provide a clock automatic synchronization system that automatically adjusts the phase synchronization difference between clocks. Our goal is to provide the following.

RJJ and Breasts The clock automatic synchronization system according to the present invention includes a plurality of clock oscillators, a plurality of frequency dividing circuits provided corresponding to each of these clock oscillators, and a frequency dividing clock using the frequency dividing circuits with equal names. A phase comparison circuit for determining a phase difference is provided, and the frequency dividing mode of the frequency dividing circuit is controlled according to the result of this phase comparison, so that one divided clock of the plurality of divided clocks is assigned to another divided clock. It is characterized by phase synchronization.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, showing an example in which there are two oscillators and phase synchronization between two clocks is achieved. The clocks of oscillators 1 and 2 are input to frequency divider circuits 3 and 4, respectively, and are frequency-divided (the period is multiplied). It is assumed that these two oscillators 1 and 2 each generate clocks of the same frequency (period) within a certain tolerance range.

Each of the frequency dividing circuits 3 and 4 has a cascade connection circuit configuration of n frequency dividers 31 to 3n and 41 to 4n, and the frequency division ratio of each of the frequency dividers 31 to 3n and 41 to 4n is For example 1/
By setting it to 10, the total frequency division ratio of each frequency dividing circuit 3 and 4 is set to 1/10. Therefore,
The periods of the divided clocks A and B from frequency dividers 3 and 4 are:
This means that the oscillation clock of each oscillator 1 and 2 is 10n times that of the oscillation clock.

The thus obtained frequency-divided clocks and B are input to the phase comparator circuit 5, and the phase lag/advance state between the two clocks is determined. Based on this determination result, control signals 51 and 52 are generated to control the frequency dividing manner of the frequency dividing circuits 3 and 4. In this example, it is assumed that the frequency dividing manner of the final stage frequency dividers 3n and 4n of the frequency dividing circuits 3 and 4 is controlled.

For example, the comparator circuit 5 determines which of the divided clocks A and B is delayed and sends a control signal 51 to the frequency dividing circuit 3 or 4 that generates the delayed clock.
or 52, and instructs adjustment control of the sending period of the delayed clock.

FIG. 2 is a time chart showing an example of the operation of the block in FIG.
1 is a time chart showing the phase relationship between frequency-divided clock B and its output, frequency-divided clock B.

The operation of the embodiment of the present invention will be explained with reference to FIG.

As mentioned above, oscillators 1 and 2 are oscillators having the same oscillation frequency within the tolerance, and the frequency division ratios of each frequency divider circuit 3 and 4 are both 1/10, forming an equal frequency divider circuit. The frequency division ratios of the frequency dividers 31 to 3n and 41 to 4n are all 1/10. Therefore, the divided clocks A and B
The period is 10' of the period of the output clocks of oscillators 1 and 2.
It has doubled.

Suppose now that the frequency-divided clock B is in a phase delayed state with respect to the frequency-divided clock A, which is outside the allowable error range. for example,
R final stage frequency division 33n or 4n input clock (400)
It is assumed that frequency-divided clock B lags frequency-divided clock A by an amount corresponding to approximately one period of . The phase comparator circuit 5 determines this and sets the phase of the divided clock B to the clock 40.
In order to advance by an amount corresponding to one period of 0, the control signal 52
Then, a command is issued to the final stage frequency divider 4n so that its frequency division mode hζ becomes a frequency division ratio of 1/10 to 1/9 only at that moment. In response to this command, the final stage frequency divider 4
Since the frequency division ratio of n is 1/9 only in that case, the second
As shown in the figure, what is originally generated as the clock 201 shown by the dotted line is generated as the indicated clock 200 by the solid line with the phase advanced by one clock of the clock 400. The clock B following this clock 200 is the output of the clock 400 divided by 1/10L, so after LJ, the normal frequency! 91 (oscillation clock 1
0 times the period) and has a phase within the allowable error range with respect to the frequency-divided clock A, and therefore automatic phase synchronization becomes possible.

In this example, the allowable range of the phase shift of both divided clocks A and B is within one clock of the input (400) of the final stage frequency divider 3n or 4n, and the final stage frequency divider 3n or 4n However, it is obvious that the frequency divider whose frequency division is to be controlled should be set according to the size of the allowable range of phase shift. Also, although we have shown an example in which a lagging divided clock is phase-synchronized with a leading divided clock, it is also possible to phase-synchronize a leading divided clock with a lagging divided clock. be. Furthermore, although two cases are shown as frequency-divided clocks, the present invention is equally applicable to the case of three or more frequency-divided clocks.

In addition, in order to increase the adjustment precision of the phase error between the divided clocks, the phase comparison discrimination period in the comparator circuit is shortened, and the frequency divider 31 to 3n, 41 to 4n is closer to the oscillator 1.2. All that is required is to select a frequency divider and control the frequency division mode.

As described in detail, according to the present invention, the phase synchronization difference between a plurality of clocks is automatically detected at regular intervals, and that information is provided to a frequency divider circuit that takes in the output from an oscillator. You can manually set the period of a clock by automatically adjusting the periods of other clocks to be within tolerance relative to the clock that is most selected or the clock that lags behind the clock. It has the effect of enabling synchronization between clocks with much higher precision than that of the conventional method, and of avoiding complexity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time tisade showing an example 01 of the block in FIG. 1. Explanation of symbols of main parts 1.2... Oscillator 3.4... Frequency divider circuit 5... Phase comparator

Claims (1)

[Claims] A plurality of clock oscillators, a plurality of frequency divider circuits provided corresponding to each of these clock oscillators, and a phase comparison circuit that determines the phase difference between the divided clocks by each of these frequency divider circuits are provided. The frequency dividing mode of the frequency dividing circuit is controlled according to the phase comparison result, so that one of the plurality of frequency divided clocks is phase-synchronized with another frequency divided clock. Clock automatic synchronization method.