JPH05241680A - Clock synchronization system - Google Patents

Abstract

PURPOSE:To prevent the increase of the circuitry monitoring the fluctuation of frequency in the clock synchronization system outputting clocks in synchronism with an input clock. CONSTITUTION:Respective input clocks with dissimilar frequency is frequency- divided into the same cycle by a frequency dividing section 1. One of the frequency division clocks outputted from the section 1 is selected by a selector section 2 and the selected frequency division clock is added as an incoming clock of a synchronization section 3 to take out the synchronization clock in synchronism with the input clock. A frequency fluctuation monitoring section 4 is provided to input an incoming clock to the synchronization section 3 outputted from the selector 2 and monitor the frequency fluctuation of the synchronization clock outputted from the section 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronization system for outputting a clock synchronized with an input clock.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing a circuit configuration of a conventional example, which is a circuit for outputting a synchronous clock synchronized with an input clock.

In the figure, 21a, 21b to 21n are a first monitoring section and a second monitoring section.
The monitoring unit to the nth monitoring unit are circuits that monitor the frequency fluctuations of the plurality of input first clocks and second clocks to the nth clock.

Further, 22a, 22b to 22n are a first frequency divider and a second frequency divider.
The frequency dividers to the nth frequency dividers divide the clocks from the first monitoring section 21a and the second monitoring section 21b to the nth monitoring section 21n into clocks having a predetermined same cycle.

A selector unit 23 selects one of a plurality of divided clocks from the first frequency divider 22a, the second frequency divider 22b to the nth frequency divider 22n, and selects the selected clock. Is transmitted as a pull-in clock for generating a synchronous clock.

In the conventional frequency fluctuation monitoring system for synchronous clocks, a plurality of first clocks and second clocks of different frequencies are used.
With respect to the clock to the nth clock, the first monitoring unit 21a and the second monitoring unit 21b to the nth monitoring unit 21n which monitor the respective frequency fluctuations are provided as frequency fluctuation monitoring circuits, and when the input clock is selected by the selector unit 23, At the same time, the first monitoring unit 21a,
The monitoring information of the second monitoring unit 21b to the n-th monitoring unit 21n is switched to monitor the frequency fluctuation of the output pull-in clock.

[0007]

Therefore, each time the frequency of the input clock to be selected increases, it is necessary to increase the number of circuits for frequency fluctuation monitoring with different frequencies to be monitored, so that the circuit scale increases according to the number of selections. There are challenges.

An object of the present invention is to prevent an increase in the scale of a frequency variation monitoring circuit.

[0009]

In order to achieve the above object, according to the present invention, each of a plurality of input clocks having different frequencies is frequency-divided by a frequency divider 1 into the same period, and the frequency divider 1
One of the plurality of divided clocks output by the selector unit 2 is selected, and the selected divided clock is synchronized by the synchronization unit 3
Of the synchronous clock synchronized with the input clock in addition to the synchronous clock of the synchronous clock, the frequency of the synchronous clock output from the synchronous unit 3 by inputting the synchronous clock output from the selector unit 2 to the synchronous unit 3. One frequency fluctuation monitoring unit 4 for monitoring fluctuations is provided.

[0010]

According to the present invention, as shown in FIG. 1, a plurality of input first clocks to nth clocks having different frequencies are provided in the frequency divider 1 and each of the n frequency dividers 1-1 and 1-1 has a different frequency division ratio. The m frequency divider 1-2 ... The k frequency divider 1-n divides the frequency into the same frequency and inputs it to the selector 2, and the selector unit 2 determines which clock among a plurality of first clocks to nth clocks. Select whether to synchronize with. Further, the output of the selector 2 is input to the synchronizing unit 3 as a pull-in clock, and a synchronous clock synchronized with the selected clock is sent out.

Therefore, the frequency fluctuation monitoring section 4 can judge the synchronization abnormality of the synchronous clock by only one frequency fluctuation monitoring circuit by monitoring the frequency fluctuation of the clock of the selected one frequency. It will be possible.

[0012]

FIG. 2 is a diagram showing the circuit configuration of an embodiment of the present invention. The present invention will be described below with reference to FIG.

In the figure, 11a is a frequency divider by 8, 11b is a frequency divider by 16,
11c is a 32 frequency divider, 12 is a selector unit, and 13 is a synchronizing unit. Further, 14 is a counter 14a, a comparison value 14b and a comparator 14
It is a frequency fluctuation monitoring unit equipped with c. 15 is a control unit.

In FIG. 2, as an example, the plurality of input clocks are three types of a first clock of 64 KHz, a second clock of 128 KHz and a third clock of 256 KHz,
The frequency of the pull-in clock of the synchronizing unit 13 is 8 kHz.

The frequencies are 64 KHz, 128 KHz, 256 KH
The three types of input clocks of Z are divided by 8
The frequency is divided into 8 KHz by the frequency divider 11a, the 16 frequency divider 11b for the 16 frequency division operation, and the 32 frequency divider 11c for the 32 frequency division operation, and input to the selector section 12.

The selector unit 12 selects the divided clock based on the clock selection information from the control unit 15,
The selected clock is sent to the synchronization unit 13. The selected 8 KHz clock becomes the pull-in clock of the synchronizing unit 13 which operates at the reference clock (for example, 4 MHz) and sends out the synchronizing clock, and at the same time, is input to the counter 14a of the frequency fluctuation monitoring unit 14.

The counter 14a operates with a comparison clock different from the reference clock used in the synchronizing section 13. In this embodiment, the oscillation frequency of the comparison clock is 256 KHz.
Since the counter 14a counts 32 in a cycle of 8 kHz,
The comparator 14c compares the count value of the counter 14a counted in the cycle of 8 KHz with the preset comparison value 14b to monitor the frequency fluctuation of the pull-in clock output from the selector section 12.

The comparison value 14b has a width in consideration of the jitter and sampling error of the first clock to the third clock which are the input clocks. The width of the comparison value 14b is the width of the comparator 14c.
It can be easily changed by setting.

The output value of the counter 14a is the comparison value 14b.
If it is not within the range, the control unit 15 is notified as an abnormality.

[0020]

As is apparent from the above description, according to the present invention, it is possible to reduce the circuit scale by using a plurality of frequency fluctuation monitoring circuits, which is required. This is advantageous in that it contributes greatly to the cost and scale reduction of the device required by the clock synchronization method.

[Brief description of drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a conventional example.

[Explanation of symbols]

 1 is frequency divider 1-1 is n frequency divider 1-2 is m frequency divider ... 1-n is k frequency divider 2 is selector section 3 is synchronization section 4 is frequency fluctuation monitoring section

Claims (1)

[Claims] 1. A frequency dividing unit divides each of a plurality of input clocks having different frequencies into the same period, and the frequency dividing unit
Select one of the divided clocks output from (1) with the selector (2), add the selected divided clock as the pull-in clock of the synchronizer (3), and synchronize with the input clock. In the case of extracting the synchronized clock, the input of the pull-in clock to the synchronizing unit (3) output from the selector unit (2) and monitoring the frequency fluctuation of the synchronizing clock output from the synchronizing unit (3) A clock synchronization system characterized by being provided with one frequency fluctuation monitoring unit (4) for this purpose.