KR19990009340A - Synchronous device and method - Google Patents

Abstract

When the reference clock supplied from the network synchronizer is out of a certain frequency control range, the quality of the reference clock is deteriorated, resulting in a slip phenomenon in which abnormal data is inserted or data is lost when data is read from the exchange.

In the present invention, when the reference clock is out of the frequency control range by using a microprocessor for controlling a voltage controlled crystal oscillator in a network device for supplying a reference clock to prevent the above phenomenon, the reference clock is switched to perform the switching. The present invention provides a device and method for providing a stable reference clock by selecting a new clock without using the same.

According to an embodiment of the present invention, a network synchronizer includes a reference clock selector for selecting one reference clock from 10 clocks, and a phase difference value between a reference clock selected from the reference clock selector and a feedback clock phase of 4 kHz. A phase comparator, a microprocessor controller for generating a control signal of a voltage controlled crystal oscillator, a voltage controlled crystal oscillator controller for generating a reference clock signal using phase comparison data, and a clock signal of 38.88 MHz obtained from a voltage controlled crystal oscillator 9720 It is made up of a dispensing part.

In accordance with the present invention, a method for monitoring a received reference clock includes selecting a reference clock by using a result value and comparing a phase of a reference clock received from a voltage controlled crystal oscillator and a selected clock by the phase comparator. And a process of selecting a fast mode and a normal mode using a cumulative phase average value P generated through the phase comparison and comparing and analyzing the cumulative calculated value and the voltage controlled crystal oscillator control value. Is done.

Description

Synchronous device and method

The present invention relates to synchronization of a network synchronizer of a switching center. When the reference clock is out of a predetermined frequency control range of -17 ppm to + 17 ppm, the microprocessor notifies the fact and adjusts the clock to detect a failure of the reference clock. The present invention relates to a device and a method having a capable function, and more particularly, to a device based on a slave synchronization method using a crystal oscillator.

In general, the network synchronizer method may be classified into an independent synchronization method, a dependent synchronization method, and a mutual synchronization method according to a method of controlling a clock oscillator of each switching center.

The independent synchronous method has the advantage that each switching station has a high accuracy clock oscillator and supplies its own synchronizer clock so that it is not necessary to control the clock oscillator between the switching stations. This independent motive method is mainly used in places where international relations are not required. However, the independent synchronization method has a disadvantage of requiring a high accuracy clock generator.

The most commonly used network synchronizer in current digital systems is the dependent synchronization method. In the slave synchronization method, the network is composed of a master network using a master-slave hierarchy.If the high-precision clock generator of the master station supplies the clock to the switching station of the slave station, the switching station of the slave station is clocked based on the clock supplied. It is a way to generate. Since this method uses a reference clock provided by the host station, the slip phenomenon that causes data error occurs relatively less, and the clock can be supplied using a crystal oscillator which is more economical than the independent synchronization method. Korea also uses this dependent motivation method.

The mutual synchronization method is a method of controlling synchronization when the switching stations have different clocks by using a separate variable oscillator for each switching station. This method is practically not used because of the disadvantages of large network ripple effect and complicated control in case of failure of Korea.

In a conventional synchronizer having a plurality of reference inputs for the input of a synchronizer, when an operation of the selected reference clock is out of a predetermined range, the exchanger uses the reference clock to diagnose the reference clock. Unless it has a function, the synchronizer device operates even if it is out of the specified range of the reference clock, and thus maintains an incorrect synchronization state throughout the network.In case of reading data from the digital system, abnormal data insertion or data loss, etc. Will cause slip phenomenon.

If it is found that the reference clock of the network synchronizer device is out of the predetermined range, it is necessary to switch to another input reference clock to perform the network synchronizer function to maintain a stable network synchronizer function.

Accordingly, the present invention is to solve the above problems, by using a microprocessor to detect that the reference clock is out of the predetermined range to enable a new high-quality reference clock can be used to operate a stable network synchronizer device It aims to do it.

1 is a circuit configuration diagram of a network synchronizer device according to the present invention

2 is a flowchart of a network synchronizer method according to the present invention.

3 is a frequency control range and a frequency control value of FIG.

4 is a detailed view of a reference clock selector of FIG. 1;

FIG. 5 is a detailed view of the phase comparator and the voltage controlled crystal oscillator of FIG.

Brief description of symbols for the main parts of the drawings

10. Input Reference Clock 11. Reference Clock Selector

12. Selected reference clock 13. Phase comparator

14. Phase compared data value 15. Microprocessor control unit

16. Reference clock selected by processor 18. Voltage controlled crystal oscillator

20. Division section 110. Reference clock selection circuit

112. Division circuit 113. Clock monitoring unit

115: reference clock selection signal 130. phase comparison

132. Phase comparison counters 180. Digital to analog converters

182. Voltage Controlled Crystal Oscillator 1130. Shift Register

1131. Register 1132. Shift register clear signal generator

In order to achieve the above object, the apparatus of the present invention provides a phase difference between a reference clock selector 11 that selects one reference clock from 10 clocks, a selected reference clock, and a feedback clock phase of 4 kHz. A phase comparator 13 for detecting a value, a microprocessor controller for generating a control signal of a voltage controlled crystal oscillator, a voltage controlled crystal oscillator controller 18 and a voltage controlled crystal oscillator for generating a reference clock signal using phase comparison data It consists of a divider 20 for dividing the clock signal of 38.88 MHz obtained by 9720.

In accordance with another aspect of the present invention, there is provided a network synchronization method for monitoring a received reference clock and selecting a reference clock by using a result value, and selecting a reference clock received from a voltage controlled crystal oscillator in a phase comparator. The process of comparing the phases of the clock and the process of selecting the fast mode and the normal mode using the cumulative phase average value P generated through the phase comparison, and the cumulative calculated value and the voltage control crystal oscillator control. This is done by comparing and analyzing the values.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. 1 shows a configuration of a network synchronizer device according to the present invention.

The present invention provides a portion for receiving 10 8 kHz clocks provided by each synchronous reference clock, that is, a clock receiver for receiving one 8 kHz clock generated from BITS and 9 8 kHz clocks received from a line interface. The clock enters into the clock selector through a 10-bit buffer and consists of a clock supervisor circuit for clock supervision and a reference clock selector for selecting a clock under the control of a microprocessor. 9720 divides the 38.88 MHz signal output from the reference clock selector 11 and the clock phase and voltage controlled crystal oscillator selected by the reference clock selector to allow the processor to select the reference clock. Phase to detect the phase difference value of the feedback clock phase generated by 4 kHz The microprocessor controller which collects the result data of the granting unit 13 and the phase comparator and generates a control signal of the voltage controlled crystal oscillator, wherein the phase comparison section is a state in which the reference clock 4 kHz and the feedback clock 4 kHz are "1". In the interval, divide the 38.88 MHz clock of the voltage controlled crystal oscillator into two and count up to 19.44 MHz. The counted up phase comparison is a 16-bit data value that allows the microprocessor to collect it. Then, the voltage control crystal oscillator unit 18 for generating a 38.88 MHz clock signal by the control data of the microprocessor controller and the division unit for dividing the 9720 clock signal of 38.88 MHz generated by the voltage control crystal oscillator controller ( 20).

4 is a detailed block diagram of the clock selector. The clock monitor 113 of the clock selector is composed of a plurality of shift registers 1130, a register 1131, and a circuit 1132 for generating a shift register erase signal. The 8 kHz synchronous reference clock received through the 10-bit buffer determines whether the clock is present through the shift register 1130. The microprocessor periodically receives the monitoring result for the synchronization reference clock from the register 1131. The circuit 1132 generates a shift register erase signal to initialize after the microprocessor reads the monitoring value or when the initial power is applied. If there is no synchronous reference clock signal until the microprocessor reads the monitoring value and then tries to read it again, the shift register 1130 transfers a "1" signal to the register 1131. If there is a signal of the synchronization reference clock, the shift register 1130 transfers a "0" signal to the register 1131. This results in the reference value required for the microprocessor to monitor the incoming sync reference clock. Using these results, the microprocessor allows the reference clock selection circuitry to select the reference clock. The 8 kHz clock signal selected by the reference clock selection circuit section is divided into two by the two dividing circuit to become a 4 kHz signal and input to the phase comparator.

The 4 kHz reference clock input by the above operation forms a phase comparison section with the 4 kHz reference clock divided by 9720 through the divider. Only phases that are “1” states with respect to the phase comparison 131 are used as counting intervals of the phase comparison counter 132. This section is called the phase comparison section and is counted using a 19.44 MHz signal input through the divider. The phase comparison counter can be up to 2430 and this counted phase comparison data is generated every 250 ms and passed to the microprocessor 15 using the 16-bit register bus 14. The phase comparison data delivered each time performs an internal processor operation as shown in FIG. 2.

The method of manipulator according to the present invention will be described in detail below with reference to FIG.

Initially, the reference clock selector monitors the received reference clock and selects the reference clock using the result value. The selected reference clock is selected from the fast mode and the normal mode by using the accumulated phase average value P generated by the phase comparison with the reference clock received from the voltage controlled crystal oscillator in the phase comparator of FIG. 1. Choose.

The first phase comparison value operates in a fast mode and accumulates an average of 512 phase comparison values. The cumulative average circuit value is calculated by using the following equation.

In = I _n-1 + BP;

W = I _n + BP;

The cumulative calculated value (W) is 100 times the cumulative calculated value outside the frequency limit control range (| 3Ec2 |) of -17 ppm to + 17 ppm of FIG. 3 before the cumulative calculated value is set before controlling the voltage controlled crystal oscillator. In the event of an error, a comparative analysis of the cumulative calculated value and the voltage-controlled crystal oscillator control value selects another reference clock that can be used without controlling the voltage-controlled crystal oscillator so as to no longer synchronize to the existing synchronous reference clock. Will perform the operation. If the cumulative calculated value is within the frequency control range, the 16-bit phase comparison data value, that is, the cumulative calculated value is converted into a data type suitable for operation in the digital / analog converter, and then transferred to the digital / analog converter. . In the digital-to-analog converter, voltage control is applied to a voltage controlled crystal oscillator to perform phase control for the network.

Table 1 shows the relationship between the frequency control range and the frequency control value in FIG. 3.

Frequency control range and frequency control value Frequency control Frequency control voltage Cumulative calculation Digital / Analog Transducer Values +35 ppm +5.0 volt + 7FFF h FFFF h +17 ppm +2.42857 volt + 3E2C h BE2C h 0 ppm 0 volt 0 h 8000 h -17 ppm -2.42857 volt -3E2C h 414D h 35 ppm -5.0 volt -7FFF h 0000 h

The voltage-controlled crystal oscillator uses a 16-bit digital-to-analog converter for control from the microprocessor. The frequency control voltage from -5 V to +5 V and the range of controlled frequencies range from -35 ppm to +35 ppm. Stability is 1 ppm / year. A detailed block diagram of the voltage controlled crystal oscillator is shown in FIG. 5.

Through the above process, the network synchronizer system can continuously supply a stable clock.

With the above configuration, the clock generator according to the present invention sets a control range by using a control value of a processor controlling a voltage controlled crystal oscillator (VCXO), and sets a reference input clock based on the set value. Beyond this frequency control range, a new clock can be selected to provide a stable network synchronizer clock.

Claims (6)

A reference clock selector 11 for selecting one reference clock from ten clocks by using the reference clock as information received from a microprocessor; A phase comparison unit (13) for detecting a phase difference value of a 4 kHz feedback clock phase generated by dividing a clock selected by the reference clock selection unit and a 38.88 MHz signal output from a voltage controlled crystal oscillator 9720; A microprocessor controller 15 which collects the result data of the phase comparator and generates a control signal of a voltage controlled crystal oscillator; A voltage controlled crystal oscillator unit 18 for generating a 38.88 MHz clock signal according to the control data of the microprocessor controller; And a divider unit 20 for dividing a clock signal of 38.88 MHz generated by the voltage controlled crystal oscillator unit 9720. The method of claim 1, wherein the reference clock selector, A clock monitoring circuit unit that performs a clock monitoring function, And a clock selector which selects a clock under the control of a microprocessor. The method of claim 1, wherein the phase comparison unit A phase comparator for detecting a phase difference between a 4 kHz reference clock received from the reference clock selector and a 4 kHz feedback clock divided by 9720 from a 38.88 MHz clock signal generated from a voltage controlled crystal oscillator; And a phase comparison counter for forming a phase comparison section in accordance with the result of the phase comparator. The oscillator of claim 1, wherein the voltage controlled oscillator A digital-analog converter for generating a control voltage for controlling the voltage controlled crystal oscillator; And a voltage controlled crystal oscillator for generating a clock of 38.88 MHz using a control voltage generated from said digital-analog converter. Monitoring the received reference clock and selecting a reference clock using the result value; Comparing a phase of the selected clock with a reference clock received from the voltage controlled crystal oscillator in the phase comparator; Selecting a fast mode and a normal mode by using the accumulated phase average value P generated through the phase comparison; And comparing and comparing the cumulative calculated value with the voltage controlled crystal oscillator control value. The method of claim 5, The first phase comparison value is operated in a high speed mode, and cumulative average of 512 phase comparison values is calculated to calculate the cumulative average value (W).