JPH02292924A - Synchronizer - Google Patents

Abstract

PURPOSE:To allow synchronizing pulse signals to coincide with each other in a short time by obtaining the time difference of synchronizing pulse signal output between a higher-order station and a controller and adjusting phases of synchronizing pulses by a reference pulse which is shifted by the difference with respect to time. CONSTITUTION:A period A from a time 61 when the higher-order station outputs a reference synchronizing pulse signal 25 to a time 67 when this station receives a synchronizing pulse signal 17 from a synchronizer is the first time difference. A first time difference signal indicating this time difference A is measured in the higher order station and is supplied to a higher order station information reception part 19. Meanwhile, a period B from a time 65 when the synchronizer outputs the synchronizing pulse signal 17 to a time 63 when the synchronizer receives the reference synchronizing pulse signal 25 is the second time difference. A second time difference 29 indicating this time difference B is obtained in a time difference measuring circuit 27. The first time difference A and the second time difference B are averaged to obtain an average value 43, thereby automatically controlling the phase deviation of the synchronizing pulse 17 to the reference synchronizing pulse 25.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization device that outputs a synchronization pulse signal.

[Conventional technology]

For example, when time-division multiplexing signals output from multiple stations, it is necessary to sample analog signals while synchronizing each station with each other. In the sampling synchronization method performed by each station, the mask station that outputs the reference synchronization signal is set as the upper station, and the output time of the synchronization pulse signal of the own station is made to match the output time of the reference synchronization pulse signal output by this upper station. There is a synchronization method.

FIG. 3 shows the configuration of a conventional synchronization device that performs such synchronization.

A fixed period, for example 4 MHz, from the clock signal output section 1l
The clock pulse signal 13 output from the synchronizer is frequency-divided by a frequency dividing circuit and output from the synchronizer as a synchronization pulse signal l7 output at a predetermined frame period, for example, 50 Hz. The synchronizing pulse signal 17 is supplied to other circuits (not shown), and synchronization is achieved based on this synchronizing pulse signal l7.

The synchronizer is an upper station information receiver that adjusts the phase of the synchronizing pulse signal 17 by detecting an output time difference based on a phase shift between the reference synchronizing pulse signal and the synchronizing pulse signal l7 output by another synchronizing device (not shown) of the upper station. section 19 and phase control section 21
It is equipped with The upper station information reception 819 is a first time difference signal representing a first time difference from outputting the reference synchronization pulse signal 25 at the upper station to receiving the synchronization pulse signal 17 output from the frequency dividing circuit 15. 23, and a reference synchronization pulse signal 25 that is transmitted from the upper station and arrives after a certain time delay.
receive. The time difference signal 23 representing the first time difference and the reference synchronization pulse signal 25 received by the upper station information receiving section l9 are output from the clock signal output section 11 together with the synchronization pulse signal 17 output from the frequency dividing circuit l5. A phase control section 21 that controls the phase of the clock pulse signal 13
is supplied to

The phase control section 21 has a time difference meter circuit 27,
A second time difference, which is the time difference between the time when the synchronization pulse signal 17 was output and the time when the reference synchronization pulse signal 25 was received, is determined, and a second time difference signal 29 is output. The second time difference signal 29 is supplied to a comparison circuit 31 together with the first time difference signal 23 received by the upper station information receiving section l9, and the comparison circuit 31 receives a comparison signal indicating the comparison result of the first time difference and the second time difference. 33 is supplied to an automatic phase control circuit 35. When the automatic phase control circuit 35 is supplied with the comparison signal 33 indicating that the first time difference is large, it controls the phase of the clock pulse signal l3 supplied to the frequency dividing circuit l5 to advance. Conversely, when the time difference signal 33 indicating that the second time difference is large is supplied to the automatic phase control circuit, the phase of the clock pulse signal 130 is controlled to be delayed.

Once the phase of the synchronization pulse signal 17 matches the phase of the reference synchronization pulse signal 25 of the upper station, there is little chance of a large deviation from then on, so the inspection is normally performed, for example, once every 24 frames. On the other hand, if the phase of the synchronizing pulse signal 17 deviates significantly for some reason, such as when starting up the device by turning on the power of the synchronizing device, the phase of the clock pulse signal 13 is controlled every frame and Synchronization is performed so that the phases match.

[Problem to be solved by the invention]

In this way, the synchronization pull-in time when the phase of the synchronization pulse signal is largely shifted is determined by the magnitude of the phase shift, that is, the time difference between the output of the synchronization pulse signal 17 and the output of the reference synchronization pulse signal 25, and the phase difference control unit. 210 control width and control frequency. The second time difference between the output of the synchronization pulse signal 17 and the output of the reference synchronization pulse signal 25 is determined by the frame period of the synchronization pulse signal l7, and is 1/2 of the maximum l frame period. The control width of the phase control section 21 is limited to the period of the clock pulse signal 13, and is in l-pulse units at the maximum. Further, the frequency of controlling the phase of the clock pulse signal 13 is limited to the frame period of the synchronizing pulse signal 17, and is controlled every frame at the shortest.

Therefore, at the time of starting up the synchronizer, etc., there are limitations due to these factors, and it takes a long time to bring the synchronization pulse signal into phase with the reference synchronization pulse signal.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a synchronization device that can match a synchronization pulse signal to a reference synchronization pulse signal output by a higher-level station in a short time.

[Means to solve the problem]

The synchronizer of the present invention includes (i) a clock signal output means for outputting a clock signal, and (l1) a synchronization pulse signal by dividing the clock signal output from the clock signal output means to a predetermined frequency division ratio. The frequency dividing circuit to be created and (iii
) A time difference signal that represents the time difference between the reference synchronization pulse signal that serves as the reference for synchronization output by the upper station, and the time when this upper station outputs the reference synchronization pulse signal and the time when the synchronization pulse signal created by the frequency divider circuit is received. and (iv) a clock signal output means based on the time difference signal and the upper station pulse signal received by the upper station information receiving means and the synchronization pulse signal created by the frequency dividing circuit. (v) time difference detection means for determining the time difference between the time when the synchronization pulse signal is output from the frequency dividing circuit and the time when the reference synchronization pulse signal is output from the upper station; , (vi) a pulse generation circuit that generates a pulse by shifting the time by the time difference determined by the control time difference detection means with respect to the synchronizing pulse signal output from the frequency dividing circuit, and supplies the pulse to the frequency dividing circuit. .

That is, in the synchronization device of the present invention, the reference synchronization pulse signal is output from the 11th and 20th time difference between the output of the reference synchronization pulse signal and the synchronization pulse signal outputted by the upper station until the reception of the other signal. A difference indicating the time difference between the time and the time when the synchronization pulse signal was output is determined. and,
The phase of the synchronizing pulse signal is adjusted based on a reference pulse signal that is output after being shifted in time by a difference with respect to the synchronizing pulse signal.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 1 is a block diagram showing the circuit configuration of a synchronizer according to an embodiment of the present invention. The same parts as in FIG. 3 are given the same reference numerals, and their explanation will be omitted as appropriate.

The synchronizer includes a control time difference detection section 41 that determines the output time difference between the output time of the reference synchronization pulse signal 25 and the output time of the synchronization pulse signal 17.

The control time difference detection unit 41 includes a time difference average value circuit 45 that calculates the average value of the first time difference 23 and the second time difference 29 and outputs the average value signal 43, and a time difference average value circuit 45 that calculates the average value of the first time difference 23 and the second time difference 29 and outputs the average value signal 43, a difference detection circuit 49 that calculates the absolute value of the difference between the time difference 29 and the second time difference and outputs a difference signal 47;
It is equipped with

The difference detection circuit 49 also determines the magnitude relationship between the average value and the second time difference. This control time difference detection section 4
1 operates upon receiving a power-on signal 53 from a power-on detection circuit 51 that detects power-on.

The synchronizer also includes a pulse generation circuit 55, which receives the difference determined by the control time difference detection 1641, shifts the output time of the synchronization pulse signal 17 by this difference, and outputs the reference pulse signal 55 to the frequency dividing circuit 15. It is designed to be supplied to

FIG. 2 shows the mutual output and reception timing of the synchronization signal 17 output from the synchronizer and the reference synchronization pulse signal 25 output from the upper station.

Next, the operation of the synchronizing device configured as described above will be explained using FIG. 2.

In FIG. 2, the horizontal axis indicates the passage of time. The reference synchronization pulse signal 25 output from the upper station at time 6l reaches the upper station information receiving section 19 at time 63 after being delayed by a predetermined time T. on the other hand,
Synchronization pulse signal l7 output from the synchronizer at time 65
similarly reaches the upper station at time 67 with a delay of time T.

The time A from when the upper station outputs the reference synchronization pulse signal 25 at time 61 to when it receives the synchronization pulse signal 17 from the synchronizer at time 67 is the first time difference.
A first time difference signal 23 indicating the time difference A is measured by the higher-level station and supplied to the higher-level station information receiving section 19. On the other hand, the time B from when the synchronizer outputs the synchronization pulse signal 17 at time 65 to when it receives the reference synchronization pulse signal 25 at time 63 is a second time difference, and the second time difference B indicates the second time difference B. A time difference 29 between the two times is determined by a time difference measuring circuit 27.

When the synchronizer is started up, the synchronization pulse signal 17 is asynchronous with respect to the reference synchronization pulse signal 25 of the upper station to be synchronized. When the power is turned on at startup, the power-on detection circuit 51 detects this and supplies a power-on signal 53 to the control time difference detection section 4l. The time difference averaging circuit 45 receives the power-on signal 53 and calculates the average value of the first time difference A and the second time difference B. The average value obtained by the time difference averaging circuit 45 is C in FIG. 2, and the average value signal 43 representing this average residue C is supplied to the difference detection circuit 49 together with the second time difference signal 29 representing the second time difference signal B. be done.

The difference detection circuit 49 determines the magnitude relationship between the average value C and the second time difference B and the absolute value of the difference, that is, 1B-CI, and sends a signal indicating the magnitude relationship and the difference signal 47 to the pulse generation circuit 55. supply to. The difference IB-CI obtained by the difference detection circuit 49 is the time difference between the time 69 when the frequency dividing circuit 15 outputs the synchronization pulse signal 17 and the time 61 when the reference synchronization pulse signal 25 is output from the upper station.

If the average value C is greater than or equal to the second time difference B, the pulse generating circuit 55 generates the difference signal 4 from time 65 when the synchronizing pulse signal l7 is output, as shown in FIG.
The reference pulse signal 57 is output at time 69 advanced by the difference IB-CI indicated by 7. Conversely, when the second time difference B is larger than the average value C, the pulse generation circuit 55 generates the difference IB-C1 indicated by the difference signal 47 from the time 65 when the synchronization pulse signal 17 is output, as shown in the opening of FIG. The reference pulse signal 57 is output at time 7l, which is delayed by the same amount.

This reference pulse signal 57 is supplied to the frequency dividing circuit 15.

The frequency dividing circuit 15 fixes the synchronization pulse signal l7 by performing synchronization pull-in based on the reference pulse signal 57. After the synchronization pulse signal l7 is fixed, the operation of the control time difference detection section 4l and the pulse generation circuit 55 is terminated. The small phase shift of the synchronization pulse signal 17 that occurs thereafter is
tE] The control circuit 2l and the upper station information receiving section 19 adjust in the same manner as in the conventional case.

In this way, since the average value 43 of the first time difference A and the second time difference B is obtained, it is possible to automatically control the displacement of the synchronization pulse signal 17 with respect to the reference synchronization pulse signal 25. .

In the embodiment described above, the difference indicating the difference between the time at which the upper station outputs the reference synchronization pulse signal and the time at which the control device outputs the synchronization pulse signal is determined by the time difference averaging circuit and the difference detection circuit. The present invention is not limited to this, and any circuit that calculates a value obtained by dividing the difference between the first time difference and the second time difference by 2 may be used.

Furthermore, in the embodiments described above, the power-on signal is manually input; therefore, the operation of the control time difference detection section is started and the reference pulse signal is output from the pulse generation circuit, but this is limited to when the power is turned on. Instead, for example, the control time difference detection section may constantly monitor the difference indicating the deviation of the reference pulse signal, and if the difference exceeds a predetermined value, the difference may be supplied to the pulse generation circuit to output the reference pulse signal. good.

〔Effect of the invention〕

As described above, according to the present invention, the difference representing the time difference between the time when the reference synchronization pulse signal is outputted by the host station and the time when the synchronization pulse signal is outputted by the control device is obtained, and the time difference is calculated by the difference with respect to the synchronization pulse signal. Since the configuration is such that the phase of the synchronization pulse signal is adjusted based on the reference pulse signal output in a shifted manner, the synchronization pulse signal can be made to coincide with the reference synchronization pulse signal output from the higher-level station in a short time.

[Brief explanation of the drawing]

Figures 1 and 2 are for explaining one embodiment of the present invention, of which Figure 1 is a block diagram showing the configuration of the synchronizer, and Figure 2A is a block diagram in which the average value is A timing diagram showing the output and reception timing of the synchronization signal output from the synchronizer and the reference synchronization pulse signal output from the upper station when the time difference between the two is greater than or equal to the time difference between the two. Figure 3 is a timing diagram showing the output and reception timing of the synchronization signal output from the synchronizer and the reference synchronization pulse signal output from the upper station when the average time difference between two shifts is larger than one shift. FIG. 2 is a block diagram showing the configuration of a synchronization device in block diagrams. 1l...Clock signal output section, 15...
・Frequency dividing circuit, l9...Upper station information receiving section, 2l
. . . Phase control section, 4l . . . Control time difference detection section, 55 . . . Pulse generation circuit. 1. Figure of horse 2.

Claims (1)

[Scope of Claims] A clock signal output means for outputting a clock signal; a frequency dividing circuit for dividing the clock signal output from the clock signal output means at a predetermined frequency division ratio to create a synchronous pulse signal; A reference synchronization pulse signal that serves as a reference for synchronization output by an upper station, and a time difference signal representing the time difference between the time when this upper station outputs the reference synchronization pulse signal and the time when the synchronization pulse signal created by the frequency dividing circuit is received. an upper station information receiving section that receives the upper station information, and the clock signal output means outputs based on the time difference signal and the upper station pulse signal received by the upper station information receiving means, and the synchronization pulse signal created by the frequency dividing circuit. a phase control unit that changes the phase of a clock pulse signal that is output from the frequency divider circuit; It is characterized by comprising a pulse generation circuit which generates a pulse by shifting the time by the time difference determined by the control time difference detection means with respect to the synchronization pulse signal outputted from the frequency dividing circuit and supplies it to the frequency dividing circuit. Synchronizer.